1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Leilk Liu <leilk.liu@mediatek.com>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/device.h>
9 #include <linux/err.h>
10 #include <linux/interrupt.h>
11 #include <linux/io.h>
12 #include <linux/ioport.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_gpio.h>
16 #include <linux/platform_device.h>
17 #include <linux/platform_data/spi-mt65xx.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/spi/spi.h>
20 #include <linux/dma-mapping.h>
21
22 #define SPI_CFG0_REG 0x0000
23 #define SPI_CFG1_REG 0x0004
24 #define SPI_TX_SRC_REG 0x0008
25 #define SPI_RX_DST_REG 0x000c
26 #define SPI_TX_DATA_REG 0x0010
27 #define SPI_RX_DATA_REG 0x0014
28 #define SPI_CMD_REG 0x0018
29 #define SPI_STATUS0_REG 0x001c
30 #define SPI_PAD_SEL_REG 0x0024
31 #define SPI_CFG2_REG 0x0028
32 #define SPI_TX_SRC_REG_64 0x002c
33 #define SPI_RX_DST_REG_64 0x0030
34
35 #define SPI_CFG0_SCK_HIGH_OFFSET 0
36 #define SPI_CFG0_SCK_LOW_OFFSET 8
37 #define SPI_CFG0_CS_HOLD_OFFSET 16
38 #define SPI_CFG0_CS_SETUP_OFFSET 24
39 #define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0
40 #define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16
41
42 #define SPI_CFG1_CS_IDLE_OFFSET 0
43 #define SPI_CFG1_PACKET_LOOP_OFFSET 8
44 #define SPI_CFG1_PACKET_LENGTH_OFFSET 16
45 #define SPI_CFG1_GET_TICK_DLY_OFFSET 29
46 #define SPI_CFG1_GET_TICK_DLY_OFFSET_V1 30
47
48 #define SPI_CFG1_GET_TICK_DLY_MASK 0xe0000000
49 #define SPI_CFG1_GET_TICK_DLY_MASK_V1 0xc0000000
50
51 #define SPI_CFG1_CS_IDLE_MASK 0xff
52 #define SPI_CFG1_PACKET_LOOP_MASK 0xff00
53 #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
54 #define SPI_CFG2_SCK_HIGH_OFFSET 0
55 #define SPI_CFG2_SCK_LOW_OFFSET 16
56
57 #define SPI_CMD_ACT BIT(0)
58 #define SPI_CMD_RESUME BIT(1)
59 #define SPI_CMD_RST BIT(2)
60 #define SPI_CMD_PAUSE_EN BIT(4)
61 #define SPI_CMD_DEASSERT BIT(5)
62 #define SPI_CMD_SAMPLE_SEL BIT(6)
63 #define SPI_CMD_CS_POL BIT(7)
64 #define SPI_CMD_CPHA BIT(8)
65 #define SPI_CMD_CPOL BIT(9)
66 #define SPI_CMD_RX_DMA BIT(10)
67 #define SPI_CMD_TX_DMA BIT(11)
68 #define SPI_CMD_TXMSBF BIT(12)
69 #define SPI_CMD_RXMSBF BIT(13)
70 #define SPI_CMD_RX_ENDIAN BIT(14)
71 #define SPI_CMD_TX_ENDIAN BIT(15)
72 #define SPI_CMD_FINISH_IE BIT(16)
73 #define SPI_CMD_PAUSE_IE BIT(17)
74
75 #define MT8173_SPI_MAX_PAD_SEL 3
76
77 #define MTK_SPI_PAUSE_INT_STATUS 0x2
78
79 #define MTK_SPI_IDLE 0
80 #define MTK_SPI_PAUSED 1
81
82 #define MTK_SPI_MAX_FIFO_SIZE 32U
83 #define MTK_SPI_PACKET_SIZE 1024
84 #define MTK_SPI_32BITS_MASK (0xffffffff)
85
86 #define DMA_ADDR_EXT_BITS (36)
87 #define DMA_ADDR_DEF_BITS (32)
88
89 struct mtk_spi_compatible {
90 bool need_pad_sel;
91 /* Must explicitly send dummy Tx bytes to do Rx only transfer */
92 bool must_tx;
93 /* some IC design adjust cfg register to enhance time accuracy */
94 bool enhance_timing;
95 /* some IC support DMA addr extension */
96 bool dma_ext;
97 /* some IC no need unprepare SPI clk */
98 bool no_need_unprepare;
99 };
100
101 struct mtk_spi {
102 void __iomem *base;
103 u32 state;
104 int pad_num;
105 u32 *pad_sel;
106 struct clk *parent_clk, *sel_clk, *spi_clk;
107 struct spi_transfer *cur_transfer;
108 u32 xfer_len;
109 u32 num_xfered;
110 struct scatterlist *tx_sgl, *rx_sgl;
111 u32 tx_sgl_len, rx_sgl_len;
112 const struct mtk_spi_compatible *dev_comp;
113 u32 spi_clk_hz;
114 };
115
116 static const struct mtk_spi_compatible mtk_common_compat;
117
118 static const struct mtk_spi_compatible mt2712_compat = {
119 .must_tx = true,
120 };
121
122 static const struct mtk_spi_compatible mt6765_compat = {
123 .need_pad_sel = true,
124 .must_tx = true,
125 .enhance_timing = true,
126 .dma_ext = true,
127 };
128
129 static const struct mtk_spi_compatible mt7622_compat = {
130 .must_tx = true,
131 .enhance_timing = true,
132 };
133
134 static const struct mtk_spi_compatible mt8173_compat = {
135 .need_pad_sel = true,
136 .must_tx = true,
137 };
138
139 static const struct mtk_spi_compatible mt8183_compat = {
140 .need_pad_sel = true,
141 .must_tx = true,
142 .enhance_timing = true,
143 };
144
145 static const struct mtk_spi_compatible mt6893_compat = {
146 .need_pad_sel = true,
147 .must_tx = true,
148 .enhance_timing = true,
149 .dma_ext = true,
150 .no_need_unprepare = true,
151 };
152
153 /*
154 * A piece of default chip info unless the platform
155 * supplies it.
156 */
157 static const struct mtk_chip_config mtk_default_chip_info = {
158 .sample_sel = 0,
159 .tick_delay = 0,
160 };
161
162 static const struct of_device_id mtk_spi_of_match[] = {
163 { .compatible = "mediatek,mt2701-spi",
164 .data = (void *)&mtk_common_compat,
165 },
166 { .compatible = "mediatek,mt2712-spi",
167 .data = (void *)&mt2712_compat,
168 },
169 { .compatible = "mediatek,mt6589-spi",
170 .data = (void *)&mtk_common_compat,
171 },
172 { .compatible = "mediatek,mt6765-spi",
173 .data = (void *)&mt6765_compat,
174 },
175 { .compatible = "mediatek,mt7622-spi",
176 .data = (void *)&mt7622_compat,
177 },
178 { .compatible = "mediatek,mt7629-spi",
179 .data = (void *)&mt7622_compat,
180 },
181 { .compatible = "mediatek,mt8135-spi",
182 .data = (void *)&mtk_common_compat,
183 },
184 { .compatible = "mediatek,mt8173-spi",
185 .data = (void *)&mt8173_compat,
186 },
187 { .compatible = "mediatek,mt8183-spi",
188 .data = (void *)&mt8183_compat,
189 },
190 { .compatible = "mediatek,mt8192-spi",
191 .data = (void *)&mt6765_compat,
192 },
193 { .compatible = "mediatek,mt6893-spi",
194 .data = (void *)&mt6893_compat,
195 },
196 {}
197 };
198 MODULE_DEVICE_TABLE(of, mtk_spi_of_match);
199
mtk_spi_reset(struct mtk_spi * mdata)200 static void mtk_spi_reset(struct mtk_spi *mdata)
201 {
202 u32 reg_val;
203
204 /* set the software reset bit in SPI_CMD_REG. */
205 reg_val = readl(mdata->base + SPI_CMD_REG);
206 reg_val |= SPI_CMD_RST;
207 writel(reg_val, mdata->base + SPI_CMD_REG);
208
209 reg_val = readl(mdata->base + SPI_CMD_REG);
210 reg_val &= ~SPI_CMD_RST;
211 writel(reg_val, mdata->base + SPI_CMD_REG);
212 }
213
mtk_spi_set_hw_cs_timing(struct spi_device * spi)214 static int mtk_spi_set_hw_cs_timing(struct spi_device *spi)
215 {
216 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
217 struct spi_delay *cs_setup = &spi->cs_setup;
218 struct spi_delay *cs_hold = &spi->cs_hold;
219 struct spi_delay *cs_inactive = &spi->cs_inactive;
220 u32 setup, hold, inactive;
221 u32 reg_val;
222 int delay;
223
224 delay = spi_delay_to_ns(cs_setup, NULL);
225 if (delay < 0)
226 return delay;
227 setup = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000;
228
229 delay = spi_delay_to_ns(cs_hold, NULL);
230 if (delay < 0)
231 return delay;
232 hold = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000;
233
234 delay = spi_delay_to_ns(cs_inactive, NULL);
235 if (delay < 0)
236 return delay;
237 inactive = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000;
238
239 if (hold || setup) {
240 reg_val = readl(mdata->base + SPI_CFG0_REG);
241 if (mdata->dev_comp->enhance_timing) {
242 if (hold) {
243 hold = min_t(u32, hold, 0x10000);
244 reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
245 reg_val |= (((hold - 1) & 0xffff)
246 << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
247 }
248 if (setup) {
249 setup = min_t(u32, setup, 0x10000);
250 reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
251 reg_val |= (((setup - 1) & 0xffff)
252 << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
253 }
254 } else {
255 if (hold) {
256 hold = min_t(u32, hold, 0x100);
257 reg_val &= ~(0xff << SPI_CFG0_CS_HOLD_OFFSET);
258 reg_val |= (((hold - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
259 }
260 if (setup) {
261 setup = min_t(u32, setup, 0x100);
262 reg_val &= ~(0xff << SPI_CFG0_CS_SETUP_OFFSET);
263 reg_val |= (((setup - 1) & 0xff)
264 << SPI_CFG0_CS_SETUP_OFFSET);
265 }
266 }
267 writel(reg_val, mdata->base + SPI_CFG0_REG);
268 }
269
270 if (inactive) {
271 inactive = min_t(u32, inactive, 0x100);
272 reg_val = readl(mdata->base + SPI_CFG1_REG);
273 reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
274 reg_val |= (((inactive - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
275 writel(reg_val, mdata->base + SPI_CFG1_REG);
276 }
277
278 return 0;
279 }
280
mtk_spi_prepare_message(struct spi_master * master,struct spi_message * msg)281 static int mtk_spi_prepare_message(struct spi_master *master,
282 struct spi_message *msg)
283 {
284 u16 cpha, cpol;
285 u32 reg_val;
286 struct spi_device *spi = msg->spi;
287 struct mtk_chip_config *chip_config = spi->controller_data;
288 struct mtk_spi *mdata = spi_master_get_devdata(master);
289
290 cpha = spi->mode & SPI_CPHA ? 1 : 0;
291 cpol = spi->mode & SPI_CPOL ? 1 : 0;
292
293 reg_val = readl(mdata->base + SPI_CMD_REG);
294 if (cpha)
295 reg_val |= SPI_CMD_CPHA;
296 else
297 reg_val &= ~SPI_CMD_CPHA;
298 if (cpol)
299 reg_val |= SPI_CMD_CPOL;
300 else
301 reg_val &= ~SPI_CMD_CPOL;
302
303 /* set the mlsbx and mlsbtx */
304 if (spi->mode & SPI_LSB_FIRST) {
305 reg_val &= ~SPI_CMD_TXMSBF;
306 reg_val &= ~SPI_CMD_RXMSBF;
307 } else {
308 reg_val |= SPI_CMD_TXMSBF;
309 reg_val |= SPI_CMD_RXMSBF;
310 }
311
312 /* set the tx/rx endian */
313 #ifdef __LITTLE_ENDIAN
314 reg_val &= ~SPI_CMD_TX_ENDIAN;
315 reg_val &= ~SPI_CMD_RX_ENDIAN;
316 #else
317 reg_val |= SPI_CMD_TX_ENDIAN;
318 reg_val |= SPI_CMD_RX_ENDIAN;
319 #endif
320
321 if (mdata->dev_comp->enhance_timing) {
322 /* set CS polarity */
323 if (spi->mode & SPI_CS_HIGH)
324 reg_val |= SPI_CMD_CS_POL;
325 else
326 reg_val &= ~SPI_CMD_CS_POL;
327
328 if (chip_config->sample_sel)
329 reg_val |= SPI_CMD_SAMPLE_SEL;
330 else
331 reg_val &= ~SPI_CMD_SAMPLE_SEL;
332 }
333
334 /* set finish and pause interrupt always enable */
335 reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE;
336
337 /* disable dma mode */
338 reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
339
340 /* disable deassert mode */
341 reg_val &= ~SPI_CMD_DEASSERT;
342
343 writel(reg_val, mdata->base + SPI_CMD_REG);
344
345 /* pad select */
346 if (mdata->dev_comp->need_pad_sel)
347 writel(mdata->pad_sel[spi->chip_select],
348 mdata->base + SPI_PAD_SEL_REG);
349
350 /* tick delay */
351 reg_val = readl(mdata->base + SPI_CFG1_REG);
352 if (mdata->dev_comp->enhance_timing) {
353 reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
354 reg_val |= ((chip_config->tick_delay & 0x7)
355 << SPI_CFG1_GET_TICK_DLY_OFFSET);
356 } else {
357 reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1;
358 reg_val |= ((chip_config->tick_delay & 0x3)
359 << SPI_CFG1_GET_TICK_DLY_OFFSET_V1);
360 }
361 writel(reg_val, mdata->base + SPI_CFG1_REG);
362
363 /* set hw cs timing */
364 mtk_spi_set_hw_cs_timing(spi);
365 return 0;
366 }
367
mtk_spi_set_cs(struct spi_device * spi,bool enable)368 static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
369 {
370 u32 reg_val;
371 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
372
373 if (spi->mode & SPI_CS_HIGH)
374 enable = !enable;
375
376 reg_val = readl(mdata->base + SPI_CMD_REG);
377 if (!enable) {
378 reg_val |= SPI_CMD_PAUSE_EN;
379 writel(reg_val, mdata->base + SPI_CMD_REG);
380 } else {
381 reg_val &= ~SPI_CMD_PAUSE_EN;
382 writel(reg_val, mdata->base + SPI_CMD_REG);
383 mdata->state = MTK_SPI_IDLE;
384 mtk_spi_reset(mdata);
385 }
386 }
387
mtk_spi_prepare_transfer(struct spi_master * master,struct spi_transfer * xfer)388 static void mtk_spi_prepare_transfer(struct spi_master *master,
389 struct spi_transfer *xfer)
390 {
391 u32 div, sck_time, reg_val;
392 struct mtk_spi *mdata = spi_master_get_devdata(master);
393
394 if (xfer->speed_hz < mdata->spi_clk_hz / 2)
395 div = DIV_ROUND_UP(mdata->spi_clk_hz, xfer->speed_hz);
396 else
397 div = 1;
398
399 sck_time = (div + 1) / 2;
400
401 if (mdata->dev_comp->enhance_timing) {
402 reg_val = readl(mdata->base + SPI_CFG2_REG);
403 reg_val &= ~(0xffff << SPI_CFG2_SCK_HIGH_OFFSET);
404 reg_val |= (((sck_time - 1) & 0xffff)
405 << SPI_CFG2_SCK_HIGH_OFFSET);
406 reg_val &= ~(0xffff << SPI_CFG2_SCK_LOW_OFFSET);
407 reg_val |= (((sck_time - 1) & 0xffff)
408 << SPI_CFG2_SCK_LOW_OFFSET);
409 writel(reg_val, mdata->base + SPI_CFG2_REG);
410 } else {
411 reg_val = readl(mdata->base + SPI_CFG0_REG);
412 reg_val &= ~(0xff << SPI_CFG0_SCK_HIGH_OFFSET);
413 reg_val |= (((sck_time - 1) & 0xff)
414 << SPI_CFG0_SCK_HIGH_OFFSET);
415 reg_val &= ~(0xff << SPI_CFG0_SCK_LOW_OFFSET);
416 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
417 writel(reg_val, mdata->base + SPI_CFG0_REG);
418 }
419 }
420
mtk_spi_setup_packet(struct spi_master * master)421 static void mtk_spi_setup_packet(struct spi_master *master)
422 {
423 u32 packet_size, packet_loop, reg_val;
424 struct mtk_spi *mdata = spi_master_get_devdata(master);
425
426 packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE);
427 packet_loop = mdata->xfer_len / packet_size;
428
429 reg_val = readl(mdata->base + SPI_CFG1_REG);
430 reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK);
431 reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
432 reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
433 writel(reg_val, mdata->base + SPI_CFG1_REG);
434 }
435
mtk_spi_enable_transfer(struct spi_master * master)436 static void mtk_spi_enable_transfer(struct spi_master *master)
437 {
438 u32 cmd;
439 struct mtk_spi *mdata = spi_master_get_devdata(master);
440
441 cmd = readl(mdata->base + SPI_CMD_REG);
442 if (mdata->state == MTK_SPI_IDLE)
443 cmd |= SPI_CMD_ACT;
444 else
445 cmd |= SPI_CMD_RESUME;
446 writel(cmd, mdata->base + SPI_CMD_REG);
447 }
448
mtk_spi_get_mult_delta(u32 xfer_len)449 static int mtk_spi_get_mult_delta(u32 xfer_len)
450 {
451 u32 mult_delta;
452
453 if (xfer_len > MTK_SPI_PACKET_SIZE)
454 mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
455 else
456 mult_delta = 0;
457
458 return mult_delta;
459 }
460
mtk_spi_update_mdata_len(struct spi_master * master)461 static void mtk_spi_update_mdata_len(struct spi_master *master)
462 {
463 int mult_delta;
464 struct mtk_spi *mdata = spi_master_get_devdata(master);
465
466 if (mdata->tx_sgl_len && mdata->rx_sgl_len) {
467 if (mdata->tx_sgl_len > mdata->rx_sgl_len) {
468 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
469 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
470 mdata->rx_sgl_len = mult_delta;
471 mdata->tx_sgl_len -= mdata->xfer_len;
472 } else {
473 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
474 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
475 mdata->tx_sgl_len = mult_delta;
476 mdata->rx_sgl_len -= mdata->xfer_len;
477 }
478 } else if (mdata->tx_sgl_len) {
479 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
480 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
481 mdata->tx_sgl_len = mult_delta;
482 } else if (mdata->rx_sgl_len) {
483 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
484 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
485 mdata->rx_sgl_len = mult_delta;
486 }
487 }
488
mtk_spi_setup_dma_addr(struct spi_master * master,struct spi_transfer * xfer)489 static void mtk_spi_setup_dma_addr(struct spi_master *master,
490 struct spi_transfer *xfer)
491 {
492 struct mtk_spi *mdata = spi_master_get_devdata(master);
493
494 if (mdata->tx_sgl) {
495 writel((u32)(xfer->tx_dma & MTK_SPI_32BITS_MASK),
496 mdata->base + SPI_TX_SRC_REG);
497 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
498 if (mdata->dev_comp->dma_ext)
499 writel((u32)(xfer->tx_dma >> 32),
500 mdata->base + SPI_TX_SRC_REG_64);
501 #endif
502 }
503
504 if (mdata->rx_sgl) {
505 writel((u32)(xfer->rx_dma & MTK_SPI_32BITS_MASK),
506 mdata->base + SPI_RX_DST_REG);
507 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
508 if (mdata->dev_comp->dma_ext)
509 writel((u32)(xfer->rx_dma >> 32),
510 mdata->base + SPI_RX_DST_REG_64);
511 #endif
512 }
513 }
514
mtk_spi_fifo_transfer(struct spi_master * master,struct spi_device * spi,struct spi_transfer * xfer)515 static int mtk_spi_fifo_transfer(struct spi_master *master,
516 struct spi_device *spi,
517 struct spi_transfer *xfer)
518 {
519 int cnt, remainder;
520 u32 reg_val;
521 struct mtk_spi *mdata = spi_master_get_devdata(master);
522
523 mdata->cur_transfer = xfer;
524 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len);
525 mdata->num_xfered = 0;
526 mtk_spi_prepare_transfer(master, xfer);
527 mtk_spi_setup_packet(master);
528
529 if (xfer->tx_buf) {
530 cnt = xfer->len / 4;
531 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
532 remainder = xfer->len % 4;
533 if (remainder > 0) {
534 reg_val = 0;
535 memcpy(®_val, xfer->tx_buf + (cnt * 4), remainder);
536 writel(reg_val, mdata->base + SPI_TX_DATA_REG);
537 }
538 }
539
540 mtk_spi_enable_transfer(master);
541
542 return 1;
543 }
544
mtk_spi_dma_transfer(struct spi_master * master,struct spi_device * spi,struct spi_transfer * xfer)545 static int mtk_spi_dma_transfer(struct spi_master *master,
546 struct spi_device *spi,
547 struct spi_transfer *xfer)
548 {
549 int cmd;
550 struct mtk_spi *mdata = spi_master_get_devdata(master);
551
552 mdata->tx_sgl = NULL;
553 mdata->rx_sgl = NULL;
554 mdata->tx_sgl_len = 0;
555 mdata->rx_sgl_len = 0;
556 mdata->cur_transfer = xfer;
557 mdata->num_xfered = 0;
558
559 mtk_spi_prepare_transfer(master, xfer);
560
561 cmd = readl(mdata->base + SPI_CMD_REG);
562 if (xfer->tx_buf)
563 cmd |= SPI_CMD_TX_DMA;
564 if (xfer->rx_buf)
565 cmd |= SPI_CMD_RX_DMA;
566 writel(cmd, mdata->base + SPI_CMD_REG);
567
568 if (xfer->tx_buf)
569 mdata->tx_sgl = xfer->tx_sg.sgl;
570 if (xfer->rx_buf)
571 mdata->rx_sgl = xfer->rx_sg.sgl;
572
573 if (mdata->tx_sgl) {
574 xfer->tx_dma = sg_dma_address(mdata->tx_sgl);
575 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
576 }
577 if (mdata->rx_sgl) {
578 xfer->rx_dma = sg_dma_address(mdata->rx_sgl);
579 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
580 }
581
582 mtk_spi_update_mdata_len(master);
583 mtk_spi_setup_packet(master);
584 mtk_spi_setup_dma_addr(master, xfer);
585 mtk_spi_enable_transfer(master);
586
587 return 1;
588 }
589
mtk_spi_transfer_one(struct spi_master * master,struct spi_device * spi,struct spi_transfer * xfer)590 static int mtk_spi_transfer_one(struct spi_master *master,
591 struct spi_device *spi,
592 struct spi_transfer *xfer)
593 {
594 if (master->can_dma(master, spi, xfer))
595 return mtk_spi_dma_transfer(master, spi, xfer);
596 else
597 return mtk_spi_fifo_transfer(master, spi, xfer);
598 }
599
mtk_spi_can_dma(struct spi_master * master,struct spi_device * spi,struct spi_transfer * xfer)600 static bool mtk_spi_can_dma(struct spi_master *master,
601 struct spi_device *spi,
602 struct spi_transfer *xfer)
603 {
604 /* Buffers for DMA transactions must be 4-byte aligned */
605 return (xfer->len > MTK_SPI_MAX_FIFO_SIZE &&
606 (unsigned long)xfer->tx_buf % 4 == 0 &&
607 (unsigned long)xfer->rx_buf % 4 == 0);
608 }
609
mtk_spi_setup(struct spi_device * spi)610 static int mtk_spi_setup(struct spi_device *spi)
611 {
612 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
613
614 if (!spi->controller_data)
615 spi->controller_data = (void *)&mtk_default_chip_info;
616
617 if (mdata->dev_comp->need_pad_sel && gpio_is_valid(spi->cs_gpio))
618 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
619
620 return 0;
621 }
622
mtk_spi_interrupt(int irq,void * dev_id)623 static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
624 {
625 u32 cmd, reg_val, cnt, remainder, len;
626 struct spi_master *master = dev_id;
627 struct mtk_spi *mdata = spi_master_get_devdata(master);
628 struct spi_transfer *trans = mdata->cur_transfer;
629
630 reg_val = readl(mdata->base + SPI_STATUS0_REG);
631 if (reg_val & MTK_SPI_PAUSE_INT_STATUS)
632 mdata->state = MTK_SPI_PAUSED;
633 else
634 mdata->state = MTK_SPI_IDLE;
635
636 if (!master->can_dma(master, NULL, trans)) {
637 if (trans->rx_buf) {
638 cnt = mdata->xfer_len / 4;
639 ioread32_rep(mdata->base + SPI_RX_DATA_REG,
640 trans->rx_buf + mdata->num_xfered, cnt);
641 remainder = mdata->xfer_len % 4;
642 if (remainder > 0) {
643 reg_val = readl(mdata->base + SPI_RX_DATA_REG);
644 memcpy(trans->rx_buf +
645 mdata->num_xfered +
646 (cnt * 4),
647 ®_val,
648 remainder);
649 }
650 }
651
652 mdata->num_xfered += mdata->xfer_len;
653 if (mdata->num_xfered == trans->len) {
654 spi_finalize_current_transfer(master);
655 return IRQ_HANDLED;
656 }
657
658 len = trans->len - mdata->num_xfered;
659 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, len);
660 mtk_spi_setup_packet(master);
661
662 cnt = mdata->xfer_len / 4;
663 iowrite32_rep(mdata->base + SPI_TX_DATA_REG,
664 trans->tx_buf + mdata->num_xfered, cnt);
665
666 remainder = mdata->xfer_len % 4;
667 if (remainder > 0) {
668 reg_val = 0;
669 memcpy(®_val,
670 trans->tx_buf + (cnt * 4) + mdata->num_xfered,
671 remainder);
672 writel(reg_val, mdata->base + SPI_TX_DATA_REG);
673 }
674
675 mtk_spi_enable_transfer(master);
676
677 return IRQ_HANDLED;
678 }
679
680 if (mdata->tx_sgl)
681 trans->tx_dma += mdata->xfer_len;
682 if (mdata->rx_sgl)
683 trans->rx_dma += mdata->xfer_len;
684
685 if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) {
686 mdata->tx_sgl = sg_next(mdata->tx_sgl);
687 if (mdata->tx_sgl) {
688 trans->tx_dma = sg_dma_address(mdata->tx_sgl);
689 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
690 }
691 }
692 if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) {
693 mdata->rx_sgl = sg_next(mdata->rx_sgl);
694 if (mdata->rx_sgl) {
695 trans->rx_dma = sg_dma_address(mdata->rx_sgl);
696 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
697 }
698 }
699
700 if (!mdata->tx_sgl && !mdata->rx_sgl) {
701 /* spi disable dma */
702 cmd = readl(mdata->base + SPI_CMD_REG);
703 cmd &= ~SPI_CMD_TX_DMA;
704 cmd &= ~SPI_CMD_RX_DMA;
705 writel(cmd, mdata->base + SPI_CMD_REG);
706
707 spi_finalize_current_transfer(master);
708 return IRQ_HANDLED;
709 }
710
711 mtk_spi_update_mdata_len(master);
712 mtk_spi_setup_packet(master);
713 mtk_spi_setup_dma_addr(master, trans);
714 mtk_spi_enable_transfer(master);
715
716 return IRQ_HANDLED;
717 }
718
mtk_spi_probe(struct platform_device * pdev)719 static int mtk_spi_probe(struct platform_device *pdev)
720 {
721 struct spi_master *master;
722 struct mtk_spi *mdata;
723 const struct of_device_id *of_id;
724 int i, irq, ret, addr_bits;
725
726 master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
727 if (!master) {
728 dev_err(&pdev->dev, "failed to alloc spi master\n");
729 return -ENOMEM;
730 }
731
732 master->auto_runtime_pm = true;
733 master->dev.of_node = pdev->dev.of_node;
734 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
735
736 master->set_cs = mtk_spi_set_cs;
737 master->prepare_message = mtk_spi_prepare_message;
738 master->transfer_one = mtk_spi_transfer_one;
739 master->can_dma = mtk_spi_can_dma;
740 master->setup = mtk_spi_setup;
741 master->set_cs_timing = mtk_spi_set_hw_cs_timing;
742
743 of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
744 if (!of_id) {
745 dev_err(&pdev->dev, "failed to probe of_node\n");
746 ret = -EINVAL;
747 goto err_put_master;
748 }
749
750 mdata = spi_master_get_devdata(master);
751 mdata->dev_comp = of_id->data;
752
753 if (mdata->dev_comp->enhance_timing)
754 master->mode_bits |= SPI_CS_HIGH;
755
756 if (mdata->dev_comp->must_tx)
757 master->flags = SPI_MASTER_MUST_TX;
758
759 if (mdata->dev_comp->need_pad_sel) {
760 mdata->pad_num = of_property_count_u32_elems(
761 pdev->dev.of_node,
762 "mediatek,pad-select");
763 if (mdata->pad_num < 0) {
764 dev_err(&pdev->dev,
765 "No 'mediatek,pad-select' property\n");
766 ret = -EINVAL;
767 goto err_put_master;
768 }
769
770 mdata->pad_sel = devm_kmalloc_array(&pdev->dev, mdata->pad_num,
771 sizeof(u32), GFP_KERNEL);
772 if (!mdata->pad_sel) {
773 ret = -ENOMEM;
774 goto err_put_master;
775 }
776
777 for (i = 0; i < mdata->pad_num; i++) {
778 of_property_read_u32_index(pdev->dev.of_node,
779 "mediatek,pad-select",
780 i, &mdata->pad_sel[i]);
781 if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) {
782 dev_err(&pdev->dev, "wrong pad-sel[%d]: %u\n",
783 i, mdata->pad_sel[i]);
784 ret = -EINVAL;
785 goto err_put_master;
786 }
787 }
788 }
789
790 platform_set_drvdata(pdev, master);
791 mdata->base = devm_platform_ioremap_resource(pdev, 0);
792 if (IS_ERR(mdata->base)) {
793 ret = PTR_ERR(mdata->base);
794 goto err_put_master;
795 }
796
797 irq = platform_get_irq(pdev, 0);
798 if (irq < 0) {
799 ret = irq;
800 goto err_put_master;
801 }
802
803 if (!pdev->dev.dma_mask)
804 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
805
806 ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt,
807 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master);
808 if (ret) {
809 dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
810 goto err_put_master;
811 }
812
813 mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk");
814 if (IS_ERR(mdata->parent_clk)) {
815 ret = PTR_ERR(mdata->parent_clk);
816 dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret);
817 goto err_put_master;
818 }
819
820 mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk");
821 if (IS_ERR(mdata->sel_clk)) {
822 ret = PTR_ERR(mdata->sel_clk);
823 dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret);
824 goto err_put_master;
825 }
826
827 mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk");
828 if (IS_ERR(mdata->spi_clk)) {
829 ret = PTR_ERR(mdata->spi_clk);
830 dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
831 goto err_put_master;
832 }
833
834 ret = clk_prepare_enable(mdata->spi_clk);
835 if (ret < 0) {
836 dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
837 goto err_put_master;
838 }
839
840 ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
841 if (ret < 0) {
842 dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
843 clk_disable_unprepare(mdata->spi_clk);
844 goto err_put_master;
845 }
846
847 mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk);
848
849 if (mdata->dev_comp->no_need_unprepare)
850 clk_disable(mdata->spi_clk);
851 else
852 clk_disable_unprepare(mdata->spi_clk);
853
854 pm_runtime_enable(&pdev->dev);
855
856 if (mdata->dev_comp->need_pad_sel) {
857 if (mdata->pad_num != master->num_chipselect) {
858 dev_err(&pdev->dev,
859 "pad_num does not match num_chipselect(%d != %d)\n",
860 mdata->pad_num, master->num_chipselect);
861 ret = -EINVAL;
862 goto err_disable_runtime_pm;
863 }
864
865 if (!master->cs_gpios && master->num_chipselect > 1) {
866 dev_err(&pdev->dev,
867 "cs_gpios not specified and num_chipselect > 1\n");
868 ret = -EINVAL;
869 goto err_disable_runtime_pm;
870 }
871
872 if (master->cs_gpios) {
873 for (i = 0; i < master->num_chipselect; i++) {
874 ret = devm_gpio_request(&pdev->dev,
875 master->cs_gpios[i],
876 dev_name(&pdev->dev));
877 if (ret) {
878 dev_err(&pdev->dev,
879 "can't get CS GPIO %i\n", i);
880 goto err_disable_runtime_pm;
881 }
882 }
883 }
884 }
885
886 if (mdata->dev_comp->dma_ext)
887 addr_bits = DMA_ADDR_EXT_BITS;
888 else
889 addr_bits = DMA_ADDR_DEF_BITS;
890 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(addr_bits));
891 if (ret)
892 dev_notice(&pdev->dev, "SPI dma_set_mask(%d) failed, ret:%d\n",
893 addr_bits, ret);
894
895 ret = devm_spi_register_master(&pdev->dev, master);
896 if (ret) {
897 dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
898 goto err_disable_runtime_pm;
899 }
900
901 return 0;
902
903 err_disable_runtime_pm:
904 pm_runtime_disable(&pdev->dev);
905 err_put_master:
906 spi_master_put(master);
907
908 return ret;
909 }
910
mtk_spi_remove(struct platform_device * pdev)911 static int mtk_spi_remove(struct platform_device *pdev)
912 {
913 struct spi_master *master = platform_get_drvdata(pdev);
914 struct mtk_spi *mdata = spi_master_get_devdata(master);
915 int ret;
916
917 ret = pm_runtime_resume_and_get(&pdev->dev);
918 if (ret < 0)
919 return ret;
920
921 mtk_spi_reset(mdata);
922
923 if (mdata->dev_comp->no_need_unprepare)
924 clk_unprepare(mdata->spi_clk);
925
926 pm_runtime_put_noidle(&pdev->dev);
927 pm_runtime_disable(&pdev->dev);
928
929 return 0;
930 }
931
932 #ifdef CONFIG_PM_SLEEP
mtk_spi_suspend(struct device * dev)933 static int mtk_spi_suspend(struct device *dev)
934 {
935 int ret;
936 struct spi_master *master = dev_get_drvdata(dev);
937 struct mtk_spi *mdata = spi_master_get_devdata(master);
938
939 ret = spi_master_suspend(master);
940 if (ret)
941 return ret;
942
943 if (!pm_runtime_suspended(dev))
944 clk_disable_unprepare(mdata->spi_clk);
945
946 return ret;
947 }
948
mtk_spi_resume(struct device * dev)949 static int mtk_spi_resume(struct device *dev)
950 {
951 int ret;
952 struct spi_master *master = dev_get_drvdata(dev);
953 struct mtk_spi *mdata = spi_master_get_devdata(master);
954
955 if (!pm_runtime_suspended(dev)) {
956 ret = clk_prepare_enable(mdata->spi_clk);
957 if (ret < 0) {
958 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
959 return ret;
960 }
961 }
962
963 ret = spi_master_resume(master);
964 if (ret < 0)
965 clk_disable_unprepare(mdata->spi_clk);
966
967 return ret;
968 }
969 #endif /* CONFIG_PM_SLEEP */
970
971 #ifdef CONFIG_PM
mtk_spi_runtime_suspend(struct device * dev)972 static int mtk_spi_runtime_suspend(struct device *dev)
973 {
974 struct spi_master *master = dev_get_drvdata(dev);
975 struct mtk_spi *mdata = spi_master_get_devdata(master);
976
977 if (mdata->dev_comp->no_need_unprepare)
978 clk_disable(mdata->spi_clk);
979 else
980 clk_disable_unprepare(mdata->spi_clk);
981
982 return 0;
983 }
984
mtk_spi_runtime_resume(struct device * dev)985 static int mtk_spi_runtime_resume(struct device *dev)
986 {
987 struct spi_master *master = dev_get_drvdata(dev);
988 struct mtk_spi *mdata = spi_master_get_devdata(master);
989 int ret;
990
991 if (mdata->dev_comp->no_need_unprepare)
992 ret = clk_enable(mdata->spi_clk);
993 else
994 ret = clk_prepare_enable(mdata->spi_clk);
995 if (ret < 0) {
996 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
997 return ret;
998 }
999
1000 return 0;
1001 }
1002 #endif /* CONFIG_PM */
1003
1004 static const struct dev_pm_ops mtk_spi_pm = {
1005 SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume)
1006 SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend,
1007 mtk_spi_runtime_resume, NULL)
1008 };
1009
1010 static struct platform_driver mtk_spi_driver = {
1011 .driver = {
1012 .name = "mtk-spi",
1013 .pm = &mtk_spi_pm,
1014 .of_match_table = mtk_spi_of_match,
1015 },
1016 .probe = mtk_spi_probe,
1017 .remove = mtk_spi_remove,
1018 };
1019
1020 module_platform_driver(mtk_spi_driver);
1021
1022 MODULE_DESCRIPTION("MTK SPI Controller driver");
1023 MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
1024 MODULE_LICENSE("GPL v2");
1025 MODULE_ALIAS("platform:mtk-spi");
1026