1#include <dt-bindings/interrupt-controller/mips-gic.h> 2#include <dt-bindings/gpio/gpio.h> 3#include <dt-bindings/clock/mt7621-clk.h> 4 5/ { 6 #address-cells = <1>; 7 #size-cells = <1>; 8 compatible = "mediatek,mt7621-soc"; 9 10 cpus { 11 cpu@0 { 12 compatible = "mips,mips1004Kc"; 13 }; 14 15 cpu@1 { 16 compatible = "mips,mips1004Kc"; 17 }; 18 }; 19 20 cpuintc: cpuintc@0 { 21 #address-cells = <0>; 22 #interrupt-cells = <1>; 23 interrupt-controller; 24 compatible = "mti,cpu-interrupt-controller"; 25 }; 26 27 aliases { 28 serial0 = &uartlite; 29 }; 30 31 32 mmc_fixed_3v3: fixedregulator@0 { 33 compatible = "regulator-fixed"; 34 regulator-name = "mmc_power"; 35 regulator-min-microvolt = <3300000>; 36 regulator-max-microvolt = <3300000>; 37 enable-active-high; 38 regulator-always-on; 39 }; 40 41 mmc_fixed_1v8_io: fixedregulator@1 { 42 compatible = "regulator-fixed"; 43 regulator-name = "mmc_io"; 44 regulator-min-microvolt = <1800000>; 45 regulator-max-microvolt = <1800000>; 46 enable-active-high; 47 regulator-always-on; 48 }; 49 50 palmbus: palmbus@1e000000 { 51 compatible = "palmbus"; 52 reg = <0x1e000000 0x100000>; 53 ranges = <0x0 0x1e000000 0x0fffff>; 54 55 #address-cells = <1>; 56 #size-cells = <1>; 57 58 sysc: syscon@0 { 59 compatible = "mediatek,mt7621-sysc", "syscon"; 60 reg = <0x0 0x100>; 61 #clock-cells = <1>; 62 ralink,memctl = <&memc>; 63 clock-output-names = "xtal", "cpu", "bus", 64 "50m", "125m", "150m", 65 "250m", "270m"; 66 }; 67 68 wdt: wdt@100 { 69 compatible = "mediatek,mt7621-wdt"; 70 reg = <0x100 0x100>; 71 }; 72 73 gpio: gpio@600 { 74 #gpio-cells = <2>; 75 #interrupt-cells = <2>; 76 compatible = "mediatek,mt7621-gpio"; 77 gpio-controller; 78 gpio-ranges = <&pinctrl 0 0 95>; 79 interrupt-controller; 80 reg = <0x600 0x100>; 81 interrupt-parent = <&gic>; 82 interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>; 83 }; 84 85 i2c: i2c@900 { 86 compatible = "mediatek,mt7621-i2c"; 87 reg = <0x900 0x100>; 88 89 clocks = <&sysc MT7621_CLK_I2C>; 90 clock-names = "i2c"; 91 resets = <&rstctrl 16>; 92 reset-names = "i2c"; 93 94 #address-cells = <1>; 95 #size-cells = <0>; 96 97 status = "disabled"; 98 99 pinctrl-names = "default"; 100 pinctrl-0 = <&i2c_pins>; 101 }; 102 103 i2s: i2s@a00 { 104 compatible = "mediatek,mt7621-i2s"; 105 reg = <0xa00 0x100>; 106 107 clocks = <&sysc MT7621_CLK_I2S>; 108 clock-names = "i2s"; 109 resets = <&rstctrl 17>; 110 reset-names = "i2s"; 111 112 interrupt-parent = <&gic>; 113 interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>; 114 115 txdma-req = <2>; 116 rxdma-req = <3>; 117 118 dmas = <&gdma 4>, 119 <&gdma 6>; 120 dma-names = "tx", "rx"; 121 122 status = "disabled"; 123 }; 124 125 memc: syscon@5000 { 126 compatible = "mediatek,mt7621-memc", "syscon"; 127 reg = <0x5000 0x1000>; 128 }; 129 130 cpc: cpc@1fbf0000 { 131 compatible = "mediatek,mt7621-cpc"; 132 reg = <0x1fbf0000 0x8000>; 133 }; 134 135 mc: mc@1fbf8000 { 136 compatible = "mediatek,mt7621-mc"; 137 reg = <0x1fbf8000 0x8000>; 138 }; 139 140 uartlite: uartlite@c00 { 141 compatible = "ns16550a"; 142 reg = <0xc00 0x100>; 143 144 clocks = <&sysc MT7621_CLK_UART1>; 145 clock-names = "uart1"; 146 147 interrupt-parent = <&gic>; 148 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>; 149 150 reg-shift = <2>; 151 reg-io-width = <4>; 152 no-loopback-test; 153 }; 154 155 spi0: spi@b00 { 156 status = "disabled"; 157 158 compatible = "ralink,mt7621-spi"; 159 reg = <0xb00 0x100>; 160 161 clocks = <&sysc MT7621_CLK_SPI>; 162 clock-names = "spi"; 163 164 resets = <&rstctrl 18>; 165 reset-names = "spi"; 166 167 #address-cells = <1>; 168 #size-cells = <0>; 169 170 pinctrl-names = "default"; 171 pinctrl-0 = <&spi_pins>; 172 }; 173 174 gdma: gdma@2800 { 175 compatible = "ralink,rt3883-gdma"; 176 reg = <0x2800 0x800>; 177 178 clocks = <&sysc MT7621_CLK_GDMA>; 179 clock-names = "gdma"; 180 resets = <&rstctrl 14>; 181 reset-names = "dma"; 182 183 interrupt-parent = <&gic>; 184 interrupts = <0 13 4>; 185 186 #dma-cells = <1>; 187 #dma-channels = <16>; 188 #dma-requests = <16>; 189 190 status = "disabled"; 191 }; 192 193 hsdma: hsdma@7000 { 194 compatible = "mediatek,mt7621-hsdma"; 195 reg = <0x7000 0x1000>; 196 197 clocks = <&sysc MT7621_CLK_HSDMA>; 198 clock-names = "hsdma"; 199 resets = <&rstctrl 5>; 200 reset-names = "hsdma"; 201 202 interrupt-parent = <&gic>; 203 interrupts = <0 11 4>; 204 205 #dma-cells = <1>; 206 #dma-channels = <1>; 207 #dma-requests = <1>; 208 209 status = "disabled"; 210 }; 211 }; 212 213 pinctrl: pinctrl { 214 compatible = "ralink,rt2880-pinmux"; 215 216 i2c_pins: i2c0-pins { 217 pinmux { 218 groups = "i2c"; 219 function = "i2c"; 220 }; 221 }; 222 223 spi_pins: spi0-pins { 224 pinmux { 225 groups = "spi"; 226 function = "spi"; 227 }; 228 }; 229 230 uart1_pins: uart1-pins { 231 pinmux { 232 groups = "uart1"; 233 function = "uart1"; 234 }; 235 }; 236 237 uart2_pins: uart2-pins { 238 pinmux { 239 groups = "uart2"; 240 function = "uart2"; 241 }; 242 }; 243 244 uart3_pins: uart3-pins { 245 pinmux { 246 groups = "uart3"; 247 function = "uart3"; 248 }; 249 }; 250 251 rgmii1_pins: rgmii1-pins { 252 pinmux { 253 groups = "rgmii1"; 254 function = "rgmii1"; 255 }; 256 }; 257 258 rgmii2_pins: rgmii2-pins { 259 pinmux { 260 groups = "rgmii2"; 261 function = "rgmii2"; 262 }; 263 }; 264 265 mdio_pins: mdio0-pins { 266 pinmux { 267 groups = "mdio"; 268 function = "mdio"; 269 }; 270 }; 271 272 pcie_pins: pcie0-pins { 273 pinmux { 274 groups = "pcie"; 275 function = "gpio"; 276 }; 277 }; 278 279 nand_pins: nand0-pins { 280 spi-pinmux { 281 groups = "spi"; 282 function = "nand1"; 283 }; 284 285 sdhci-pinmux { 286 groups = "sdhci"; 287 function = "nand2"; 288 }; 289 }; 290 291 sdhci_pins: sdhci0-pins { 292 pinmux { 293 groups = "sdhci"; 294 function = "sdhci"; 295 }; 296 }; 297 }; 298 299 rstctrl: rstctrl { 300 compatible = "ralink,rt2880-reset"; 301 #reset-cells = <1>; 302 }; 303 304 sdhci: sdhci@1e130000 { 305 status = "disabled"; 306 307 compatible = "mediatek,mt7620-mmc"; 308 reg = <0x1e130000 0x4000>; 309 310 bus-width = <4>; 311 max-frequency = <48000000>; 312 cap-sd-highspeed; 313 cap-mmc-highspeed; 314 vmmc-supply = <&mmc_fixed_3v3>; 315 vqmmc-supply = <&mmc_fixed_1v8_io>; 316 disable-wp; 317 318 pinctrl-names = "default", "state_uhs"; 319 pinctrl-0 = <&sdhci_pins>; 320 pinctrl-1 = <&sdhci_pins>; 321 322 clocks = <&sysc MT7621_CLK_SHXC>, 323 <&sysc MT7621_CLK_50M>; 324 clock-names = "source", "hclk"; 325 326 interrupt-parent = <&gic>; 327 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>; 328 }; 329 330 xhci: xhci@1e1c0000 { 331 status = "okay"; 332 333 compatible = "mediatek,mt8173-xhci"; 334 reg = <0x1e1c0000 0x1000 335 0x1e1d0700 0x0100>; 336 reg-names = "mac", "ippc"; 337 338 clocks = <&sysc MT7621_CLK_XTAL>; 339 clock-names = "sys_ck"; 340 341 interrupt-parent = <&gic>; 342 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>; 343 }; 344 345 gic: interrupt-controller@1fbc0000 { 346 compatible = "mti,gic"; 347 reg = <0x1fbc0000 0x2000>; 348 349 interrupt-controller; 350 #interrupt-cells = <3>; 351 352 mti,reserved-cpu-vectors = <7>; 353 354 timer { 355 compatible = "mti,gic-timer"; 356 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; 357 clocks = <&sysc MT7621_CLK_CPU>; 358 }; 359 }; 360 361 nand: nand@1e003000 { 362 status = "disabled"; 363 364 compatible = "mediatek,mt7621-nand"; 365 bank-width = <2>; 366 reg = <0x1e003000 0x800 367 0x1e003800 0x800>; 368 #address-cells = <1>; 369 #size-cells = <1>; 370 371 clocks = <&sysc MT7621_CLK_NAND>; 372 clock-names = "nand"; 373 }; 374 375 ethernet: ethernet@1e100000 { 376 compatible = "mediatek,mt7621-eth"; 377 reg = <0x1e100000 0x10000>; 378 379 clocks = <&sysc MT7621_CLK_FE>, 380 <&sysc MT7621_CLK_ETH>; 381 clock-names = "fe", "ethif"; 382 383 #address-cells = <1>; 384 #size-cells = <0>; 385 386 resets = <&rstctrl 6 &rstctrl 23>; 387 reset-names = "fe", "eth"; 388 389 interrupt-parent = <&gic>; 390 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; 391 392 mediatek,ethsys = <&sysc>; 393 394 pinctrl-names = "default"; 395 pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>; 396 397 gmac0: mac@0 { 398 compatible = "mediatek,eth-mac"; 399 reg = <0>; 400 phy-mode = "rgmii"; 401 402 fixed-link { 403 speed = <1000>; 404 full-duplex; 405 pause; 406 }; 407 }; 408 409 gmac1: mac@1 { 410 compatible = "mediatek,eth-mac"; 411 reg = <1>; 412 status = "off"; 413 phy-mode = "rgmii-rxid"; 414 }; 415 416 mdio-bus { 417 #address-cells = <1>; 418 #size-cells = <0>; 419 420 switch0: switch0@0 { 421 compatible = "mediatek,mt7621"; 422 #address-cells = <1>; 423 #size-cells = <0>; 424 reg = <0>; 425 mediatek,mcm; 426 resets = <&rstctrl 2>; 427 reset-names = "mcm"; 428 interrupt-controller; 429 #interrupt-cells = <1>; 430 interrupt-parent = <&gic>; 431 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 432 433 ports { 434 #address-cells = <1>; 435 #size-cells = <0>; 436 reg = <0>; 437 438 port@0 { 439 status = "off"; 440 reg = <0>; 441 label = "lan0"; 442 }; 443 444 port@1 { 445 status = "off"; 446 reg = <1>; 447 label = "lan1"; 448 }; 449 450 port@2 { 451 status = "off"; 452 reg = <2>; 453 label = "lan2"; 454 }; 455 456 port@3 { 457 status = "off"; 458 reg = <3>; 459 label = "lan3"; 460 }; 461 462 port@4 { 463 status = "off"; 464 reg = <4>; 465 label = "lan4"; 466 }; 467 468 port@6 { 469 reg = <6>; 470 label = "cpu"; 471 ethernet = <&gmac0>; 472 phy-mode = "trgmii"; 473 474 fixed-link { 475 speed = <1000>; 476 full-duplex; 477 }; 478 }; 479 }; 480 }; 481 }; 482 }; 483 484 pcie: pcie@1e140000 { 485 compatible = "mediatek,mt7621-pci"; 486 reg = <0x1e140000 0x100>, /* host-pci bridge registers */ 487 <0x1e142000 0x100>, /* pcie port 0 RC control registers */ 488 <0x1e143000 0x100>, /* pcie port 1 RC control registers */ 489 <0x1e144000 0x100>; /* pcie port 2 RC control registers */ 490 #address-cells = <3>; 491 #size-cells = <2>; 492 493 pinctrl-names = "default"; 494 pinctrl-0 = <&pcie_pins>; 495 496 device_type = "pci"; 497 498 ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */ 499 <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */ 500 501 #interrupt-cells = <1>; 502 interrupt-map-mask = <0xF800 0 0 0>; 503 interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>, 504 <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>, 505 <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; 506 507 status = "disabled"; 508 509 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>; 510 511 pcie@0,0 { 512 reg = <0x0000 0 0 0 0>; 513 #address-cells = <3>; 514 #size-cells = <2>; 515 device_type = "pci"; 516 #interrupt-cells = <1>; 517 interrupt-map-mask = <0 0 0 0>; 518 interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>; 519 resets = <&rstctrl 24>; 520 clocks = <&sysc MT7621_CLK_PCIE0>; 521 phys = <&pcie0_phy 1>; 522 phy-names = "pcie-phy0"; 523 ranges; 524 }; 525 526 pcie@1,0 { 527 reg = <0x0800 0 0 0 0>; 528 #address-cells = <3>; 529 #size-cells = <2>; 530 device_type = "pci"; 531 #interrupt-cells = <1>; 532 interrupt-map-mask = <0 0 0 0>; 533 interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; 534 resets = <&rstctrl 25>; 535 clocks = <&sysc MT7621_CLK_PCIE1>; 536 phys = <&pcie0_phy 1>; 537 phy-names = "pcie-phy1"; 538 ranges; 539 }; 540 541 pcie@2,0 { 542 reg = <0x1000 0 0 0 0>; 543 #address-cells = <3>; 544 #size-cells = <2>; 545 device_type = "pci"; 546 #interrupt-cells = <1>; 547 interrupt-map-mask = <0 0 0 0>; 548 interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; 549 resets = <&rstctrl 26>; 550 clocks = <&sysc MT7621_CLK_PCIE2>; 551 phys = <&pcie2_phy 0>; 552 phy-names = "pcie-phy2"; 553 ranges; 554 }; 555 }; 556 557 pcie0_phy: pcie-phy@1e149000 { 558 compatible = "mediatek,mt7621-pci-phy"; 559 reg = <0x1e149000 0x0700>; 560 clocks = <&sysc MT7621_CLK_XTAL>; 561 #phy-cells = <1>; 562 }; 563 564 pcie2_phy: pcie-phy@1e14a000 { 565 compatible = "mediatek,mt7621-pci-phy"; 566 reg = <0x1e14a000 0x0700>; 567 clocks = <&sysc MT7621_CLK_XTAL>; 568 #phy-cells = <1>; 569 }; 570}; 571