1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2011 Realtek Corporation. */
3
4 #include "../include/odm_precomp.h"
5
ODM_DIG_LowerBound_88E(struct odm_dm_struct * dm_odm)6 void ODM_DIG_LowerBound_88E(struct odm_dm_struct *dm_odm)
7 {
8 struct rtw_dig *pDM_DigTable = &dm_odm->DM_DigTable;
9
10 if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
11 pDM_DigTable->rx_gain_range_min = (u8)pDM_DigTable->AntDiv_RSSI_max;
12 /* If only one Entry connected */
13 }
14
odm_RX_HWAntDivInit(struct odm_dm_struct * dm_odm)15 static void odm_RX_HWAntDivInit(struct odm_dm_struct *dm_odm)
16 {
17 u32 value32;
18
19 if (*dm_odm->mp_mode == 1) {
20 dm_odm->AntDivType = CGCS_RX_SW_ANTDIV;
21 ODM_SetBBReg(dm_odm, ODM_REG_IGI_A_11N, BIT(7), 0); /* disable HW AntDiv */
22 ODM_SetBBReg(dm_odm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* 1:CG, 0:CS */
23 return;
24 }
25
26 /* MAC Setting */
27 value32 = ODM_GetMACReg(dm_odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
28 ODM_SetMACReg(dm_odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
29 /* Pin Settings */
30 ODM_SetBBReg(dm_odm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */
31 ODM_SetBBReg(dm_odm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* Reg864[10]=1'b0 antsel2 by HW */
32 ODM_SetBBReg(dm_odm, ODM_REG_LNA_SWITCH_11N, BIT(22), 1); /* Regb2c[22]=1'b0 disable CS/CG switch */
33 ODM_SetBBReg(dm_odm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* Regb2c[31]=1'b1 output at CG only */
34 /* OFDM Settings */
35 ODM_SetBBReg(dm_odm, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0);
36 /* CCK Settings */
37 ODM_SetBBReg(dm_odm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report issue */
38 ODM_SetBBReg(dm_odm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */
39 ODM_UpdateRxIdleAnt_88E(dm_odm, MAIN_ANT);
40 ODM_SetBBReg(dm_odm, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0201); /* antenna mapping table */
41 }
42
odm_TRX_HWAntDivInit(struct odm_dm_struct * dm_odm)43 static void odm_TRX_HWAntDivInit(struct odm_dm_struct *dm_odm)
44 {
45 u32 value32;
46
47 if (*dm_odm->mp_mode == 1) {
48 dm_odm->AntDivType = CGCS_RX_SW_ANTDIV;
49 ODM_SetBBReg(dm_odm, ODM_REG_IGI_A_11N, BIT(7), 0); /* disable HW AntDiv */
50 ODM_SetBBReg(dm_odm, ODM_REG_RX_ANT_CTRL_11N, BIT(5) | BIT(4) | BIT(3), 0); /* Default RX (0/1) */
51 return;
52 }
53
54 /* MAC Setting */
55 value32 = ODM_GetMACReg(dm_odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
56 ODM_SetMACReg(dm_odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
57 /* Pin Settings */
58 ODM_SetBBReg(dm_odm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */
59 ODM_SetBBReg(dm_odm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* Reg864[10]=1'b0 antsel2 by HW */
60 ODM_SetBBReg(dm_odm, ODM_REG_LNA_SWITCH_11N, BIT(22), 0); /* Regb2c[22]=1'b0 disable CS/CG switch */
61 ODM_SetBBReg(dm_odm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* Regb2c[31]=1'b1 output at CG only */
62 /* OFDM Settings */
63 ODM_SetBBReg(dm_odm, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0);
64 /* CCK Settings */
65 ODM_SetBBReg(dm_odm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report issue */
66 ODM_SetBBReg(dm_odm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */
67 /* Tx Settings */
68 ODM_SetBBReg(dm_odm, ODM_REG_TX_ANT_CTRL_11N, BIT(21), 0); /* Reg80c[21]=1'b0 from TX Reg */
69 ODM_UpdateRxIdleAnt_88E(dm_odm, MAIN_ANT);
70
71 /* antenna mapping table */
72 if (!dm_odm->bIsMPChip) { /* testchip */
73 ODM_SetBBReg(dm_odm, ODM_REG_RX_DEFUALT_A_11N, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */
74 ODM_SetBBReg(dm_odm, ODM_REG_RX_DEFUALT_A_11N, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */
75 } else { /* MPchip */
76 ODM_SetBBReg(dm_odm, ODM_REG_ANT_MAPPING1_11N, bMaskDWord, 0x0201); /* Reg914=3'b010, Reg915=3'b001 */
77 }
78 }
79
odm_FastAntTrainingInit(struct odm_dm_struct * dm_odm)80 static void odm_FastAntTrainingInit(struct odm_dm_struct *dm_odm)
81 {
82 u32 value32, i;
83 struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
84 u32 AntCombination = 2;
85
86 if (*dm_odm->mp_mode == 1)
87 return;
88
89 for (i = 0; i < 6; i++) {
90 dm_fat_tbl->Bssid[i] = 0;
91 dm_fat_tbl->antSumRSSI[i] = 0;
92 dm_fat_tbl->antRSSIcnt[i] = 0;
93 dm_fat_tbl->antAveRSSI[i] = 0;
94 }
95 dm_fat_tbl->TrainIdx = 0;
96 dm_fat_tbl->FAT_State = FAT_NORMAL_STATE;
97
98 /* MAC Setting */
99 value32 = ODM_GetMACReg(dm_odm, 0x4c, bMaskDWord);
100 ODM_SetMACReg(dm_odm, 0x4c, bMaskDWord, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
101 value32 = ODM_GetMACReg(dm_odm, 0x7B4, bMaskDWord);
102 ODM_SetMACReg(dm_odm, 0x7b4, bMaskDWord, value32 | (BIT(16) | BIT(17))); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */
103
104 /* Match MAC ADDR */
105 ODM_SetMACReg(dm_odm, 0x7b4, 0xFFFF, 0);
106 ODM_SetMACReg(dm_odm, 0x7b0, bMaskDWord, 0);
107
108 ODM_SetBBReg(dm_odm, 0x870, BIT(9) | BIT(8), 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */
109 ODM_SetBBReg(dm_odm, 0x864, BIT(10), 0); /* Reg864[10]=1'b0 antsel2 by HW */
110 ODM_SetBBReg(dm_odm, 0xb2c, BIT(22), 0); /* Regb2c[22]=1'b0 disable CS/CG switch */
111 ODM_SetBBReg(dm_odm, 0xb2c, BIT(31), 1); /* Regb2c[31]=1'b1 output at CG only */
112 ODM_SetBBReg(dm_odm, 0xca4, bMaskDWord, 0x000000a0);
113
114 /* antenna mapping table */
115 if (AntCombination == 2) {
116 if (!dm_odm->bIsMPChip) { /* testchip */
117 ODM_SetBBReg(dm_odm, 0x858, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */
118 ODM_SetBBReg(dm_odm, 0x858, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */
119 } else { /* MPchip */
120 ODM_SetBBReg(dm_odm, 0x914, bMaskByte0, 1);
121 ODM_SetBBReg(dm_odm, 0x914, bMaskByte1, 2);
122 }
123 } else if (AntCombination == 7) {
124 if (!dm_odm->bIsMPChip) { /* testchip */
125 ODM_SetBBReg(dm_odm, 0x858, BIT(10) | BIT(9) | BIT(8), 0); /* Reg858[10:8]=3'b000 */
126 ODM_SetBBReg(dm_odm, 0x858, BIT(13) | BIT(12) | BIT(11), 1); /* Reg858[13:11]=3'b001 */
127 ODM_SetBBReg(dm_odm, 0x878, BIT(16), 0);
128 ODM_SetBBReg(dm_odm, 0x858, BIT(15) | BIT(14), 2); /* Reg878[0],Reg858[14:15])=3'b010 */
129 ODM_SetBBReg(dm_odm, 0x878, BIT(19) | BIT(18) | BIT(17), 3);/* Reg878[3:1]=3b'011 */
130 ODM_SetBBReg(dm_odm, 0x878, BIT(22) | BIT(21) | BIT(20), 4);/* Reg878[6:4]=3b'100 */
131 ODM_SetBBReg(dm_odm, 0x878, BIT(25) | BIT(24) | BIT(23), 5);/* Reg878[9:7]=3b'101 */
132 ODM_SetBBReg(dm_odm, 0x878, BIT(28) | BIT(27) | BIT(26), 6);/* Reg878[12:10]=3b'110 */
133 ODM_SetBBReg(dm_odm, 0x878, BIT(31) | BIT(30) | BIT(29), 7);/* Reg878[15:13]=3b'111 */
134 } else { /* MPchip */
135 ODM_SetBBReg(dm_odm, 0x914, bMaskByte0, 0);
136 ODM_SetBBReg(dm_odm, 0x914, bMaskByte1, 1);
137 ODM_SetBBReg(dm_odm, 0x914, bMaskByte2, 2);
138 ODM_SetBBReg(dm_odm, 0x914, bMaskByte3, 3);
139 ODM_SetBBReg(dm_odm, 0x918, bMaskByte0, 4);
140 ODM_SetBBReg(dm_odm, 0x918, bMaskByte1, 5);
141 ODM_SetBBReg(dm_odm, 0x918, bMaskByte2, 6);
142 ODM_SetBBReg(dm_odm, 0x918, bMaskByte3, 7);
143 }
144 }
145
146 /* Default Ant Setting when no fast training */
147 ODM_SetBBReg(dm_odm, 0x80c, BIT(21), 1); /* Reg80c[21]=1'b1 from TX Info */
148 ODM_SetBBReg(dm_odm, 0x864, BIT(5) | BIT(4) | BIT(3), 0); /* Default RX */
149 ODM_SetBBReg(dm_odm, 0x864, BIT(8) | BIT(7) | BIT(6), 1); /* Optional RX */
150
151 /* Enter Traing state */
152 ODM_SetBBReg(dm_odm, 0x864, BIT(2) | BIT(1) | BIT(0), (AntCombination - 1)); /* Reg864[2:0]=3'd6 ant combination=reg864[2:0]+1 */
153 ODM_SetBBReg(dm_odm, 0xc50, BIT(7), 1); /* RegC50[7]=1'b1 enable HW AntDiv */
154 }
155
ODM_AntennaDiversityInit_88E(struct odm_dm_struct * dm_odm)156 void ODM_AntennaDiversityInit_88E(struct odm_dm_struct *dm_odm)
157 {
158 if (dm_odm->SupportICType != ODM_RTL8188E)
159 return;
160
161 if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV)
162 odm_RX_HWAntDivInit(dm_odm);
163 else if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
164 odm_TRX_HWAntDivInit(dm_odm);
165 else if (dm_odm->AntDivType == CG_TRX_SMART_ANTDIV)
166 odm_FastAntTrainingInit(dm_odm);
167 }
168
ODM_UpdateRxIdleAnt_88E(struct odm_dm_struct * dm_odm,u8 Ant)169 void ODM_UpdateRxIdleAnt_88E(struct odm_dm_struct *dm_odm, u8 Ant)
170 {
171 struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
172 u32 DefaultAnt, OptionalAnt;
173
174 if (dm_fat_tbl->RxIdleAnt != Ant) {
175 if (Ant == MAIN_ANT) {
176 DefaultAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
177 OptionalAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
178 } else {
179 DefaultAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
180 OptionalAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
181 }
182
183 if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) {
184 ODM_SetBBReg(dm_odm, ODM_REG_RX_ANT_CTRL_11N, BIT(5) | BIT(4) | BIT(3), DefaultAnt); /* Default RX */
185 ODM_SetBBReg(dm_odm, ODM_REG_RX_ANT_CTRL_11N, BIT(8) | BIT(7) | BIT(6), OptionalAnt); /* Optional RX */
186 ODM_SetBBReg(dm_odm, ODM_REG_ANTSEL_CTRL_11N, BIT(14) | BIT(13) | BIT(12), DefaultAnt); /* Default TX */
187 ODM_SetMACReg(dm_odm, ODM_REG_RESP_TX_11N, BIT(6) | BIT(7), DefaultAnt); /* Resp Tx */
188 } else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) {
189 ODM_SetBBReg(dm_odm, ODM_REG_RX_ANT_CTRL_11N, BIT(5) | BIT(4) | BIT(3), DefaultAnt); /* Default RX */
190 ODM_SetBBReg(dm_odm, ODM_REG_RX_ANT_CTRL_11N, BIT(8) | BIT(7) | BIT(6), OptionalAnt); /* Optional RX */
191 }
192 }
193 dm_fat_tbl->RxIdleAnt = Ant;
194 if (Ant != MAIN_ANT)
195 pr_info("RxIdleAnt=AUX_ANT\n");
196 }
197
odm_UpdateTxAnt_88E(struct odm_dm_struct * dm_odm,u8 Ant,u32 MacId)198 static void odm_UpdateTxAnt_88E(struct odm_dm_struct *dm_odm, u8 Ant, u32 MacId)
199 {
200 struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
201 u8 TargetAnt;
202
203 if (Ant == MAIN_ANT)
204 TargetAnt = MAIN_ANT_CG_TRX;
205 else
206 TargetAnt = AUX_ANT_CG_TRX;
207 dm_fat_tbl->antsel_a[MacId] = TargetAnt & BIT(0);
208 dm_fat_tbl->antsel_b[MacId] = (TargetAnt & BIT(1)) >> 1;
209 dm_fat_tbl->antsel_c[MacId] = (TargetAnt & BIT(2)) >> 2;
210 }
211
ODM_SetTxAntByTxInfo_88E(struct odm_dm_struct * dm_odm,u8 * pDesc,u8 macId)212 void ODM_SetTxAntByTxInfo_88E(struct odm_dm_struct *dm_odm, u8 *pDesc, u8 macId)
213 {
214 struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
215
216 if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) || (dm_odm->AntDivType == CG_TRX_SMART_ANTDIV)) {
217 SET_TX_DESC_ANTSEL_A_88E(pDesc, dm_fat_tbl->antsel_a[macId]);
218 SET_TX_DESC_ANTSEL_B_88E(pDesc, dm_fat_tbl->antsel_b[macId]);
219 SET_TX_DESC_ANTSEL_C_88E(pDesc, dm_fat_tbl->antsel_c[macId]);
220 }
221 }
222
ODM_AntselStatistics_88E(struct odm_dm_struct * dm_odm,u8 antsel_tr_mux,u32 MacId,u8 RxPWDBAll)223 void ODM_AntselStatistics_88E(struct odm_dm_struct *dm_odm, u8 antsel_tr_mux, u32 MacId, u8 RxPWDBAll)
224 {
225 struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
226 if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) {
227 if (antsel_tr_mux == MAIN_ANT_CG_TRX) {
228 dm_fat_tbl->MainAnt_Sum[MacId] += RxPWDBAll;
229 dm_fat_tbl->MainAnt_Cnt[MacId]++;
230 } else {
231 dm_fat_tbl->AuxAnt_Sum[MacId] += RxPWDBAll;
232 dm_fat_tbl->AuxAnt_Cnt[MacId]++;
233 }
234 } else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) {
235 if (antsel_tr_mux == MAIN_ANT_CGCS_RX) {
236 dm_fat_tbl->MainAnt_Sum[MacId] += RxPWDBAll;
237 dm_fat_tbl->MainAnt_Cnt[MacId]++;
238 } else {
239 dm_fat_tbl->AuxAnt_Sum[MacId] += RxPWDBAll;
240 dm_fat_tbl->AuxAnt_Cnt[MacId]++;
241 }
242 }
243 }
244
odm_HWAntDiv(struct odm_dm_struct * dm_odm)245 static void odm_HWAntDiv(struct odm_dm_struct *dm_odm)
246 {
247 u32 i, MinRSSI = 0xFF, AntDivMaxRSSI = 0, MaxRSSI = 0, LocalMinRSSI, LocalMaxRSSI;
248 u32 Main_RSSI, Aux_RSSI;
249 u8 RxIdleAnt = 0, TargetAnt = 7;
250 struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
251 struct rtw_dig *pDM_DigTable = &dm_odm->DM_DigTable;
252 struct sta_info *pEntry;
253
254 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
255 pEntry = dm_odm->pODM_StaInfo[i];
256 if (IS_STA_VALID(pEntry)) {
257 /* 2 Caculate RSSI per Antenna */
258 Main_RSSI = (dm_fat_tbl->MainAnt_Cnt[i] != 0) ? (dm_fat_tbl->MainAnt_Sum[i] / dm_fat_tbl->MainAnt_Cnt[i]) : 0;
259 Aux_RSSI = (dm_fat_tbl->AuxAnt_Cnt[i] != 0) ? (dm_fat_tbl->AuxAnt_Sum[i] / dm_fat_tbl->AuxAnt_Cnt[i]) : 0;
260 TargetAnt = (Main_RSSI >= Aux_RSSI) ? MAIN_ANT : AUX_ANT;
261 /* 2 Select MaxRSSI for DIG */
262 LocalMaxRSSI = (Main_RSSI > Aux_RSSI) ? Main_RSSI : Aux_RSSI;
263 if ((LocalMaxRSSI > AntDivMaxRSSI) && (LocalMaxRSSI < 40))
264 AntDivMaxRSSI = LocalMaxRSSI;
265 if (LocalMaxRSSI > MaxRSSI)
266 MaxRSSI = LocalMaxRSSI;
267
268 /* 2 Select RX Idle Antenna */
269 if ((dm_fat_tbl->RxIdleAnt == MAIN_ANT) && (Main_RSSI == 0))
270 Main_RSSI = Aux_RSSI;
271 else if ((dm_fat_tbl->RxIdleAnt == AUX_ANT) && (Aux_RSSI == 0))
272 Aux_RSSI = Main_RSSI;
273
274 LocalMinRSSI = (Main_RSSI > Aux_RSSI) ? Aux_RSSI : Main_RSSI;
275 if (LocalMinRSSI < MinRSSI) {
276 MinRSSI = LocalMinRSSI;
277 RxIdleAnt = TargetAnt;
278 }
279 /* 2 Select TRX Antenna */
280 if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
281 odm_UpdateTxAnt_88E(dm_odm, TargetAnt, i);
282 }
283 dm_fat_tbl->MainAnt_Sum[i] = 0;
284 dm_fat_tbl->AuxAnt_Sum[i] = 0;
285 dm_fat_tbl->MainAnt_Cnt[i] = 0;
286 dm_fat_tbl->AuxAnt_Cnt[i] = 0;
287 }
288
289 /* 2 Set RX Idle Antenna */
290 ODM_UpdateRxIdleAnt_88E(dm_odm, RxIdleAnt);
291
292 pDM_DigTable->AntDiv_RSSI_max = AntDivMaxRSSI;
293 pDM_DigTable->RSSI_max = MaxRSSI;
294 }
295
ODM_AntennaDiversity_88E(struct odm_dm_struct * dm_odm)296 void ODM_AntennaDiversity_88E(struct odm_dm_struct *dm_odm)
297 {
298 struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
299 if ((dm_odm->SupportICType != ODM_RTL8188E) || (!(dm_odm->SupportAbility & ODM_BB_ANT_DIV)))
300 return;
301 if (!dm_odm->bLinked) {
302 if (dm_fat_tbl->bBecomeLinked) {
303 ODM_SetBBReg(dm_odm, ODM_REG_IGI_A_11N, BIT(7), 0); /* RegC50[7]=1'b1 enable HW AntDiv */
304 ODM_SetBBReg(dm_odm, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT(15), 0); /* Enable CCK AntDiv */
305 if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
306 ODM_SetBBReg(dm_odm, ODM_REG_TX_ANT_CTRL_11N, BIT(21), 0); /* Reg80c[21]=1'b0 from TX Reg */
307 dm_fat_tbl->bBecomeLinked = dm_odm->bLinked;
308 }
309 return;
310 } else {
311 if (!dm_fat_tbl->bBecomeLinked) {
312 /* Because HW AntDiv is disabled before Link, we enable HW AntDiv after link */
313 ODM_SetBBReg(dm_odm, ODM_REG_IGI_A_11N, BIT(7), 1); /* RegC50[7]=1'b1 enable HW AntDiv */
314 ODM_SetBBReg(dm_odm, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT(15), 1); /* Enable CCK AntDiv */
315 if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
316 ODM_SetBBReg(dm_odm, ODM_REG_TX_ANT_CTRL_11N, BIT(21), 1); /* Reg80c[21]=1'b1 from TX Info */
317 dm_fat_tbl->bBecomeLinked = dm_odm->bLinked;
318 }
319 }
320 if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) || (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV))
321 odm_HWAntDiv(dm_odm);
322 }
323
324 /* 3============================================================ */
325 /* 3 Dynamic Primary CCA */
326 /* 3============================================================ */
327
odm_PrimaryCCA_Init(struct odm_dm_struct * dm_odm)328 void odm_PrimaryCCA_Init(struct odm_dm_struct *dm_odm)
329 {
330 struct dyn_primary_cca *PrimaryCCA = &dm_odm->DM_PriCCA;
331
332 PrimaryCCA->dup_rts_flag = 0;
333 PrimaryCCA->intf_flag = 0;
334 PrimaryCCA->intf_type = 0;
335 PrimaryCCA->monitor_flag = 0;
336 PrimaryCCA->pri_cca_flag = 0;
337 }
338