1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2007 - 2011 Realtek Corporation. */ 3 4 #ifndef __INC_HAL8188EPHYCFG_H__ 5 #define __INC_HAL8188EPHYCFG_H__ 6 7 /*--------------------------Define Parameters-------------------------------*/ 8 #define LOOP_LIMIT 5 9 #define MAX_STALL_TIME 50 /* us */ 10 #define AntennaDiversityValue 0x80 11 #define MAX_TXPWR_IDX_NMODE_92S 63 12 #define Reset_Cnt_Limit 3 13 14 #define IQK_MAC_REG_NUM 4 15 #define IQK_ADDA_REG_NUM 16 16 #define IQK_BB_REG_NUM 9 17 #define HP_THERMAL_NUM 8 18 19 #define MAX_AGGR_NUM 0x07 20 21 /*--------------------------Define Parameters-------------------------------*/ 22 23 /*------------------------------Define structure----------------------------*/ 24 enum sw_chnl_cmd_id { 25 CmdID_End, 26 CmdID_SetTxPowerLevel, 27 CmdID_BBRegWrite10, 28 CmdID_WritePortUlong, 29 CmdID_WritePortUshort, 30 CmdID_WritePortUchar, 31 CmdID_RF_WriteReg, 32 }; 33 34 /* 1. Switch channel related */ 35 struct sw_chnl_cmd { 36 enum sw_chnl_cmd_id CmdID; 37 u32 Para1; 38 u32 Para2; 39 u32 msDelay; 40 }; 41 42 enum hw90_block { 43 HW90_BLOCK_MAC = 0, 44 HW90_BLOCK_PHY0 = 1, 45 HW90_BLOCK_PHY1 = 2, 46 HW90_BLOCK_RF = 3, 47 HW90_BLOCK_MAXIMUM = 4, /* Never use this */ 48 }; 49 50 enum rf_radio_path { 51 RF_PATH_A = 0, /* Radio Path A */ 52 RF_PATH_B = 1, /* Radio Path B */ 53 RF_PATH_C = 2, /* Radio Path C */ 54 RF_PATH_D = 3, /* Radio Path D */ 55 }; 56 57 #define MAX_PG_GROUP 13 58 59 #define RF_PATH_MAX 3 60 #define MAX_TX_COUNT 4 /* path numbers */ 61 62 #define CHANNEL_MAX_NUMBER 14 /* 14 is the max chnl number */ 63 #define MAX_CHNL_GROUP_24G 6 /* ch1~2, ch3~5, ch6~8, 64 *ch9~11, ch12~13, CH 14 65 * total three groups */ 66 #define CHANNEL_GROUP_MAX_88E 6 67 68 enum wireless_mode { 69 WIRELESS_MODE_UNKNOWN = 0x00, 70 WIRELESS_MODE_B = BIT(0), 71 WIRELESS_MODE_G = BIT(1), 72 WIRELESS_MODE_AUTO = BIT(5), 73 WIRELESS_MODE_N_24G = BIT(3), 74 }; 75 76 enum phy_rate_tx_offset_area { 77 RA_OFFSET_LEGACY_OFDM1, 78 RA_OFFSET_LEGACY_OFDM2, 79 RA_OFFSET_HT_OFDM1, 80 RA_OFFSET_HT_OFDM2, 81 RA_OFFSET_HT_OFDM3, 82 RA_OFFSET_HT_OFDM4, 83 RA_OFFSET_HT_CCK, 84 }; 85 86 /* BB/RF related */ 87 enum RF_TYPE_8190P { 88 RF_TYPE_MIN, /* 0 */ 89 RF_8225 = 1, /* 1 11b/g RF for verification only */ 90 RF_8256 = 2, /* 2 11b/g/n */ 91 RF_6052 = 4, /* 4 11b/g/n RF */ 92 /* TODO: We should remove this psudo PHY RF after we get new RF. */ 93 RF_PSEUDO_11N = 5, /* 5, It is a temporality RF. */ 94 }; 95 96 struct bb_reg_def { 97 u32 rfintfs; /* set software control: */ 98 /* 0x870~0x877[8 bytes] */ 99 u32 rfintfi; /* readback data: */ 100 /* 0x8e0~0x8e7[8 bytes] */ 101 u32 rfintfo; /* output data: */ 102 /* 0x860~0x86f [16 bytes] */ 103 u32 rfintfe; /* output enable: */ 104 /* 0x860~0x86f [16 bytes] */ 105 u32 rf3wireOffset; /* LSSI data: */ 106 /* 0x840~0x84f [16 bytes] */ 107 u32 rfLSSI_Select; /* BB Band Select: */ 108 /* 0x878~0x87f [8 bytes] */ 109 u32 rfTxGainStage; /* Tx gain stage: */ 110 /* 0x80c~0x80f [4 bytes] */ 111 u32 rfHSSIPara1; /* wire parameter control1 : */ 112 /* 0x820~0x823,0x828~0x82b, 113 * 0x830~0x833, 0x838~0x83b [16 bytes] */ 114 u32 rfHSSIPara2; /* wire parameter control2 : */ 115 /* 0x824~0x827,0x82c~0x82f, 0x834~0x837, 116 * 0x83c~0x83f [16 bytes] */ 117 u32 rfSwitchControl; /* Tx Rx antenna control : */ 118 /* 0x858~0x85f [16 bytes] */ 119 u32 rfAGCControl1; /* AGC parameter control1 : */ 120 /* 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 121 * 0xc68~0xc6b [16 bytes] */ 122 u32 rfAGCControl2; /* AGC parameter control2 : */ 123 /* 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 124 * 0xc6c~0xc6f [16 bytes] */ 125 u32 rfRxIQImbalance; /* OFDM Rx IQ imbalance matrix : */ 126 /* 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 127 * 0xc2c~0xc2f [16 bytes] */ 128 u32 rfRxAFE; /* Rx IQ DC ofset and Rx digital filter, 129 * Rx DC notch filter : */ 130 /* 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 131 * 0xc28~0xc2b [16 bytes] */ 132 u32 rfTxIQImbalance; /* OFDM Tx IQ imbalance matrix */ 133 /* 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 134 * 0xc98~0xc9b [16 bytes] */ 135 u32 rfTxAFE; /* Tx IQ DC Offset and Tx DFIR type */ 136 /* 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 137 * 0xc9c~0xc9f [16 bytes] */ 138 u32 rfLSSIReadBack; /* LSSI RF readback data SI mode */ 139 /* 0x8a0~0x8af [16 bytes] */ 140 u32 rfLSSIReadBackPi; /* LSSI RF readback data PI mode 0x8b8-8bc for 141 * Path A and B */ 142 }; 143 144 struct ant_sel_ofdm { 145 u32 r_tx_antenna:4; 146 u32 r_ant_l:4; 147 u32 r_ant_non_ht:4; 148 u32 r_ant_ht1:4; 149 u32 r_ant_ht2:4; 150 u32 r_ant_ht_s1:4; 151 u32 r_ant_non_ht_s1:4; 152 u32 OFDM_TXSC:2; 153 u32 reserved:2; 154 }; 155 156 struct ant_sel_cck { 157 u8 r_cckrx_enable_2:2; 158 u8 r_cckrx_enable:2; 159 u8 r_ccktx_enable:4; 160 }; 161 162 /*------------------------------Define structure----------------------------*/ 163 164 /*------------------------Export global variable----------------------------*/ 165 /*------------------------Export global variable----------------------------*/ 166 167 /*------------------------Export Marco Definition---------------------------*/ 168 /*------------------------Export Marco Definition---------------------------*/ 169 170 /*--------------------------Exported Function prototype---------------------*/ 171 /* */ 172 /* BB and RF register read/write */ 173 /* */ 174 u32 rtl8188e_PHY_QueryBBReg(struct adapter *adapter, u32 regaddr, u32 mask); 175 void rtl8188e_PHY_SetBBReg(struct adapter *Adapter, u32 RegAddr, 176 u32 mask, u32 data); 177 u32 rtl8188e_PHY_QueryRFReg(struct adapter *adapter, enum rf_radio_path rfpath, 178 u32 regaddr, u32 mask); 179 void rtl8188e_PHY_SetRFReg(struct adapter *adapter, enum rf_radio_path rfpath, 180 u32 regaddr, u32 mask, u32 data); 181 182 /* Initialization related function */ 183 /* MAC/BB/RF HAL config */ 184 int PHY_MACConfig8188E(struct adapter *adapter); 185 int PHY_BBConfig8188E(struct adapter *adapter); 186 int PHY_RFConfig8188E(struct adapter *adapter); 187 188 /* RF config */ 189 int rtl8188e_PHY_ConfigRFWithParaFile(struct adapter *adapter, u8 *filename, 190 enum rf_radio_path rfpath); 191 int rtl8188e_PHY_ConfigRFWithHeaderFile(struct adapter *adapter, 192 enum rf_radio_path rfpath); 193 194 /* Read initi reg value for tx power setting. */ 195 void rtl8192c_PHY_GetHWRegOriginalValue(struct adapter *adapter); 196 197 /* BB TX Power R/W */ 198 void PHY_GetTxPowerLevel8188E(struct adapter *adapter, u32 *powerlevel); 199 void PHY_SetTxPowerLevel8188E(struct adapter *adapter, u8 channel); 200 bool PHY_UpdateTxPowerDbm8188E(struct adapter *adapter, int power); 201 202 void PHY_ScanOperationBackup8188E(struct adapter *Adapter, u8 Operation); 203 204 /* Switch bandwidth for 8192S */ 205 void PHY_SetBWMode8188E(struct adapter *adapter, 206 enum ht_channel_width chnlwidth, unsigned char offset); 207 208 /* channel switch related funciton */ 209 void PHY_SwChnl8188E(struct adapter *adapter, u8 channel); 210 /* Call after initialization */ 211 void ChkFwCmdIoDone(struct adapter *adapter); 212 213 /* BB/MAC/RF other monitor API */ 214 void PHY_SetRFPathSwitch_8188E(struct adapter *adapter, bool main); 215 216 void PHY_SwitchEphyParameter(struct adapter *adapter); 217 218 void PHY_EnableHostClkReq(struct adapter *adapter); 219 220 bool SetAntennaConfig92C(struct adapter *adapter, u8 defaultant); 221 222 void storePwrIndexDiffRateOffset(struct adapter *adapter, u32 regaddr, 223 u32 mask, u32 data); 224 /*--------------------------Exported Function prototype---------------------*/ 225 226 #define PHY_QueryBBReg(adapt, regaddr, mask) \ 227 rtl8188e_PHY_QueryBBReg((adapt), (regaddr), (mask)) 228 #define PHY_SetBBReg(adapt, regaddr, bitmask, data) \ 229 rtl8188e_PHY_SetBBReg((adapt), (regaddr), (bitmask), (data)) 230 #define PHY_QueryRFReg(adapt, rfpath, regaddr, bitmask) \ 231 rtl8188e_PHY_QueryRFReg((adapt), (rfpath), (regaddr), (bitmask)) 232 #define PHY_SetRFReg(adapt, rfpath, regaddr, bitmask, data) \ 233 rtl8188e_PHY_SetRFReg((adapt), (rfpath), (regaddr), (bitmask), (data)) 234 235 #define PHY_SetMacReg PHY_SetBBReg 236 237 #define SIC_HW_SUPPORT 0 238 239 #define SIC_MAX_POLL_CNT 5 240 241 #define SIC_CMD_READY 0 242 #define SIC_CMD_WRITE 1 243 #define SIC_CMD_READ 2 244 245 #define SIC_CMD_REG 0x1EB /* 1byte */ 246 #define SIC_ADDR_REG 0x1E8 /* 1b9~1ba, 2 bytes */ 247 #define SIC_DATA_REG 0x1EC /* 1bc~1bf */ 248 249 #endif /* __INC_HAL8192CPHYCFG_H */ 250