1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for AMBA serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright 1999 ARM Limited
8 * Copyright (C) 2000 Deep Blue Solutions Ltd.
9 *
10 * This is a generic driver for ARM AMBA-type serial ports. They
11 * have a lot of 16550-like features, but are not register compatible.
12 * Note that although they do have CTS, DCD and DSR inputs, they do
13 * not have an RI input, nor do they have DTR or RTS outputs. If
14 * required, these have to be supplied via some other means (eg, GPIO)
15 * and hooked into this driver.
16 */
17
18 #include <linux/module.h>
19 #include <linux/ioport.h>
20 #include <linux/init.h>
21 #include <linux/console.h>
22 #include <linux/sysrq.h>
23 #include <linux/device.h>
24 #include <linux/tty.h>
25 #include <linux/tty_flip.h>
26 #include <linux/serial_core.h>
27 #include <linux/serial.h>
28 #include <linux/amba/bus.h>
29 #include <linux/amba/serial.h>
30 #include <linux/clk.h>
31 #include <linux/slab.h>
32 #include <linux/io.h>
33
34 #define UART_NR 8
35
36 #define SERIAL_AMBA_MAJOR 204
37 #define SERIAL_AMBA_MINOR 16
38 #define SERIAL_AMBA_NR UART_NR
39
40 #define AMBA_ISR_PASS_LIMIT 256
41
42 #define UART_RX_DATA(s) (((s) & UART01x_FR_RXFE) == 0)
43 #define UART_TX_READY(s) (((s) & UART01x_FR_TXFF) == 0)
44
45 #define UART_DUMMY_RSR_RX 256
46 #define UART_PORT_SIZE 64
47
48 /*
49 * We wrap our port structure around the generic uart_port.
50 */
51 struct uart_amba_port {
52 struct uart_port port;
53 struct clk *clk;
54 struct amba_device *dev;
55 struct amba_pl010_data *data;
56 unsigned int old_status;
57 };
58
pl010_stop_tx(struct uart_port * port)59 static void pl010_stop_tx(struct uart_port *port)
60 {
61 struct uart_amba_port *uap =
62 container_of(port, struct uart_amba_port, port);
63 unsigned int cr;
64
65 cr = readb(uap->port.membase + UART010_CR);
66 cr &= ~UART010_CR_TIE;
67 writel(cr, uap->port.membase + UART010_CR);
68 }
69
pl010_start_tx(struct uart_port * port)70 static void pl010_start_tx(struct uart_port *port)
71 {
72 struct uart_amba_port *uap =
73 container_of(port, struct uart_amba_port, port);
74 unsigned int cr;
75
76 cr = readb(uap->port.membase + UART010_CR);
77 cr |= UART010_CR_TIE;
78 writel(cr, uap->port.membase + UART010_CR);
79 }
80
pl010_stop_rx(struct uart_port * port)81 static void pl010_stop_rx(struct uart_port *port)
82 {
83 struct uart_amba_port *uap =
84 container_of(port, struct uart_amba_port, port);
85 unsigned int cr;
86
87 cr = readb(uap->port.membase + UART010_CR);
88 cr &= ~(UART010_CR_RIE | UART010_CR_RTIE);
89 writel(cr, uap->port.membase + UART010_CR);
90 }
91
pl010_disable_ms(struct uart_port * port)92 static void pl010_disable_ms(struct uart_port *port)
93 {
94 struct uart_amba_port *uap = (struct uart_amba_port *)port;
95 unsigned int cr;
96
97 cr = readb(uap->port.membase + UART010_CR);
98 cr &= ~UART010_CR_MSIE;
99 writel(cr, uap->port.membase + UART010_CR);
100 }
101
pl010_enable_ms(struct uart_port * port)102 static void pl010_enable_ms(struct uart_port *port)
103 {
104 struct uart_amba_port *uap =
105 container_of(port, struct uart_amba_port, port);
106 unsigned int cr;
107
108 cr = readb(uap->port.membase + UART010_CR);
109 cr |= UART010_CR_MSIE;
110 writel(cr, uap->port.membase + UART010_CR);
111 }
112
pl010_rx_chars(struct uart_amba_port * uap)113 static void pl010_rx_chars(struct uart_amba_port *uap)
114 {
115 unsigned int status, ch, flag, rsr, max_count = 256;
116
117 status = readb(uap->port.membase + UART01x_FR);
118 while (UART_RX_DATA(status) && max_count--) {
119 ch = readb(uap->port.membase + UART01x_DR);
120 flag = TTY_NORMAL;
121
122 uap->port.icount.rx++;
123
124 /*
125 * Note that the error handling code is
126 * out of the main execution path
127 */
128 rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
129 if (unlikely(rsr & UART01x_RSR_ANY)) {
130 writel(0, uap->port.membase + UART01x_ECR);
131
132 if (rsr & UART01x_RSR_BE) {
133 rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
134 uap->port.icount.brk++;
135 if (uart_handle_break(&uap->port))
136 goto ignore_char;
137 } else if (rsr & UART01x_RSR_PE)
138 uap->port.icount.parity++;
139 else if (rsr & UART01x_RSR_FE)
140 uap->port.icount.frame++;
141 if (rsr & UART01x_RSR_OE)
142 uap->port.icount.overrun++;
143
144 rsr &= uap->port.read_status_mask;
145
146 if (rsr & UART01x_RSR_BE)
147 flag = TTY_BREAK;
148 else if (rsr & UART01x_RSR_PE)
149 flag = TTY_PARITY;
150 else if (rsr & UART01x_RSR_FE)
151 flag = TTY_FRAME;
152 }
153
154 if (uart_handle_sysrq_char(&uap->port, ch))
155 goto ignore_char;
156
157 uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag);
158
159 ignore_char:
160 status = readb(uap->port.membase + UART01x_FR);
161 }
162 tty_flip_buffer_push(&uap->port.state->port);
163 }
164
pl010_tx_chars(struct uart_amba_port * uap)165 static void pl010_tx_chars(struct uart_amba_port *uap)
166 {
167 struct circ_buf *xmit = &uap->port.state->xmit;
168 int count;
169
170 if (uap->port.x_char) {
171 writel(uap->port.x_char, uap->port.membase + UART01x_DR);
172 uap->port.icount.tx++;
173 uap->port.x_char = 0;
174 return;
175 }
176 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
177 pl010_stop_tx(&uap->port);
178 return;
179 }
180
181 count = uap->port.fifosize >> 1;
182 do {
183 writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
184 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
185 uap->port.icount.tx++;
186 if (uart_circ_empty(xmit))
187 break;
188 } while (--count > 0);
189
190 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
191 uart_write_wakeup(&uap->port);
192
193 if (uart_circ_empty(xmit))
194 pl010_stop_tx(&uap->port);
195 }
196
pl010_modem_status(struct uart_amba_port * uap)197 static void pl010_modem_status(struct uart_amba_port *uap)
198 {
199 unsigned int status, delta;
200
201 writel(0, uap->port.membase + UART010_ICR);
202
203 status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
204
205 delta = status ^ uap->old_status;
206 uap->old_status = status;
207
208 if (!delta)
209 return;
210
211 if (delta & UART01x_FR_DCD)
212 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
213
214 if (delta & UART01x_FR_DSR)
215 uap->port.icount.dsr++;
216
217 if (delta & UART01x_FR_CTS)
218 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
219
220 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
221 }
222
pl010_int(int irq,void * dev_id)223 static irqreturn_t pl010_int(int irq, void *dev_id)
224 {
225 struct uart_amba_port *uap = dev_id;
226 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
227 int handled = 0;
228
229 spin_lock(&uap->port.lock);
230
231 status = readb(uap->port.membase + UART010_IIR);
232 if (status) {
233 do {
234 if (status & (UART010_IIR_RTIS | UART010_IIR_RIS))
235 pl010_rx_chars(uap);
236 if (status & UART010_IIR_MIS)
237 pl010_modem_status(uap);
238 if (status & UART010_IIR_TIS)
239 pl010_tx_chars(uap);
240
241 if (pass_counter-- == 0)
242 break;
243
244 status = readb(uap->port.membase + UART010_IIR);
245 } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS |
246 UART010_IIR_TIS));
247 handled = 1;
248 }
249
250 spin_unlock(&uap->port.lock);
251
252 return IRQ_RETVAL(handled);
253 }
254
pl010_tx_empty(struct uart_port * port)255 static unsigned int pl010_tx_empty(struct uart_port *port)
256 {
257 struct uart_amba_port *uap =
258 container_of(port, struct uart_amba_port, port);
259 unsigned int status = readb(uap->port.membase + UART01x_FR);
260 return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT;
261 }
262
pl010_get_mctrl(struct uart_port * port)263 static unsigned int pl010_get_mctrl(struct uart_port *port)
264 {
265 struct uart_amba_port *uap =
266 container_of(port, struct uart_amba_port, port);
267 unsigned int result = 0;
268 unsigned int status;
269
270 status = readb(uap->port.membase + UART01x_FR);
271 if (status & UART01x_FR_DCD)
272 result |= TIOCM_CAR;
273 if (status & UART01x_FR_DSR)
274 result |= TIOCM_DSR;
275 if (status & UART01x_FR_CTS)
276 result |= TIOCM_CTS;
277
278 return result;
279 }
280
pl010_set_mctrl(struct uart_port * port,unsigned int mctrl)281 static void pl010_set_mctrl(struct uart_port *port, unsigned int mctrl)
282 {
283 struct uart_amba_port *uap =
284 container_of(port, struct uart_amba_port, port);
285
286 if (uap->data)
287 uap->data->set_mctrl(uap->dev, uap->port.membase, mctrl);
288 }
289
pl010_break_ctl(struct uart_port * port,int break_state)290 static void pl010_break_ctl(struct uart_port *port, int break_state)
291 {
292 struct uart_amba_port *uap =
293 container_of(port, struct uart_amba_port, port);
294 unsigned long flags;
295 unsigned int lcr_h;
296
297 spin_lock_irqsave(&uap->port.lock, flags);
298 lcr_h = readb(uap->port.membase + UART010_LCRH);
299 if (break_state == -1)
300 lcr_h |= UART01x_LCRH_BRK;
301 else
302 lcr_h &= ~UART01x_LCRH_BRK;
303 writel(lcr_h, uap->port.membase + UART010_LCRH);
304 spin_unlock_irqrestore(&uap->port.lock, flags);
305 }
306
pl010_startup(struct uart_port * port)307 static int pl010_startup(struct uart_port *port)
308 {
309 struct uart_amba_port *uap =
310 container_of(port, struct uart_amba_port, port);
311 int retval;
312
313 /*
314 * Try to enable the clock producer.
315 */
316 retval = clk_prepare_enable(uap->clk);
317 if (retval)
318 goto out;
319
320 uap->port.uartclk = clk_get_rate(uap->clk);
321
322 /*
323 * Allocate the IRQ
324 */
325 retval = request_irq(uap->port.irq, pl010_int, 0, "uart-pl010", uap);
326 if (retval)
327 goto clk_dis;
328
329 /*
330 * initialise the old status of the modem signals
331 */
332 uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
333
334 /*
335 * Finally, enable interrupts
336 */
337 writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
338 uap->port.membase + UART010_CR);
339
340 return 0;
341
342 clk_dis:
343 clk_disable_unprepare(uap->clk);
344 out:
345 return retval;
346 }
347
pl010_shutdown(struct uart_port * port)348 static void pl010_shutdown(struct uart_port *port)
349 {
350 struct uart_amba_port *uap =
351 container_of(port, struct uart_amba_port, port);
352
353 /*
354 * Free the interrupt
355 */
356 free_irq(uap->port.irq, uap);
357
358 /*
359 * disable all interrupts, disable the port
360 */
361 writel(0, uap->port.membase + UART010_CR);
362
363 /* disable break condition and fifos */
364 writel(readb(uap->port.membase + UART010_LCRH) &
365 ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN),
366 uap->port.membase + UART010_LCRH);
367
368 /*
369 * Shut down the clock producer
370 */
371 clk_disable_unprepare(uap->clk);
372 }
373
374 static void
pl010_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)375 pl010_set_termios(struct uart_port *port, struct ktermios *termios,
376 struct ktermios *old)
377 {
378 struct uart_amba_port *uap =
379 container_of(port, struct uart_amba_port, port);
380 unsigned int lcr_h, old_cr;
381 unsigned long flags;
382 unsigned int baud, quot;
383
384 /*
385 * Ask the core to calculate the divisor for us.
386 */
387 baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16);
388 quot = uart_get_divisor(port, baud);
389
390 switch (termios->c_cflag & CSIZE) {
391 case CS5:
392 lcr_h = UART01x_LCRH_WLEN_5;
393 break;
394 case CS6:
395 lcr_h = UART01x_LCRH_WLEN_6;
396 break;
397 case CS7:
398 lcr_h = UART01x_LCRH_WLEN_7;
399 break;
400 default: // CS8
401 lcr_h = UART01x_LCRH_WLEN_8;
402 break;
403 }
404 if (termios->c_cflag & CSTOPB)
405 lcr_h |= UART01x_LCRH_STP2;
406 if (termios->c_cflag & PARENB) {
407 lcr_h |= UART01x_LCRH_PEN;
408 if (!(termios->c_cflag & PARODD))
409 lcr_h |= UART01x_LCRH_EPS;
410 }
411 if (uap->port.fifosize > 1)
412 lcr_h |= UART01x_LCRH_FEN;
413
414 spin_lock_irqsave(&uap->port.lock, flags);
415
416 /*
417 * Update the per-port timeout.
418 */
419 uart_update_timeout(port, termios->c_cflag, baud);
420
421 uap->port.read_status_mask = UART01x_RSR_OE;
422 if (termios->c_iflag & INPCK)
423 uap->port.read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
424 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
425 uap->port.read_status_mask |= UART01x_RSR_BE;
426
427 /*
428 * Characters to ignore
429 */
430 uap->port.ignore_status_mask = 0;
431 if (termios->c_iflag & IGNPAR)
432 uap->port.ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
433 if (termios->c_iflag & IGNBRK) {
434 uap->port.ignore_status_mask |= UART01x_RSR_BE;
435 /*
436 * If we're ignoring parity and break indicators,
437 * ignore overruns too (for real raw support).
438 */
439 if (termios->c_iflag & IGNPAR)
440 uap->port.ignore_status_mask |= UART01x_RSR_OE;
441 }
442
443 /*
444 * Ignore all characters if CREAD is not set.
445 */
446 if ((termios->c_cflag & CREAD) == 0)
447 uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX;
448
449 old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
450
451 if (UART_ENABLE_MS(port, termios->c_cflag))
452 old_cr |= UART010_CR_MSIE;
453
454 /* Set baud rate */
455 quot -= 1;
456 writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
457 writel(quot & 0xff, uap->port.membase + UART010_LCRL);
458
459 /*
460 * ----------v----------v----------v----------v-----
461 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
462 * ----------^----------^----------^----------^-----
463 */
464 writel(lcr_h, uap->port.membase + UART010_LCRH);
465 writel(old_cr, uap->port.membase + UART010_CR);
466
467 spin_unlock_irqrestore(&uap->port.lock, flags);
468 }
469
pl010_set_ldisc(struct uart_port * port,struct ktermios * termios)470 static void pl010_set_ldisc(struct uart_port *port, struct ktermios *termios)
471 {
472 if (termios->c_line == N_PPS) {
473 port->flags |= UPF_HARDPPS_CD;
474 spin_lock_irq(&port->lock);
475 pl010_enable_ms(port);
476 spin_unlock_irq(&port->lock);
477 } else {
478 port->flags &= ~UPF_HARDPPS_CD;
479 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
480 spin_lock_irq(&port->lock);
481 pl010_disable_ms(port);
482 spin_unlock_irq(&port->lock);
483 }
484 }
485 }
486
pl010_type(struct uart_port * port)487 static const char *pl010_type(struct uart_port *port)
488 {
489 return port->type == PORT_AMBA ? "AMBA" : NULL;
490 }
491
492 /*
493 * Release the memory region(s) being used by 'port'
494 */
pl010_release_port(struct uart_port * port)495 static void pl010_release_port(struct uart_port *port)
496 {
497 release_mem_region(port->mapbase, UART_PORT_SIZE);
498 }
499
500 /*
501 * Request the memory region(s) being used by 'port'
502 */
pl010_request_port(struct uart_port * port)503 static int pl010_request_port(struct uart_port *port)
504 {
505 return request_mem_region(port->mapbase, UART_PORT_SIZE, "uart-pl010")
506 != NULL ? 0 : -EBUSY;
507 }
508
509 /*
510 * Configure/autoconfigure the port.
511 */
pl010_config_port(struct uart_port * port,int flags)512 static void pl010_config_port(struct uart_port *port, int flags)
513 {
514 if (flags & UART_CONFIG_TYPE) {
515 port->type = PORT_AMBA;
516 pl010_request_port(port);
517 }
518 }
519
520 /*
521 * verify the new serial_struct (for TIOCSSERIAL).
522 */
pl010_verify_port(struct uart_port * port,struct serial_struct * ser)523 static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
524 {
525 int ret = 0;
526 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
527 ret = -EINVAL;
528 if (ser->irq < 0 || ser->irq >= nr_irqs)
529 ret = -EINVAL;
530 if (ser->baud_base < 9600)
531 ret = -EINVAL;
532 return ret;
533 }
534
535 static const struct uart_ops amba_pl010_pops = {
536 .tx_empty = pl010_tx_empty,
537 .set_mctrl = pl010_set_mctrl,
538 .get_mctrl = pl010_get_mctrl,
539 .stop_tx = pl010_stop_tx,
540 .start_tx = pl010_start_tx,
541 .stop_rx = pl010_stop_rx,
542 .enable_ms = pl010_enable_ms,
543 .break_ctl = pl010_break_ctl,
544 .startup = pl010_startup,
545 .shutdown = pl010_shutdown,
546 .set_termios = pl010_set_termios,
547 .set_ldisc = pl010_set_ldisc,
548 .type = pl010_type,
549 .release_port = pl010_release_port,
550 .request_port = pl010_request_port,
551 .config_port = pl010_config_port,
552 .verify_port = pl010_verify_port,
553 };
554
555 static struct uart_amba_port *amba_ports[UART_NR];
556
557 #ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE
558
pl010_console_putchar(struct uart_port * port,int ch)559 static void pl010_console_putchar(struct uart_port *port, int ch)
560 {
561 struct uart_amba_port *uap =
562 container_of(port, struct uart_amba_port, port);
563 unsigned int status;
564
565 do {
566 status = readb(uap->port.membase + UART01x_FR);
567 barrier();
568 } while (!UART_TX_READY(status));
569 writel(ch, uap->port.membase + UART01x_DR);
570 }
571
572 static void
pl010_console_write(struct console * co,const char * s,unsigned int count)573 pl010_console_write(struct console *co, const char *s, unsigned int count)
574 {
575 struct uart_amba_port *uap = amba_ports[co->index];
576 unsigned int status, old_cr;
577
578 clk_enable(uap->clk);
579
580 /*
581 * First save the CR then disable the interrupts
582 */
583 old_cr = readb(uap->port.membase + UART010_CR);
584 writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
585
586 uart_console_write(&uap->port, s, count, pl010_console_putchar);
587
588 /*
589 * Finally, wait for transmitter to become empty
590 * and restore the TCR
591 */
592 do {
593 status = readb(uap->port.membase + UART01x_FR);
594 barrier();
595 } while (status & UART01x_FR_BUSY);
596 writel(old_cr, uap->port.membase + UART010_CR);
597
598 clk_disable(uap->clk);
599 }
600
601 static void __init
pl010_console_get_options(struct uart_amba_port * uap,int * baud,int * parity,int * bits)602 pl010_console_get_options(struct uart_amba_port *uap, int *baud,
603 int *parity, int *bits)
604 {
605 if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
606 unsigned int lcr_h, quot;
607 lcr_h = readb(uap->port.membase + UART010_LCRH);
608
609 *parity = 'n';
610 if (lcr_h & UART01x_LCRH_PEN) {
611 if (lcr_h & UART01x_LCRH_EPS)
612 *parity = 'e';
613 else
614 *parity = 'o';
615 }
616
617 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
618 *bits = 7;
619 else
620 *bits = 8;
621
622 quot = readb(uap->port.membase + UART010_LCRL) |
623 readb(uap->port.membase + UART010_LCRM) << 8;
624 *baud = uap->port.uartclk / (16 * (quot + 1));
625 }
626 }
627
pl010_console_setup(struct console * co,char * options)628 static int __init pl010_console_setup(struct console *co, char *options)
629 {
630 struct uart_amba_port *uap;
631 int baud = 38400;
632 int bits = 8;
633 int parity = 'n';
634 int flow = 'n';
635 int ret;
636
637 /*
638 * Check whether an invalid uart number has been specified, and
639 * if so, search for the first available port that does have
640 * console support.
641 */
642 if (co->index >= UART_NR)
643 co->index = 0;
644 uap = amba_ports[co->index];
645 if (!uap)
646 return -ENODEV;
647
648 ret = clk_prepare(uap->clk);
649 if (ret)
650 return ret;
651
652 uap->port.uartclk = clk_get_rate(uap->clk);
653
654 if (options)
655 uart_parse_options(options, &baud, &parity, &bits, &flow);
656 else
657 pl010_console_get_options(uap, &baud, &parity, &bits);
658
659 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
660 }
661
662 static struct uart_driver amba_reg;
663 static struct console amba_console = {
664 .name = "ttyAM",
665 .write = pl010_console_write,
666 .device = uart_console_device,
667 .setup = pl010_console_setup,
668 .flags = CON_PRINTBUFFER,
669 .index = -1,
670 .data = &amba_reg,
671 };
672
673 #define AMBA_CONSOLE &amba_console
674 #else
675 #define AMBA_CONSOLE NULL
676 #endif
677
678 static DEFINE_MUTEX(amba_reg_lock);
679 static struct uart_driver amba_reg = {
680 .owner = THIS_MODULE,
681 .driver_name = "ttyAM",
682 .dev_name = "ttyAM",
683 .major = SERIAL_AMBA_MAJOR,
684 .minor = SERIAL_AMBA_MINOR,
685 .nr = UART_NR,
686 .cons = AMBA_CONSOLE,
687 };
688
pl010_probe(struct amba_device * dev,const struct amba_id * id)689 static int pl010_probe(struct amba_device *dev, const struct amba_id *id)
690 {
691 struct uart_amba_port *uap;
692 void __iomem *base;
693 int i, ret;
694
695 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
696 if (amba_ports[i] == NULL)
697 break;
698
699 if (i == ARRAY_SIZE(amba_ports))
700 return -EBUSY;
701
702 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
703 GFP_KERNEL);
704 if (!uap)
705 return -ENOMEM;
706
707 base = devm_ioremap(&dev->dev, dev->res.start,
708 resource_size(&dev->res));
709 if (!base)
710 return -ENOMEM;
711
712 uap->clk = devm_clk_get(&dev->dev, NULL);
713 if (IS_ERR(uap->clk))
714 return PTR_ERR(uap->clk);
715
716 uap->port.dev = &dev->dev;
717 uap->port.mapbase = dev->res.start;
718 uap->port.membase = base;
719 uap->port.iotype = UPIO_MEM;
720 uap->port.irq = dev->irq[0];
721 uap->port.fifosize = 16;
722 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL010_CONSOLE);
723 uap->port.ops = &amba_pl010_pops;
724 uap->port.flags = UPF_BOOT_AUTOCONF;
725 uap->port.line = i;
726 uap->dev = dev;
727 uap->data = dev_get_platdata(&dev->dev);
728
729 amba_ports[i] = uap;
730
731 amba_set_drvdata(dev, uap);
732
733 mutex_lock(&amba_reg_lock);
734 if (!amba_reg.state) {
735 ret = uart_register_driver(&amba_reg);
736 if (ret < 0) {
737 mutex_unlock(&amba_reg_lock);
738 dev_err(uap->port.dev,
739 "Failed to register AMBA-PL010 driver\n");
740 return ret;
741 }
742 }
743 mutex_unlock(&amba_reg_lock);
744
745 ret = uart_add_one_port(&amba_reg, &uap->port);
746 if (ret)
747 amba_ports[i] = NULL;
748
749 return ret;
750 }
751
pl010_remove(struct amba_device * dev)752 static void pl010_remove(struct amba_device *dev)
753 {
754 struct uart_amba_port *uap = amba_get_drvdata(dev);
755 int i;
756 bool busy = false;
757
758 uart_remove_one_port(&amba_reg, &uap->port);
759
760 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
761 if (amba_ports[i] == uap)
762 amba_ports[i] = NULL;
763 else if (amba_ports[i])
764 busy = true;
765
766 if (!busy)
767 uart_unregister_driver(&amba_reg);
768 }
769
770 #ifdef CONFIG_PM_SLEEP
pl010_suspend(struct device * dev)771 static int pl010_suspend(struct device *dev)
772 {
773 struct uart_amba_port *uap = dev_get_drvdata(dev);
774
775 if (uap)
776 uart_suspend_port(&amba_reg, &uap->port);
777
778 return 0;
779 }
780
pl010_resume(struct device * dev)781 static int pl010_resume(struct device *dev)
782 {
783 struct uart_amba_port *uap = dev_get_drvdata(dev);
784
785 if (uap)
786 uart_resume_port(&amba_reg, &uap->port);
787
788 return 0;
789 }
790 #endif
791
792 static SIMPLE_DEV_PM_OPS(pl010_dev_pm_ops, pl010_suspend, pl010_resume);
793
794 static const struct amba_id pl010_ids[] = {
795 {
796 .id = 0x00041010,
797 .mask = 0x000fffff,
798 },
799 { 0, 0 },
800 };
801
802 MODULE_DEVICE_TABLE(amba, pl010_ids);
803
804 static struct amba_driver pl010_driver = {
805 .drv = {
806 .name = "uart-pl010",
807 .pm = &pl010_dev_pm_ops,
808 },
809 .id_table = pl010_ids,
810 .probe = pl010_probe,
811 .remove = pl010_remove,
812 };
813
pl010_init(void)814 static int __init pl010_init(void)
815 {
816 printk(KERN_INFO "Serial: AMBA driver\n");
817
818 return amba_driver_register(&pl010_driver);
819 }
820
pl010_exit(void)821 static void __exit pl010_exit(void)
822 {
823 amba_driver_unregister(&pl010_driver);
824 }
825
826 module_init(pl010_init);
827 module_exit(pl010_exit);
828
829 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
830 MODULE_DESCRIPTION("ARM AMBA serial port driver");
831 MODULE_LICENSE("GPL");
832