1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * ***************************************************************************
4 * Marvell Armada-3700 Serial Driver
5 * Author: Wilson Ding <dingwei@marvell.com>
6 * Copyright (C) 2015 Marvell International Ltd.
7 * ***************************************************************************
8 */
9
10 #include <linux/clk.h>
11 #include <linux/console.h>
12 #include <linux/delay.h>
13 #include <linux/device.h>
14 #include <linux/init.h>
15 #include <linux/io.h>
16 #include <linux/iopoll.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <linux/of_device.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_platform.h>
22 #include <linux/platform_device.h>
23 #include <linux/serial.h>
24 #include <linux/serial_core.h>
25 #include <linux/slab.h>
26 #include <linux/tty.h>
27 #include <linux/tty_flip.h>
28
29 /* Register Map */
30 #define UART_STD_RBR 0x00
31 #define UART_EXT_RBR 0x18
32
33 #define UART_STD_TSH 0x04
34 #define UART_EXT_TSH 0x1C
35
36 #define UART_STD_CTRL1 0x08
37 #define UART_EXT_CTRL1 0x04
38 #define CTRL_SOFT_RST BIT(31)
39 #define CTRL_TXFIFO_RST BIT(15)
40 #define CTRL_RXFIFO_RST BIT(14)
41 #define CTRL_SND_BRK_SEQ BIT(11)
42 #define CTRL_BRK_DET_INT BIT(3)
43 #define CTRL_FRM_ERR_INT BIT(2)
44 #define CTRL_PAR_ERR_INT BIT(1)
45 #define CTRL_OVR_ERR_INT BIT(0)
46 #define CTRL_BRK_INT (CTRL_BRK_DET_INT | CTRL_FRM_ERR_INT | \
47 CTRL_PAR_ERR_INT | CTRL_OVR_ERR_INT)
48
49 #define UART_STD_CTRL2 UART_STD_CTRL1
50 #define UART_EXT_CTRL2 0x20
51 #define CTRL_STD_TX_RDY_INT BIT(5)
52 #define CTRL_EXT_TX_RDY_INT BIT(6)
53 #define CTRL_STD_RX_RDY_INT BIT(4)
54 #define CTRL_EXT_RX_RDY_INT BIT(5)
55
56 #define UART_STAT 0x0C
57 #define STAT_TX_FIFO_EMP BIT(13)
58 #define STAT_TX_FIFO_FUL BIT(11)
59 #define STAT_TX_EMP BIT(6)
60 #define STAT_STD_TX_RDY BIT(5)
61 #define STAT_EXT_TX_RDY BIT(15)
62 #define STAT_STD_RX_RDY BIT(4)
63 #define STAT_EXT_RX_RDY BIT(14)
64 #define STAT_BRK_DET BIT(3)
65 #define STAT_FRM_ERR BIT(2)
66 #define STAT_PAR_ERR BIT(1)
67 #define STAT_OVR_ERR BIT(0)
68 #define STAT_BRK_ERR (STAT_BRK_DET | STAT_FRM_ERR \
69 | STAT_PAR_ERR | STAT_OVR_ERR)
70
71 #define UART_BRDV 0x10
72 #define BRDV_BAUD_MASK 0x3FF
73
74 #define UART_OSAMP 0x14
75 #define OSAMP_DEFAULT_DIVISOR 16
76 #define OSAMP_DIVISORS_MASK 0x3F3F3F3F
77
78 #define MVEBU_NR_UARTS 2
79
80 #define MVEBU_UART_TYPE "mvebu-uart"
81 #define DRIVER_NAME "mvebu_serial"
82
83 enum {
84 /* Either there is only one summed IRQ... */
85 UART_IRQ_SUM = 0,
86 /* ...or there are two separate IRQ for RX and TX */
87 UART_RX_IRQ = 0,
88 UART_TX_IRQ,
89 UART_IRQ_COUNT
90 };
91
92 /* Diverging register offsets */
93 struct uart_regs_layout {
94 unsigned int rbr;
95 unsigned int tsh;
96 unsigned int ctrl;
97 unsigned int intr;
98 };
99
100 /* Diverging flags */
101 struct uart_flags {
102 unsigned int ctrl_tx_rdy_int;
103 unsigned int ctrl_rx_rdy_int;
104 unsigned int stat_tx_rdy;
105 unsigned int stat_rx_rdy;
106 };
107
108 /* Driver data, a structure for each UART port */
109 struct mvebu_uart_driver_data {
110 bool is_ext;
111 struct uart_regs_layout regs;
112 struct uart_flags flags;
113 };
114
115 /* Saved registers during suspend */
116 struct mvebu_uart_pm_regs {
117 unsigned int rbr;
118 unsigned int tsh;
119 unsigned int ctrl;
120 unsigned int intr;
121 unsigned int stat;
122 unsigned int brdv;
123 unsigned int osamp;
124 };
125
126 /* MVEBU UART driver structure */
127 struct mvebu_uart {
128 struct uart_port *port;
129 struct clk *clk;
130 int irq[UART_IRQ_COUNT];
131 struct mvebu_uart_driver_data *data;
132 #if defined(CONFIG_PM)
133 struct mvebu_uart_pm_regs pm_regs;
134 #endif /* CONFIG_PM */
135 };
136
to_mvuart(struct uart_port * port)137 static struct mvebu_uart *to_mvuart(struct uart_port *port)
138 {
139 return (struct mvebu_uart *)port->private_data;
140 }
141
142 #define IS_EXTENDED(port) (to_mvuart(port)->data->is_ext)
143
144 #define UART_RBR(port) (to_mvuart(port)->data->regs.rbr)
145 #define UART_TSH(port) (to_mvuart(port)->data->regs.tsh)
146 #define UART_CTRL(port) (to_mvuart(port)->data->regs.ctrl)
147 #define UART_INTR(port) (to_mvuart(port)->data->regs.intr)
148
149 #define CTRL_TX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_tx_rdy_int)
150 #define CTRL_RX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_rx_rdy_int)
151 #define STAT_TX_RDY(port) (to_mvuart(port)->data->flags.stat_tx_rdy)
152 #define STAT_RX_RDY(port) (to_mvuart(port)->data->flags.stat_rx_rdy)
153
154 static struct uart_port mvebu_uart_ports[MVEBU_NR_UARTS];
155
156 /* Core UART Driver Operations */
mvebu_uart_tx_empty(struct uart_port * port)157 static unsigned int mvebu_uart_tx_empty(struct uart_port *port)
158 {
159 unsigned long flags;
160 unsigned int st;
161
162 spin_lock_irqsave(&port->lock, flags);
163 st = readl(port->membase + UART_STAT);
164 spin_unlock_irqrestore(&port->lock, flags);
165
166 return (st & STAT_TX_EMP) ? TIOCSER_TEMT : 0;
167 }
168
mvebu_uart_get_mctrl(struct uart_port * port)169 static unsigned int mvebu_uart_get_mctrl(struct uart_port *port)
170 {
171 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
172 }
173
mvebu_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)174 static void mvebu_uart_set_mctrl(struct uart_port *port,
175 unsigned int mctrl)
176 {
177 /*
178 * Even if we do not support configuring the modem control lines, this
179 * function must be proided to the serial core
180 */
181 }
182
mvebu_uart_stop_tx(struct uart_port * port)183 static void mvebu_uart_stop_tx(struct uart_port *port)
184 {
185 unsigned int ctl = readl(port->membase + UART_INTR(port));
186
187 ctl &= ~CTRL_TX_RDY_INT(port);
188 writel(ctl, port->membase + UART_INTR(port));
189 }
190
mvebu_uart_start_tx(struct uart_port * port)191 static void mvebu_uart_start_tx(struct uart_port *port)
192 {
193 unsigned int ctl;
194 struct circ_buf *xmit = &port->state->xmit;
195
196 if (IS_EXTENDED(port) && !uart_circ_empty(xmit)) {
197 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
198 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
199 port->icount.tx++;
200 }
201
202 ctl = readl(port->membase + UART_INTR(port));
203 ctl |= CTRL_TX_RDY_INT(port);
204 writel(ctl, port->membase + UART_INTR(port));
205 }
206
mvebu_uart_stop_rx(struct uart_port * port)207 static void mvebu_uart_stop_rx(struct uart_port *port)
208 {
209 unsigned int ctl;
210
211 ctl = readl(port->membase + UART_CTRL(port));
212 ctl &= ~CTRL_BRK_INT;
213 writel(ctl, port->membase + UART_CTRL(port));
214
215 ctl = readl(port->membase + UART_INTR(port));
216 ctl &= ~CTRL_RX_RDY_INT(port);
217 writel(ctl, port->membase + UART_INTR(port));
218 }
219
mvebu_uart_break_ctl(struct uart_port * port,int brk)220 static void mvebu_uart_break_ctl(struct uart_port *port, int brk)
221 {
222 unsigned int ctl;
223 unsigned long flags;
224
225 spin_lock_irqsave(&port->lock, flags);
226 ctl = readl(port->membase + UART_CTRL(port));
227 if (brk == -1)
228 ctl |= CTRL_SND_BRK_SEQ;
229 else
230 ctl &= ~CTRL_SND_BRK_SEQ;
231 writel(ctl, port->membase + UART_CTRL(port));
232 spin_unlock_irqrestore(&port->lock, flags);
233 }
234
mvebu_uart_rx_chars(struct uart_port * port,unsigned int status)235 static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status)
236 {
237 struct tty_port *tport = &port->state->port;
238 unsigned char ch = 0;
239 char flag = 0;
240 int ret;
241
242 do {
243 if (status & STAT_RX_RDY(port)) {
244 ch = readl(port->membase + UART_RBR(port));
245 ch &= 0xff;
246 flag = TTY_NORMAL;
247 port->icount.rx++;
248
249 if (status & STAT_PAR_ERR)
250 port->icount.parity++;
251 }
252
253 /*
254 * For UART2, error bits are not cleared on buffer read.
255 * This causes interrupt loop and system hang.
256 */
257 if (IS_EXTENDED(port) && (status & STAT_BRK_ERR)) {
258 ret = readl(port->membase + UART_STAT);
259 ret |= STAT_BRK_ERR;
260 writel(ret, port->membase + UART_STAT);
261 }
262
263 if (status & STAT_BRK_DET) {
264 port->icount.brk++;
265 status &= ~(STAT_FRM_ERR | STAT_PAR_ERR);
266 if (uart_handle_break(port))
267 goto ignore_char;
268 }
269
270 if (status & STAT_OVR_ERR)
271 port->icount.overrun++;
272
273 if (status & STAT_FRM_ERR)
274 port->icount.frame++;
275
276 if (uart_handle_sysrq_char(port, ch))
277 goto ignore_char;
278
279 if (status & port->ignore_status_mask & STAT_PAR_ERR)
280 status &= ~STAT_RX_RDY(port);
281
282 status &= port->read_status_mask;
283
284 if (status & STAT_PAR_ERR)
285 flag = TTY_PARITY;
286
287 status &= ~port->ignore_status_mask;
288
289 if (status & STAT_RX_RDY(port))
290 tty_insert_flip_char(tport, ch, flag);
291
292 if (status & STAT_BRK_DET)
293 tty_insert_flip_char(tport, 0, TTY_BREAK);
294
295 if (status & STAT_FRM_ERR)
296 tty_insert_flip_char(tport, 0, TTY_FRAME);
297
298 if (status & STAT_OVR_ERR)
299 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
300
301 ignore_char:
302 status = readl(port->membase + UART_STAT);
303 } while (status & (STAT_RX_RDY(port) | STAT_BRK_DET));
304
305 tty_flip_buffer_push(tport);
306 }
307
mvebu_uart_tx_chars(struct uart_port * port,unsigned int status)308 static void mvebu_uart_tx_chars(struct uart_port *port, unsigned int status)
309 {
310 struct circ_buf *xmit = &port->state->xmit;
311 unsigned int count;
312 unsigned int st;
313
314 if (port->x_char) {
315 writel(port->x_char, port->membase + UART_TSH(port));
316 port->icount.tx++;
317 port->x_char = 0;
318 return;
319 }
320
321 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
322 mvebu_uart_stop_tx(port);
323 return;
324 }
325
326 for (count = 0; count < port->fifosize; count++) {
327 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
328 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
329 port->icount.tx++;
330
331 if (uart_circ_empty(xmit))
332 break;
333
334 st = readl(port->membase + UART_STAT);
335 if (st & STAT_TX_FIFO_FUL)
336 break;
337 }
338
339 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
340 uart_write_wakeup(port);
341
342 if (uart_circ_empty(xmit))
343 mvebu_uart_stop_tx(port);
344 }
345
mvebu_uart_isr(int irq,void * dev_id)346 static irqreturn_t mvebu_uart_isr(int irq, void *dev_id)
347 {
348 struct uart_port *port = (struct uart_port *)dev_id;
349 unsigned int st = readl(port->membase + UART_STAT);
350
351 if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR |
352 STAT_BRK_DET))
353 mvebu_uart_rx_chars(port, st);
354
355 if (st & STAT_TX_RDY(port))
356 mvebu_uart_tx_chars(port, st);
357
358 return IRQ_HANDLED;
359 }
360
mvebu_uart_rx_isr(int irq,void * dev_id)361 static irqreturn_t mvebu_uart_rx_isr(int irq, void *dev_id)
362 {
363 struct uart_port *port = (struct uart_port *)dev_id;
364 unsigned int st = readl(port->membase + UART_STAT);
365
366 if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR |
367 STAT_BRK_DET))
368 mvebu_uart_rx_chars(port, st);
369
370 return IRQ_HANDLED;
371 }
372
mvebu_uart_tx_isr(int irq,void * dev_id)373 static irqreturn_t mvebu_uart_tx_isr(int irq, void *dev_id)
374 {
375 struct uart_port *port = (struct uart_port *)dev_id;
376 unsigned int st = readl(port->membase + UART_STAT);
377
378 if (st & STAT_TX_RDY(port))
379 mvebu_uart_tx_chars(port, st);
380
381 return IRQ_HANDLED;
382 }
383
mvebu_uart_startup(struct uart_port * port)384 static int mvebu_uart_startup(struct uart_port *port)
385 {
386 struct mvebu_uart *mvuart = to_mvuart(port);
387 unsigned int ctl;
388 int ret;
389
390 writel(CTRL_TXFIFO_RST | CTRL_RXFIFO_RST,
391 port->membase + UART_CTRL(port));
392 udelay(1);
393
394 /* Clear the error bits of state register before IRQ request */
395 ret = readl(port->membase + UART_STAT);
396 ret |= STAT_BRK_ERR;
397 writel(ret, port->membase + UART_STAT);
398
399 writel(CTRL_BRK_INT, port->membase + UART_CTRL(port));
400
401 ctl = readl(port->membase + UART_INTR(port));
402 ctl |= CTRL_RX_RDY_INT(port);
403 writel(ctl, port->membase + UART_INTR(port));
404
405 if (!mvuart->irq[UART_TX_IRQ]) {
406 /* Old bindings with just one interrupt (UART0 only) */
407 ret = devm_request_irq(port->dev, mvuart->irq[UART_IRQ_SUM],
408 mvebu_uart_isr, port->irqflags,
409 dev_name(port->dev), port);
410 if (ret) {
411 dev_err(port->dev, "unable to request IRQ %d\n",
412 mvuart->irq[UART_IRQ_SUM]);
413 return ret;
414 }
415 } else {
416 /* New bindings with an IRQ for RX and TX (both UART) */
417 ret = devm_request_irq(port->dev, mvuart->irq[UART_RX_IRQ],
418 mvebu_uart_rx_isr, port->irqflags,
419 dev_name(port->dev), port);
420 if (ret) {
421 dev_err(port->dev, "unable to request IRQ %d\n",
422 mvuart->irq[UART_RX_IRQ]);
423 return ret;
424 }
425
426 ret = devm_request_irq(port->dev, mvuart->irq[UART_TX_IRQ],
427 mvebu_uart_tx_isr, port->irqflags,
428 dev_name(port->dev),
429 port);
430 if (ret) {
431 dev_err(port->dev, "unable to request IRQ %d\n",
432 mvuart->irq[UART_TX_IRQ]);
433 devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ],
434 port);
435 return ret;
436 }
437 }
438
439 return 0;
440 }
441
mvebu_uart_shutdown(struct uart_port * port)442 static void mvebu_uart_shutdown(struct uart_port *port)
443 {
444 struct mvebu_uart *mvuart = to_mvuart(port);
445
446 writel(0, port->membase + UART_INTR(port));
447
448 if (!mvuart->irq[UART_TX_IRQ]) {
449 devm_free_irq(port->dev, mvuart->irq[UART_IRQ_SUM], port);
450 } else {
451 devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ], port);
452 devm_free_irq(port->dev, mvuart->irq[UART_TX_IRQ], port);
453 }
454 }
455
mvebu_uart_baud_rate_set(struct uart_port * port,unsigned int baud)456 static unsigned int mvebu_uart_baud_rate_set(struct uart_port *port, unsigned int baud)
457 {
458 unsigned int d_divisor, m_divisor;
459 u32 brdv, osamp;
460
461 if (!port->uartclk)
462 return 0;
463
464 /*
465 * The baudrate is derived from the UART clock thanks to two divisors:
466 * > D ("baud generator"): can divide the clock from 2 to 2^10 - 1.
467 * > M ("fractional divisor"): allows a better accuracy for
468 * baudrates higher than 230400.
469 *
470 * As the derivation of M is rather complicated, the code sticks to its
471 * default value (x16) when all the prescalers are zeroed, and only
472 * makes use of D to configure the desired baudrate.
473 */
474 m_divisor = OSAMP_DEFAULT_DIVISOR;
475 d_divisor = DIV_ROUND_CLOSEST(port->uartclk, baud * m_divisor);
476
477 brdv = readl(port->membase + UART_BRDV);
478 brdv &= ~BRDV_BAUD_MASK;
479 brdv |= d_divisor;
480 writel(brdv, port->membase + UART_BRDV);
481
482 osamp = readl(port->membase + UART_OSAMP);
483 osamp &= ~OSAMP_DIVISORS_MASK;
484 writel(osamp, port->membase + UART_OSAMP);
485
486 return DIV_ROUND_CLOSEST(port->uartclk, d_divisor * m_divisor);
487 }
488
mvebu_uart_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)489 static void mvebu_uart_set_termios(struct uart_port *port,
490 struct ktermios *termios,
491 struct ktermios *old)
492 {
493 unsigned long flags;
494 unsigned int baud, min_baud, max_baud;
495
496 spin_lock_irqsave(&port->lock, flags);
497
498 port->read_status_mask = STAT_RX_RDY(port) | STAT_OVR_ERR |
499 STAT_TX_RDY(port) | STAT_TX_FIFO_FUL;
500
501 if (termios->c_iflag & INPCK)
502 port->read_status_mask |= STAT_FRM_ERR | STAT_PAR_ERR;
503
504 port->ignore_status_mask = 0;
505 if (termios->c_iflag & IGNPAR)
506 port->ignore_status_mask |=
507 STAT_FRM_ERR | STAT_PAR_ERR | STAT_OVR_ERR;
508
509 if ((termios->c_cflag & CREAD) == 0)
510 port->ignore_status_mask |= STAT_RX_RDY(port) | STAT_BRK_ERR;
511
512 /*
513 * Maximal divisor is 1023 * 16 when using default (x16) scheme.
514 * Maximum achievable frequency with simple baudrate divisor is 230400.
515 * Since the error per bit frame would be of more than 15%, achieving
516 * higher frequencies would require to implement the fractional divisor
517 * feature.
518 */
519 min_baud = DIV_ROUND_UP(port->uartclk, 1023 * 16);
520 max_baud = 230400;
521
522 baud = uart_get_baud_rate(port, termios, old, min_baud, max_baud);
523 baud = mvebu_uart_baud_rate_set(port, baud);
524
525 /* In case baudrate cannot be changed, report previous old value */
526 if (baud == 0 && old)
527 baud = tty_termios_baud_rate(old);
528
529 /* Only the following flag changes are supported */
530 if (old) {
531 termios->c_iflag &= INPCK | IGNPAR;
532 termios->c_iflag |= old->c_iflag & ~(INPCK | IGNPAR);
533 termios->c_cflag &= CREAD | CBAUD;
534 termios->c_cflag |= old->c_cflag & ~(CREAD | CBAUD);
535 termios->c_cflag |= CS8;
536 }
537
538 if (baud != 0) {
539 tty_termios_encode_baud_rate(termios, baud, baud);
540 uart_update_timeout(port, termios->c_cflag, baud);
541 }
542
543 spin_unlock_irqrestore(&port->lock, flags);
544 }
545
mvebu_uart_type(struct uart_port * port)546 static const char *mvebu_uart_type(struct uart_port *port)
547 {
548 return MVEBU_UART_TYPE;
549 }
550
mvebu_uart_release_port(struct uart_port * port)551 static void mvebu_uart_release_port(struct uart_port *port)
552 {
553 /* Nothing to do here */
554 }
555
mvebu_uart_request_port(struct uart_port * port)556 static int mvebu_uart_request_port(struct uart_port *port)
557 {
558 return 0;
559 }
560
561 #ifdef CONFIG_CONSOLE_POLL
mvebu_uart_get_poll_char(struct uart_port * port)562 static int mvebu_uart_get_poll_char(struct uart_port *port)
563 {
564 unsigned int st = readl(port->membase + UART_STAT);
565
566 if (!(st & STAT_RX_RDY(port)))
567 return NO_POLL_CHAR;
568
569 return readl(port->membase + UART_RBR(port));
570 }
571
mvebu_uart_put_poll_char(struct uart_port * port,unsigned char c)572 static void mvebu_uart_put_poll_char(struct uart_port *port, unsigned char c)
573 {
574 unsigned int st;
575
576 for (;;) {
577 st = readl(port->membase + UART_STAT);
578
579 if (!(st & STAT_TX_FIFO_FUL))
580 break;
581
582 udelay(1);
583 }
584
585 writel(c, port->membase + UART_TSH(port));
586 }
587 #endif
588
589 static const struct uart_ops mvebu_uart_ops = {
590 .tx_empty = mvebu_uart_tx_empty,
591 .set_mctrl = mvebu_uart_set_mctrl,
592 .get_mctrl = mvebu_uart_get_mctrl,
593 .stop_tx = mvebu_uart_stop_tx,
594 .start_tx = mvebu_uart_start_tx,
595 .stop_rx = mvebu_uart_stop_rx,
596 .break_ctl = mvebu_uart_break_ctl,
597 .startup = mvebu_uart_startup,
598 .shutdown = mvebu_uart_shutdown,
599 .set_termios = mvebu_uart_set_termios,
600 .type = mvebu_uart_type,
601 .release_port = mvebu_uart_release_port,
602 .request_port = mvebu_uart_request_port,
603 #ifdef CONFIG_CONSOLE_POLL
604 .poll_get_char = mvebu_uart_get_poll_char,
605 .poll_put_char = mvebu_uart_put_poll_char,
606 #endif
607 };
608
609 /* Console Driver Operations */
610
611 #ifdef CONFIG_SERIAL_MVEBU_CONSOLE
612 /* Early Console */
mvebu_uart_putc(struct uart_port * port,int c)613 static void mvebu_uart_putc(struct uart_port *port, int c)
614 {
615 unsigned int st;
616
617 for (;;) {
618 st = readl(port->membase + UART_STAT);
619 if (!(st & STAT_TX_FIFO_FUL))
620 break;
621 }
622
623 /* At early stage, DT is not parsed yet, only use UART0 */
624 writel(c, port->membase + UART_STD_TSH);
625
626 for (;;) {
627 st = readl(port->membase + UART_STAT);
628 if (st & STAT_TX_FIFO_EMP)
629 break;
630 }
631 }
632
mvebu_uart_putc_early_write(struct console * con,const char * s,unsigned int n)633 static void mvebu_uart_putc_early_write(struct console *con,
634 const char *s,
635 unsigned int n)
636 {
637 struct earlycon_device *dev = con->data;
638
639 uart_console_write(&dev->port, s, n, mvebu_uart_putc);
640 }
641
642 static int __init
mvebu_uart_early_console_setup(struct earlycon_device * device,const char * opt)643 mvebu_uart_early_console_setup(struct earlycon_device *device,
644 const char *opt)
645 {
646 if (!device->port.membase)
647 return -ENODEV;
648
649 device->con->write = mvebu_uart_putc_early_write;
650
651 return 0;
652 }
653
654 EARLYCON_DECLARE(ar3700_uart, mvebu_uart_early_console_setup);
655 OF_EARLYCON_DECLARE(ar3700_uart, "marvell,armada-3700-uart",
656 mvebu_uart_early_console_setup);
657
wait_for_xmitr(struct uart_port * port)658 static void wait_for_xmitr(struct uart_port *port)
659 {
660 u32 val;
661
662 readl_poll_timeout_atomic(port->membase + UART_STAT, val,
663 (val & STAT_TX_RDY(port)), 1, 10000);
664 }
665
wait_for_xmite(struct uart_port * port)666 static void wait_for_xmite(struct uart_port *port)
667 {
668 u32 val;
669
670 readl_poll_timeout_atomic(port->membase + UART_STAT, val,
671 (val & STAT_TX_EMP), 1, 10000);
672 }
673
mvebu_uart_console_putchar(struct uart_port * port,int ch)674 static void mvebu_uart_console_putchar(struct uart_port *port, int ch)
675 {
676 wait_for_xmitr(port);
677 writel(ch, port->membase + UART_TSH(port));
678 }
679
mvebu_uart_console_write(struct console * co,const char * s,unsigned int count)680 static void mvebu_uart_console_write(struct console *co, const char *s,
681 unsigned int count)
682 {
683 struct uart_port *port = &mvebu_uart_ports[co->index];
684 unsigned long flags;
685 unsigned int ier, intr, ctl;
686 int locked = 1;
687
688 if (oops_in_progress)
689 locked = spin_trylock_irqsave(&port->lock, flags);
690 else
691 spin_lock_irqsave(&port->lock, flags);
692
693 ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT;
694 intr = readl(port->membase + UART_INTR(port)) &
695 (CTRL_RX_RDY_INT(port) | CTRL_TX_RDY_INT(port));
696 writel(0, port->membase + UART_CTRL(port));
697 writel(0, port->membase + UART_INTR(port));
698
699 uart_console_write(port, s, count, mvebu_uart_console_putchar);
700
701 wait_for_xmite(port);
702
703 if (ier)
704 writel(ier, port->membase + UART_CTRL(port));
705
706 if (intr) {
707 ctl = intr | readl(port->membase + UART_INTR(port));
708 writel(ctl, port->membase + UART_INTR(port));
709 }
710
711 if (locked)
712 spin_unlock_irqrestore(&port->lock, flags);
713 }
714
mvebu_uart_console_setup(struct console * co,char * options)715 static int mvebu_uart_console_setup(struct console *co, char *options)
716 {
717 struct uart_port *port;
718 int baud = 9600;
719 int bits = 8;
720 int parity = 'n';
721 int flow = 'n';
722
723 if (co->index < 0 || co->index >= MVEBU_NR_UARTS)
724 return -EINVAL;
725
726 port = &mvebu_uart_ports[co->index];
727
728 if (!port->mapbase || !port->membase) {
729 pr_debug("console on ttyMV%i not present\n", co->index);
730 return -ENODEV;
731 }
732
733 if (options)
734 uart_parse_options(options, &baud, &parity, &bits, &flow);
735
736 return uart_set_options(port, co, baud, parity, bits, flow);
737 }
738
739 static struct uart_driver mvebu_uart_driver;
740
741 static struct console mvebu_uart_console = {
742 .name = "ttyMV",
743 .write = mvebu_uart_console_write,
744 .device = uart_console_device,
745 .setup = mvebu_uart_console_setup,
746 .flags = CON_PRINTBUFFER,
747 .index = -1,
748 .data = &mvebu_uart_driver,
749 };
750
mvebu_uart_console_init(void)751 static int __init mvebu_uart_console_init(void)
752 {
753 register_console(&mvebu_uart_console);
754 return 0;
755 }
756
757 console_initcall(mvebu_uart_console_init);
758
759
760 #endif /* CONFIG_SERIAL_MVEBU_CONSOLE */
761
762 static struct uart_driver mvebu_uart_driver = {
763 .owner = THIS_MODULE,
764 .driver_name = DRIVER_NAME,
765 .dev_name = "ttyMV",
766 .nr = MVEBU_NR_UARTS,
767 #ifdef CONFIG_SERIAL_MVEBU_CONSOLE
768 .cons = &mvebu_uart_console,
769 #endif
770 };
771
772 #if defined(CONFIG_PM)
mvebu_uart_suspend(struct device * dev)773 static int mvebu_uart_suspend(struct device *dev)
774 {
775 struct mvebu_uart *mvuart = dev_get_drvdata(dev);
776 struct uart_port *port = mvuart->port;
777
778 uart_suspend_port(&mvebu_uart_driver, port);
779
780 mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port));
781 mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port));
782 mvuart->pm_regs.ctrl = readl(port->membase + UART_CTRL(port));
783 mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port));
784 mvuart->pm_regs.stat = readl(port->membase + UART_STAT);
785 mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV);
786 mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP);
787
788 device_set_wakeup_enable(dev, true);
789
790 return 0;
791 }
792
mvebu_uart_resume(struct device * dev)793 static int mvebu_uart_resume(struct device *dev)
794 {
795 struct mvebu_uart *mvuart = dev_get_drvdata(dev);
796 struct uart_port *port = mvuart->port;
797
798 writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port));
799 writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port));
800 writel(mvuart->pm_regs.ctrl, port->membase + UART_CTRL(port));
801 writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port));
802 writel(mvuart->pm_regs.stat, port->membase + UART_STAT);
803 writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV);
804 writel(mvuart->pm_regs.osamp, port->membase + UART_OSAMP);
805
806 uart_resume_port(&mvebu_uart_driver, port);
807
808 return 0;
809 }
810
811 static const struct dev_pm_ops mvebu_uart_pm_ops = {
812 .suspend = mvebu_uart_suspend,
813 .resume = mvebu_uart_resume,
814 };
815 #endif /* CONFIG_PM */
816
817 static const struct of_device_id mvebu_uart_of_match[];
818
819 /* Counter to keep track of each UART port id when not using CONFIG_OF */
820 static int uart_num_counter;
821
mvebu_uart_probe(struct platform_device * pdev)822 static int mvebu_uart_probe(struct platform_device *pdev)
823 {
824 struct resource *reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
825 const struct of_device_id *match = of_match_device(mvebu_uart_of_match,
826 &pdev->dev);
827 struct uart_port *port;
828 struct mvebu_uart *mvuart;
829 int id, irq;
830
831 if (!reg) {
832 dev_err(&pdev->dev, "no registers defined\n");
833 return -EINVAL;
834 }
835
836 /* Assume that all UART ports have a DT alias or none has */
837 id = of_alias_get_id(pdev->dev.of_node, "serial");
838 if (!pdev->dev.of_node || id < 0)
839 pdev->id = uart_num_counter++;
840 else
841 pdev->id = id;
842
843 if (pdev->id >= MVEBU_NR_UARTS) {
844 dev_err(&pdev->dev, "cannot have more than %d UART ports\n",
845 MVEBU_NR_UARTS);
846 return -EINVAL;
847 }
848
849 port = &mvebu_uart_ports[pdev->id];
850
851 spin_lock_init(&port->lock);
852
853 port->dev = &pdev->dev;
854 port->type = PORT_MVEBU;
855 port->ops = &mvebu_uart_ops;
856 port->regshift = 0;
857
858 port->fifosize = 32;
859 port->iotype = UPIO_MEM32;
860 port->flags = UPF_FIXED_PORT;
861 port->line = pdev->id;
862
863 /*
864 * IRQ number is not stored in this structure because we may have two of
865 * them per port (RX and TX). Instead, use the driver UART structure
866 * array so called ->irq[].
867 */
868 port->irq = 0;
869 port->irqflags = 0;
870 port->mapbase = reg->start;
871
872 port->membase = devm_ioremap_resource(&pdev->dev, reg);
873 if (IS_ERR(port->membase))
874 return PTR_ERR(port->membase);
875
876 mvuart = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart),
877 GFP_KERNEL);
878 if (!mvuart)
879 return -ENOMEM;
880
881 /* Get controller data depending on the compatible string */
882 mvuart->data = (struct mvebu_uart_driver_data *)match->data;
883 mvuart->port = port;
884
885 port->private_data = mvuart;
886 platform_set_drvdata(pdev, mvuart);
887
888 /* Get fixed clock frequency */
889 mvuart->clk = devm_clk_get(&pdev->dev, NULL);
890 if (IS_ERR(mvuart->clk)) {
891 if (PTR_ERR(mvuart->clk) == -EPROBE_DEFER)
892 return PTR_ERR(mvuart->clk);
893
894 if (IS_EXTENDED(port)) {
895 dev_err(&pdev->dev, "unable to get UART clock\n");
896 return PTR_ERR(mvuart->clk);
897 }
898 } else {
899 if (!clk_prepare_enable(mvuart->clk))
900 port->uartclk = clk_get_rate(mvuart->clk);
901 }
902
903 /* Manage interrupts */
904 if (platform_irq_count(pdev) == 1) {
905 /* Old bindings: no name on the single unamed UART0 IRQ */
906 irq = platform_get_irq(pdev, 0);
907 if (irq < 0)
908 return irq;
909
910 mvuart->irq[UART_IRQ_SUM] = irq;
911 } else {
912 /*
913 * New bindings: named interrupts (RX, TX) for both UARTS,
914 * only make use of uart-rx and uart-tx interrupts, do not use
915 * uart-sum of UART0 port.
916 */
917 irq = platform_get_irq_byname(pdev, "uart-rx");
918 if (irq < 0)
919 return irq;
920
921 mvuart->irq[UART_RX_IRQ] = irq;
922
923 irq = platform_get_irq_byname(pdev, "uart-tx");
924 if (irq < 0)
925 return irq;
926
927 mvuart->irq[UART_TX_IRQ] = irq;
928 }
929
930 /* UART Soft Reset*/
931 writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port));
932 udelay(1);
933 writel(0, port->membase + UART_CTRL(port));
934
935 return uart_add_one_port(&mvebu_uart_driver, port);
936 }
937
938 static struct mvebu_uart_driver_data uart_std_driver_data = {
939 .is_ext = false,
940 .regs.rbr = UART_STD_RBR,
941 .regs.tsh = UART_STD_TSH,
942 .regs.ctrl = UART_STD_CTRL1,
943 .regs.intr = UART_STD_CTRL2,
944 .flags.ctrl_tx_rdy_int = CTRL_STD_TX_RDY_INT,
945 .flags.ctrl_rx_rdy_int = CTRL_STD_RX_RDY_INT,
946 .flags.stat_tx_rdy = STAT_STD_TX_RDY,
947 .flags.stat_rx_rdy = STAT_STD_RX_RDY,
948 };
949
950 static struct mvebu_uart_driver_data uart_ext_driver_data = {
951 .is_ext = true,
952 .regs.rbr = UART_EXT_RBR,
953 .regs.tsh = UART_EXT_TSH,
954 .regs.ctrl = UART_EXT_CTRL1,
955 .regs.intr = UART_EXT_CTRL2,
956 .flags.ctrl_tx_rdy_int = CTRL_EXT_TX_RDY_INT,
957 .flags.ctrl_rx_rdy_int = CTRL_EXT_RX_RDY_INT,
958 .flags.stat_tx_rdy = STAT_EXT_TX_RDY,
959 .flags.stat_rx_rdy = STAT_EXT_RX_RDY,
960 };
961
962 /* Match table for of_platform binding */
963 static const struct of_device_id mvebu_uart_of_match[] = {
964 {
965 .compatible = "marvell,armada-3700-uart",
966 .data = (void *)&uart_std_driver_data,
967 },
968 {
969 .compatible = "marvell,armada-3700-uart-ext",
970 .data = (void *)&uart_ext_driver_data,
971 },
972 {}
973 };
974
975 static struct platform_driver mvebu_uart_platform_driver = {
976 .probe = mvebu_uart_probe,
977 .driver = {
978 .name = "mvebu-uart",
979 .of_match_table = of_match_ptr(mvebu_uart_of_match),
980 .suppress_bind_attrs = true,
981 #if defined(CONFIG_PM)
982 .pm = &mvebu_uart_pm_ops,
983 #endif /* CONFIG_PM */
984 },
985 };
986
mvebu_uart_init(void)987 static int __init mvebu_uart_init(void)
988 {
989 int ret;
990
991 ret = uart_register_driver(&mvebu_uart_driver);
992 if (ret)
993 return ret;
994
995 ret = platform_driver_register(&mvebu_uart_platform_driver);
996 if (ret)
997 uart_unregister_driver(&mvebu_uart_driver);
998
999 return ret;
1000 }
1001 arch_initcall(mvebu_uart_init);
1002