1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
4 * Author: Jon Ringle <jringle@gridpoint.com>
5 *
6 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
7 */
8
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11 #include <linux/bitops.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/i2c.h>
17 #include <linux/mod_devicetable.h>
18 #include <linux/module.h>
19 #include <linux/property.h>
20 #include <linux/regmap.h>
21 #include <linux/serial_core.h>
22 #include <linux/serial.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/spi/spi.h>
26 #include <linux/uaccess.h>
27 #include <linux/units.h>
28 #include <uapi/linux/sched/types.h>
29
30 #define SC16IS7XX_NAME "sc16is7xx"
31 #define SC16IS7XX_MAX_DEVS 8
32
33 /* SC16IS7XX register definitions */
34 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */
35 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */
36 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */
37 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */
38 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */
39 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */
40 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */
41 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */
42 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */
43 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
44 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
45 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
46 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction
47 * - only on 75x/76x
48 */
49 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State
50 * - only on 75x/76x
51 */
52 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable
53 * - only on 75x/76x
54 */
55 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control
56 * - only on 75x/76x
57 */
58 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
59
60 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
61 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */
62 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
63
64 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
65 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */
66 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
67
68 /* Enhanced Register set: Only if (LCR == 0xBF) */
69 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */
70 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */
71 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */
72 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */
73 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */
74
75 /* IER register bits */
76 #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */
77 #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register
78 * interrupt */
79 #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status
80 * interrupt */
81 #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status
82 * interrupt */
83
84 /* IER register bits - write only if (EFR[4] == 1) */
85 #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */
86 #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */
87 #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */
88 #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */
89
90 /* FCR register bits */
91 #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */
92 #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */
93 #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */
94 #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */
95 #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */
96
97 /* FCR register bits - write only if (EFR[4] == 1) */
98 #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */
99 #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */
100
101 /* IIR register bits */
102 #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */
103 #define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */
104 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */
105 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */
106 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */
107 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
108 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt
109 * - only on 75x/76x
110 */
111 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state
112 * - only on 75x/76x
113 */
114 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
115 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state
116 * from active (LOW)
117 * to inactive (HIGH)
118 */
119 /* LCR register bits */
120 #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
121 #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
122 *
123 * Word length bits table:
124 * 00 -> 5 bit words
125 * 01 -> 6 bit words
126 * 10 -> 7 bit words
127 * 11 -> 8 bit words
128 */
129 #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
130 *
131 * STOP length bit table:
132 * 0 -> 1 stop bit
133 * 1 -> 1-1.5 stop bits if
134 * word length is 5,
135 * 2 stop bits otherwise
136 */
137 #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
138 #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
139 #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
140 #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
141 #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */
142 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00)
143 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
144 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
145 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
146 #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special
147 * reg set */
148 #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced
149 * reg set */
150
151 /* MCR register bits */
152 #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement
153 * - only on 75x/76x
154 */
155 #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */
156 #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */
157 #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */
158 #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any
159 * - write enabled
160 * if (EFR[4] == 1)
161 */
162 #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode
163 * - write enabled
164 * if (EFR[4] == 1)
165 */
166 #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4
167 * - write enabled
168 * if (EFR[4] == 1)
169 */
170
171 /* LSR register bits */
172 #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */
173 #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */
174 #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */
175 #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */
176 #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */
177 #define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */
178 #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */
179 #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */
180 #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */
181
182 /* MSR register bits */
183 #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */
184 #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready
185 * or (IO4)
186 * - only on 75x/76x
187 */
188 #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator
189 * or (IO7)
190 * - only on 75x/76x
191 */
192 #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect
193 * or (IO6)
194 * - only on 75x/76x
195 */
196 #define SC16IS7XX_MSR_CTS_BIT (1 << 4) /* CTS */
197 #define SC16IS7XX_MSR_DSR_BIT (1 << 5) /* DSR (IO4)
198 * - only on 75x/76x
199 */
200 #define SC16IS7XX_MSR_RI_BIT (1 << 6) /* RI (IO7)
201 * - only on 75x/76x
202 */
203 #define SC16IS7XX_MSR_CD_BIT (1 << 7) /* CD (IO6)
204 * - only on 75x/76x
205 */
206 #define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */
207
208 /*
209 * TCR register bits
210 * TCR trigger levels are available from 0 to 60 characters with a granularity
211 * of four.
212 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
213 * no built-in hardware check to make sure this condition is met. Also, the TCR
214 * must be programmed with this condition before auto RTS or software flow
215 * control is enabled to avoid spurious operation of the device.
216 */
217 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
218 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
219
220 /*
221 * TLR register bits
222 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
223 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
224 * trigger levels. Trigger levels from 4 characters to 60 characters are
225 * available with a granularity of four.
226 *
227 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the
228 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
229 * the trigger level defined in FCR is discarded. This applies to both transmit
230 * FIFO and receive FIFO trigger level setting.
231 *
232 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
233 * default state, that is, '00'.
234 */
235 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
236 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
237
238 /* IOControl register bits (Only 750/760) */
239 #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */
240 #define SC16IS7XX_IOCONTROL_MODEM_BIT (1 << 1) /* Enable GPIO[7:4] as modem pins */
241 #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */
242
243 /* EFCR register bits */
244 #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop
245 * mode (RS485) */
246 #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */
247 #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */
248 #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */
249 #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */
250 #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode
251 * 0 = rate upto 115.2 kbit/s
252 * - Only 750/760
253 * 1 = rate upto 1.152 Mbit/s
254 * - Only 760
255 */
256
257 /* EFR register bits */
258 #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */
259 #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */
260 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */
261 #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions
262 * and writing to IER[7:4],
263 * FCR[5:4], MCR[7:5]
264 */
265 #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */
266 #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2
267 *
268 * SWFLOW bits 3 & 2 table:
269 * 00 -> no transmitter flow
270 * control
271 * 01 -> transmitter generates
272 * XON2 and XOFF2
273 * 10 -> transmitter generates
274 * XON1 and XOFF1
275 * 11 -> transmitter generates
276 * XON1, XON2, XOFF1 and
277 * XOFF2
278 */
279 #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */
280 #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3
281 *
282 * SWFLOW bits 3 & 2 table:
283 * 00 -> no received flow
284 * control
285 * 01 -> receiver compares
286 * XON2 and XOFF2
287 * 10 -> receiver compares
288 * XON1 and XOFF1
289 * 11 -> receiver compares
290 * XON1, XON2, XOFF1 and
291 * XOFF2
292 */
293
294 /* Misc definitions */
295 #define SC16IS7XX_FIFO_SIZE (64)
296 #define SC16IS7XX_REG_SHIFT 2
297
298 struct sc16is7xx_devtype {
299 char name[10];
300 int nr_gpio;
301 int nr_uart;
302 };
303
304 #define SC16IS7XX_RECONF_MD (1 << 0)
305 #define SC16IS7XX_RECONF_IER (1 << 1)
306 #define SC16IS7XX_RECONF_RS485 (1 << 2)
307
308 struct sc16is7xx_one_config {
309 unsigned int flags;
310 u8 ier_clear;
311 };
312
313 struct sc16is7xx_one {
314 struct uart_port port;
315 u8 line;
316 struct kthread_work tx_work;
317 struct kthread_work reg_work;
318 struct sc16is7xx_one_config config;
319 bool irda_mode;
320 };
321
322 struct sc16is7xx_port {
323 const struct sc16is7xx_devtype *devtype;
324 struct regmap *regmap;
325 struct clk *clk;
326 #ifdef CONFIG_GPIOLIB
327 struct gpio_chip gpio;
328 #endif
329 unsigned char buf[SC16IS7XX_FIFO_SIZE];
330 struct kthread_worker kworker;
331 struct task_struct *kworker_task;
332 struct mutex efr_lock;
333 struct sc16is7xx_one p[];
334 };
335
336 static unsigned long sc16is7xx_lines;
337
338 static struct uart_driver sc16is7xx_uart = {
339 .owner = THIS_MODULE,
340 .dev_name = "ttySC",
341 .nr = SC16IS7XX_MAX_DEVS,
342 };
343
344 #define to_sc16is7xx_port(p,e) ((container_of((p), struct sc16is7xx_port, e)))
345 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e)))
346
sc16is7xx_line(struct uart_port * port)347 static int sc16is7xx_line(struct uart_port *port)
348 {
349 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
350
351 return one->line;
352 }
353
sc16is7xx_port_read(struct uart_port * port,u8 reg)354 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
355 {
356 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
357 unsigned int val = 0;
358 const u8 line = sc16is7xx_line(port);
359
360 regmap_read(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, &val);
361
362 return val;
363 }
364
sc16is7xx_port_write(struct uart_port * port,u8 reg,u8 val)365 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
366 {
367 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
368 const u8 line = sc16is7xx_line(port);
369
370 regmap_write(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, val);
371 }
372
sc16is7xx_fifo_read(struct uart_port * port,unsigned int rxlen)373 static void sc16is7xx_fifo_read(struct uart_port *port, unsigned int rxlen)
374 {
375 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
376 const u8 line = sc16is7xx_line(port);
377 u8 addr = (SC16IS7XX_RHR_REG << SC16IS7XX_REG_SHIFT) | line;
378
379 regcache_cache_bypass(s->regmap, true);
380 regmap_raw_read(s->regmap, addr, s->buf, rxlen);
381 regcache_cache_bypass(s->regmap, false);
382 }
383
sc16is7xx_fifo_write(struct uart_port * port,u8 to_send)384 static void sc16is7xx_fifo_write(struct uart_port *port, u8 to_send)
385 {
386 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
387 const u8 line = sc16is7xx_line(port);
388 u8 addr = (SC16IS7XX_THR_REG << SC16IS7XX_REG_SHIFT) | line;
389
390 /*
391 * Don't send zero-length data, at least on SPI it confuses the chip
392 * delivering wrong TXLVL data.
393 */
394 if (unlikely(!to_send))
395 return;
396
397 regcache_cache_bypass(s->regmap, true);
398 regmap_raw_write(s->regmap, addr, s->buf, to_send);
399 regcache_cache_bypass(s->regmap, false);
400 }
401
sc16is7xx_port_update(struct uart_port * port,u8 reg,u8 mask,u8 val)402 static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
403 u8 mask, u8 val)
404 {
405 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
406 const u8 line = sc16is7xx_line(port);
407
408 regmap_update_bits(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line,
409 mask, val);
410 }
411
sc16is7xx_alloc_line(void)412 static int sc16is7xx_alloc_line(void)
413 {
414 int i;
415
416 BUILD_BUG_ON(SC16IS7XX_MAX_DEVS > BITS_PER_LONG);
417
418 for (i = 0; i < SC16IS7XX_MAX_DEVS; i++)
419 if (!test_and_set_bit(i, &sc16is7xx_lines))
420 break;
421
422 return i;
423 }
424
sc16is7xx_power(struct uart_port * port,int on)425 static void sc16is7xx_power(struct uart_port *port, int on)
426 {
427 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
428 SC16IS7XX_IER_SLEEP_BIT,
429 on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
430 }
431
432 static const struct sc16is7xx_devtype sc16is74x_devtype = {
433 .name = "SC16IS74X",
434 .nr_gpio = 0,
435 .nr_uart = 1,
436 };
437
438 static const struct sc16is7xx_devtype sc16is750_devtype = {
439 .name = "SC16IS750",
440 .nr_gpio = 8,
441 .nr_uart = 1,
442 };
443
444 static const struct sc16is7xx_devtype sc16is752_devtype = {
445 .name = "SC16IS752",
446 .nr_gpio = 8,
447 .nr_uart = 2,
448 };
449
450 static const struct sc16is7xx_devtype sc16is760_devtype = {
451 .name = "SC16IS760",
452 .nr_gpio = 8,
453 .nr_uart = 1,
454 };
455
456 static const struct sc16is7xx_devtype sc16is762_devtype = {
457 .name = "SC16IS762",
458 .nr_gpio = 8,
459 .nr_uart = 2,
460 };
461
sc16is7xx_regmap_volatile(struct device * dev,unsigned int reg)462 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
463 {
464 switch (reg >> SC16IS7XX_REG_SHIFT) {
465 case SC16IS7XX_RHR_REG:
466 case SC16IS7XX_IIR_REG:
467 case SC16IS7XX_LSR_REG:
468 case SC16IS7XX_MSR_REG:
469 case SC16IS7XX_TXLVL_REG:
470 case SC16IS7XX_RXLVL_REG:
471 case SC16IS7XX_IOSTATE_REG:
472 return true;
473 default:
474 break;
475 }
476
477 return false;
478 }
479
sc16is7xx_regmap_precious(struct device * dev,unsigned int reg)480 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
481 {
482 switch (reg >> SC16IS7XX_REG_SHIFT) {
483 case SC16IS7XX_RHR_REG:
484 return true;
485 default:
486 break;
487 }
488
489 return false;
490 }
491
sc16is7xx_set_baud(struct uart_port * port,int baud)492 static int sc16is7xx_set_baud(struct uart_port *port, int baud)
493 {
494 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
495 u8 lcr;
496 u8 prescaler = 0;
497 unsigned long clk = port->uartclk, div = clk / 16 / baud;
498
499 if (div > 0xffff) {
500 prescaler = SC16IS7XX_MCR_CLKSEL_BIT;
501 div /= 4;
502 }
503
504 /* In an amazing feat of design, the Enhanced Features Register shares
505 * the address of the Interrupt Identification Register, and is
506 * switched in by writing a magic value (0xbf) to the Line Control
507 * Register. Any interrupt firing during this time will see the EFR
508 * where it expects the IIR to be, leading to "Unexpected interrupt"
509 * messages.
510 *
511 * Prevent this possibility by claiming a mutex while accessing the
512 * EFR, and claiming the same mutex from within the interrupt handler.
513 * This is similar to disabling the interrupt, but that doesn't work
514 * because the bulk of the interrupt processing is run as a workqueue
515 * job in thread context.
516 */
517 mutex_lock(&s->efr_lock);
518
519 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
520
521 /* Open the LCR divisors for configuration */
522 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
523 SC16IS7XX_LCR_CONF_MODE_B);
524
525 /* Enable enhanced features */
526 regcache_cache_bypass(s->regmap, true);
527 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
528 SC16IS7XX_EFR_ENABLE_BIT);
529 regcache_cache_bypass(s->regmap, false);
530
531 /* Put LCR back to the normal mode */
532 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
533
534 mutex_unlock(&s->efr_lock);
535
536 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
537 SC16IS7XX_MCR_CLKSEL_BIT,
538 prescaler);
539
540 /* Open the LCR divisors for configuration */
541 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
542 SC16IS7XX_LCR_CONF_MODE_A);
543
544 /* Write the new divisor */
545 regcache_cache_bypass(s->regmap, true);
546 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
547 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
548 regcache_cache_bypass(s->regmap, false);
549
550 /* Put LCR back to the normal mode */
551 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
552
553 return DIV_ROUND_CLOSEST(clk / 16, div);
554 }
555
sc16is7xx_handle_rx(struct uart_port * port,unsigned int rxlen,unsigned int iir)556 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
557 unsigned int iir)
558 {
559 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
560 unsigned int lsr = 0, ch, flag, bytes_read, i;
561 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false;
562
563 if (unlikely(rxlen >= sizeof(s->buf))) {
564 dev_warn_ratelimited(port->dev,
565 "ttySC%i: Possible RX FIFO overrun: %d\n",
566 port->line, rxlen);
567 port->icount.buf_overrun++;
568 /* Ensure sanity of RX level */
569 rxlen = sizeof(s->buf);
570 }
571
572 while (rxlen) {
573 /* Only read lsr if there are possible errors in FIFO */
574 if (read_lsr) {
575 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
576 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
577 read_lsr = false; /* No errors left in FIFO */
578 } else
579 lsr = 0;
580
581 if (read_lsr) {
582 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
583 bytes_read = 1;
584 } else {
585 sc16is7xx_fifo_read(port, rxlen);
586 bytes_read = rxlen;
587 }
588
589 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
590
591 port->icount.rx++;
592 flag = TTY_NORMAL;
593
594 if (unlikely(lsr)) {
595 if (lsr & SC16IS7XX_LSR_BI_BIT) {
596 port->icount.brk++;
597 if (uart_handle_break(port))
598 continue;
599 } else if (lsr & SC16IS7XX_LSR_PE_BIT)
600 port->icount.parity++;
601 else if (lsr & SC16IS7XX_LSR_FE_BIT)
602 port->icount.frame++;
603 else if (lsr & SC16IS7XX_LSR_OE_BIT)
604 port->icount.overrun++;
605
606 lsr &= port->read_status_mask;
607 if (lsr & SC16IS7XX_LSR_BI_BIT)
608 flag = TTY_BREAK;
609 else if (lsr & SC16IS7XX_LSR_PE_BIT)
610 flag = TTY_PARITY;
611 else if (lsr & SC16IS7XX_LSR_FE_BIT)
612 flag = TTY_FRAME;
613 else if (lsr & SC16IS7XX_LSR_OE_BIT)
614 flag = TTY_OVERRUN;
615 }
616
617 for (i = 0; i < bytes_read; ++i) {
618 ch = s->buf[i];
619 if (uart_handle_sysrq_char(port, ch))
620 continue;
621
622 if (lsr & port->ignore_status_mask)
623 continue;
624
625 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
626 flag);
627 }
628 rxlen -= bytes_read;
629 }
630
631 tty_flip_buffer_push(&port->state->port);
632 }
633
sc16is7xx_handle_tx(struct uart_port * port)634 static void sc16is7xx_handle_tx(struct uart_port *port)
635 {
636 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
637 struct circ_buf *xmit = &port->state->xmit;
638 unsigned int txlen, to_send, i;
639
640 if (unlikely(port->x_char)) {
641 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
642 port->icount.tx++;
643 port->x_char = 0;
644 return;
645 }
646
647 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
648 return;
649
650 /* Get length of data pending in circular buffer */
651 to_send = uart_circ_chars_pending(xmit);
652 if (likely(to_send)) {
653 /* Limit to size of TX FIFO */
654 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
655 if (txlen > SC16IS7XX_FIFO_SIZE) {
656 dev_err_ratelimited(port->dev,
657 "chip reports %d free bytes in TX fifo, but it only has %d",
658 txlen, SC16IS7XX_FIFO_SIZE);
659 txlen = 0;
660 }
661 to_send = (to_send > txlen) ? txlen : to_send;
662
663 /* Add data to send */
664 port->icount.tx += to_send;
665
666 /* Convert to linear buffer */
667 for (i = 0; i < to_send; ++i) {
668 s->buf[i] = xmit->buf[xmit->tail];
669 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
670 }
671
672 sc16is7xx_fifo_write(port, to_send);
673 }
674
675 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
676 uart_write_wakeup(port);
677 }
678
sc16is7xx_port_irq(struct sc16is7xx_port * s,int portno)679 static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
680 {
681 struct uart_port *port = &s->p[portno].port;
682
683 do {
684 unsigned int iir, rxlen;
685
686 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
687 if (iir & SC16IS7XX_IIR_NO_INT_BIT)
688 return false;
689
690 iir &= SC16IS7XX_IIR_ID_MASK;
691
692 switch (iir) {
693 case SC16IS7XX_IIR_RDI_SRC:
694 case SC16IS7XX_IIR_RLSE_SRC:
695 case SC16IS7XX_IIR_RTOI_SRC:
696 case SC16IS7XX_IIR_XOFFI_SRC:
697 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
698
699 /*
700 * There is a silicon bug that makes the chip report a
701 * time-out interrupt but no data in the FIFO. This is
702 * described in errata section 18.1.4.
703 *
704 * When this happens, read one byte from the FIFO to
705 * clear the interrupt.
706 */
707 if (iir == SC16IS7XX_IIR_RTOI_SRC && !rxlen)
708 rxlen = 1;
709
710 if (rxlen)
711 sc16is7xx_handle_rx(port, rxlen, iir);
712 break;
713 case SC16IS7XX_IIR_THRI_SRC:
714 sc16is7xx_handle_tx(port);
715 break;
716 default:
717 dev_err_ratelimited(port->dev,
718 "ttySC%i: Unexpected interrupt: %x",
719 port->line, iir);
720 break;
721 }
722 } while (0);
723 return true;
724 }
725
sc16is7xx_irq(int irq,void * dev_id)726 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id)
727 {
728 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;
729
730 mutex_lock(&s->efr_lock);
731
732 while (1) {
733 bool keep_polling = false;
734 int i;
735
736 for (i = 0; i < s->devtype->nr_uart; ++i)
737 keep_polling |= sc16is7xx_port_irq(s, i);
738 if (!keep_polling)
739 break;
740 }
741
742 mutex_unlock(&s->efr_lock);
743
744 return IRQ_HANDLED;
745 }
746
sc16is7xx_tx_proc(struct kthread_work * ws)747 static void sc16is7xx_tx_proc(struct kthread_work *ws)
748 {
749 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port);
750 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
751
752 if ((port->rs485.flags & SER_RS485_ENABLED) &&
753 (port->rs485.delay_rts_before_send > 0))
754 msleep(port->rs485.delay_rts_before_send);
755
756 mutex_lock(&s->efr_lock);
757 sc16is7xx_handle_tx(port);
758 mutex_unlock(&s->efr_lock);
759 }
760
sc16is7xx_reconf_rs485(struct uart_port * port)761 static void sc16is7xx_reconf_rs485(struct uart_port *port)
762 {
763 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |
764 SC16IS7XX_EFCR_RTS_INVERT_BIT;
765 u32 efcr = 0;
766 struct serial_rs485 *rs485 = &port->rs485;
767 unsigned long irqflags;
768
769 spin_lock_irqsave(&port->lock, irqflags);
770 if (rs485->flags & SER_RS485_ENABLED) {
771 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT;
772
773 if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
774 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;
775 }
776 spin_unlock_irqrestore(&port->lock, irqflags);
777
778 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);
779 }
780
sc16is7xx_reg_proc(struct kthread_work * ws)781 static void sc16is7xx_reg_proc(struct kthread_work *ws)
782 {
783 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work);
784 struct sc16is7xx_one_config config;
785 unsigned long irqflags;
786
787 spin_lock_irqsave(&one->port.lock, irqflags);
788 config = one->config;
789 memset(&one->config, 0, sizeof(one->config));
790 spin_unlock_irqrestore(&one->port.lock, irqflags);
791
792 if (config.flags & SC16IS7XX_RECONF_MD) {
793 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
794 SC16IS7XX_MCR_LOOP_BIT,
795 (one->port.mctrl & TIOCM_LOOP) ?
796 SC16IS7XX_MCR_LOOP_BIT : 0);
797 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
798 SC16IS7XX_MCR_RTS_BIT,
799 (one->port.mctrl & TIOCM_RTS) ?
800 SC16IS7XX_MCR_RTS_BIT : 0);
801 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
802 SC16IS7XX_MCR_DTR_BIT,
803 (one->port.mctrl & TIOCM_DTR) ?
804 SC16IS7XX_MCR_DTR_BIT : 0);
805 }
806 if (config.flags & SC16IS7XX_RECONF_IER)
807 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG,
808 config.ier_clear, 0);
809
810 if (config.flags & SC16IS7XX_RECONF_RS485)
811 sc16is7xx_reconf_rs485(&one->port);
812 }
813
sc16is7xx_ier_clear(struct uart_port * port,u8 bit)814 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit)
815 {
816 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
817 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
818
819 one->config.flags |= SC16IS7XX_RECONF_IER;
820 one->config.ier_clear |= bit;
821 kthread_queue_work(&s->kworker, &one->reg_work);
822 }
823
sc16is7xx_stop_tx(struct uart_port * port)824 static void sc16is7xx_stop_tx(struct uart_port *port)
825 {
826 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT);
827 }
828
sc16is7xx_stop_rx(struct uart_port * port)829 static void sc16is7xx_stop_rx(struct uart_port *port)
830 {
831 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
832 }
833
sc16is7xx_start_tx(struct uart_port * port)834 static void sc16is7xx_start_tx(struct uart_port *port)
835 {
836 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
837 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
838
839 kthread_queue_work(&s->kworker, &one->tx_work);
840 }
841
sc16is7xx_tx_empty(struct uart_port * port)842 static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
843 {
844 unsigned int lsr;
845
846 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
847
848 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0;
849 }
850
sc16is7xx_get_mctrl(struct uart_port * port)851 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
852 {
853 /* DCD and DSR are not wired and CTS/RTS is handled automatically
854 * so just indicate DSR and CAR asserted
855 */
856 return TIOCM_DSR | TIOCM_CAR;
857 }
858
sc16is7xx_set_mctrl(struct uart_port * port,unsigned int mctrl)859 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
860 {
861 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
862 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
863
864 one->config.flags |= SC16IS7XX_RECONF_MD;
865 kthread_queue_work(&s->kworker, &one->reg_work);
866 }
867
sc16is7xx_break_ctl(struct uart_port * port,int break_state)868 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
869 {
870 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
871 SC16IS7XX_LCR_TXBREAK_BIT,
872 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
873 }
874
sc16is7xx_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)875 static void sc16is7xx_set_termios(struct uart_port *port,
876 struct ktermios *termios,
877 struct ktermios *old)
878 {
879 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
880 unsigned int lcr, flow = 0;
881 int baud;
882
883 /* Mask termios capabilities we don't support */
884 termios->c_cflag &= ~CMSPAR;
885
886 /* Word size */
887 switch (termios->c_cflag & CSIZE) {
888 case CS5:
889 lcr = SC16IS7XX_LCR_WORD_LEN_5;
890 break;
891 case CS6:
892 lcr = SC16IS7XX_LCR_WORD_LEN_6;
893 break;
894 case CS7:
895 lcr = SC16IS7XX_LCR_WORD_LEN_7;
896 break;
897 case CS8:
898 lcr = SC16IS7XX_LCR_WORD_LEN_8;
899 break;
900 default:
901 lcr = SC16IS7XX_LCR_WORD_LEN_8;
902 termios->c_cflag &= ~CSIZE;
903 termios->c_cflag |= CS8;
904 break;
905 }
906
907 /* Parity */
908 if (termios->c_cflag & PARENB) {
909 lcr |= SC16IS7XX_LCR_PARITY_BIT;
910 if (!(termios->c_cflag & PARODD))
911 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
912 }
913
914 /* Stop bits */
915 if (termios->c_cflag & CSTOPB)
916 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
917
918 /* Set read status mask */
919 port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
920 if (termios->c_iflag & INPCK)
921 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
922 SC16IS7XX_LSR_FE_BIT;
923 if (termios->c_iflag & (BRKINT | PARMRK))
924 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
925
926 /* Set status ignore mask */
927 port->ignore_status_mask = 0;
928 if (termios->c_iflag & IGNBRK)
929 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
930 if (!(termios->c_cflag & CREAD))
931 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
932
933 /* As above, claim the mutex while accessing the EFR. */
934 mutex_lock(&s->efr_lock);
935
936 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
937 SC16IS7XX_LCR_CONF_MODE_B);
938
939 /* Configure flow control */
940 regcache_cache_bypass(s->regmap, true);
941 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
942 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
943 if (termios->c_cflag & CRTSCTS)
944 flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
945 SC16IS7XX_EFR_AUTORTS_BIT;
946 if (termios->c_iflag & IXON)
947 flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
948 if (termios->c_iflag & IXOFF)
949 flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
950
951 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, flow);
952 regcache_cache_bypass(s->regmap, false);
953
954 /* Update LCR register */
955 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
956
957 mutex_unlock(&s->efr_lock);
958
959 /* Get baud rate generator configuration */
960 baud = uart_get_baud_rate(port, termios, old,
961 port->uartclk / 16 / 4 / 0xffff,
962 port->uartclk / 16);
963
964 /* Setup baudrate generator */
965 baud = sc16is7xx_set_baud(port, baud);
966
967 /* Update timeout according to new baud rate */
968 uart_update_timeout(port, termios->c_cflag, baud);
969 }
970
sc16is7xx_config_rs485(struct uart_port * port,struct serial_rs485 * rs485)971 static int sc16is7xx_config_rs485(struct uart_port *port,
972 struct serial_rs485 *rs485)
973 {
974 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
975 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
976
977 if (rs485->flags & SER_RS485_ENABLED) {
978 bool rts_during_rx, rts_during_tx;
979
980 rts_during_rx = rs485->flags & SER_RS485_RTS_AFTER_SEND;
981 rts_during_tx = rs485->flags & SER_RS485_RTS_ON_SEND;
982
983 if (rts_during_rx == rts_during_tx)
984 dev_err(port->dev,
985 "unsupported RTS signalling on_send:%d after_send:%d - exactly one of RS485 RTS flags should be set\n",
986 rts_during_tx, rts_during_rx);
987
988 /*
989 * RTS signal is handled by HW, it's timing can't be influenced.
990 * However, it's sometimes useful to delay TX even without RTS
991 * control therefore we try to handle .delay_rts_before_send.
992 */
993 if (rs485->delay_rts_after_send)
994 return -EINVAL;
995 }
996
997 port->rs485 = *rs485;
998 one->config.flags |= SC16IS7XX_RECONF_RS485;
999 kthread_queue_work(&s->kworker, &one->reg_work);
1000
1001 return 0;
1002 }
1003
sc16is7xx_startup(struct uart_port * port)1004 static int sc16is7xx_startup(struct uart_port *port)
1005 {
1006 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1007 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1008 unsigned int val;
1009
1010 sc16is7xx_power(port, 1);
1011
1012 /* Reset FIFOs*/
1013 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
1014 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
1015 udelay(5);
1016 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
1017 SC16IS7XX_FCR_FIFO_BIT);
1018
1019 /* Enable EFR */
1020 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
1021 SC16IS7XX_LCR_CONF_MODE_B);
1022
1023 regcache_cache_bypass(s->regmap, true);
1024
1025 /* Enable write access to enhanced features and internal clock div */
1026 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
1027 SC16IS7XX_EFR_ENABLE_BIT);
1028
1029 /* Enable TCR/TLR */
1030 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1031 SC16IS7XX_MCR_TCRTLR_BIT,
1032 SC16IS7XX_MCR_TCRTLR_BIT);
1033
1034 /* Configure flow control levels */
1035 /* Flow control halt level 48, resume level 24 */
1036 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
1037 SC16IS7XX_TCR_RX_RESUME(24) |
1038 SC16IS7XX_TCR_RX_HALT(48));
1039
1040 regcache_cache_bypass(s->regmap, false);
1041
1042 /* Now, initialize the UART */
1043 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
1044
1045 /* Enable IrDA mode if requested in DT */
1046 /* This bit must be written with LCR[7] = 0 */
1047 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1048 SC16IS7XX_MCR_IRDA_BIT,
1049 one->irda_mode ?
1050 SC16IS7XX_MCR_IRDA_BIT : 0);
1051
1052 /* Enable the Rx and Tx FIFO */
1053 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1054 SC16IS7XX_EFCR_RXDISABLE_BIT |
1055 SC16IS7XX_EFCR_TXDISABLE_BIT,
1056 0);
1057
1058 /* Enable RX, TX interrupts */
1059 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_THRI_BIT;
1060 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
1061
1062 return 0;
1063 }
1064
sc16is7xx_shutdown(struct uart_port * port)1065 static void sc16is7xx_shutdown(struct uart_port *port)
1066 {
1067 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1068
1069 /* Disable all interrupts */
1070 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
1071 /* Disable TX/RX */
1072 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1073 SC16IS7XX_EFCR_RXDISABLE_BIT |
1074 SC16IS7XX_EFCR_TXDISABLE_BIT,
1075 SC16IS7XX_EFCR_RXDISABLE_BIT |
1076 SC16IS7XX_EFCR_TXDISABLE_BIT);
1077
1078 sc16is7xx_power(port, 0);
1079
1080 kthread_flush_worker(&s->kworker);
1081 }
1082
sc16is7xx_type(struct uart_port * port)1083 static const char *sc16is7xx_type(struct uart_port *port)
1084 {
1085 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1086
1087 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
1088 }
1089
sc16is7xx_request_port(struct uart_port * port)1090 static int sc16is7xx_request_port(struct uart_port *port)
1091 {
1092 /* Do nothing */
1093 return 0;
1094 }
1095
sc16is7xx_config_port(struct uart_port * port,int flags)1096 static void sc16is7xx_config_port(struct uart_port *port, int flags)
1097 {
1098 if (flags & UART_CONFIG_TYPE)
1099 port->type = PORT_SC16IS7XX;
1100 }
1101
sc16is7xx_verify_port(struct uart_port * port,struct serial_struct * s)1102 static int sc16is7xx_verify_port(struct uart_port *port,
1103 struct serial_struct *s)
1104 {
1105 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
1106 return -EINVAL;
1107 if (s->irq != port->irq)
1108 return -EINVAL;
1109
1110 return 0;
1111 }
1112
sc16is7xx_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)1113 static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
1114 unsigned int oldstate)
1115 {
1116 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
1117 }
1118
sc16is7xx_null_void(struct uart_port * port)1119 static void sc16is7xx_null_void(struct uart_port *port)
1120 {
1121 /* Do nothing */
1122 }
1123
1124 static const struct uart_ops sc16is7xx_ops = {
1125 .tx_empty = sc16is7xx_tx_empty,
1126 .set_mctrl = sc16is7xx_set_mctrl,
1127 .get_mctrl = sc16is7xx_get_mctrl,
1128 .stop_tx = sc16is7xx_stop_tx,
1129 .start_tx = sc16is7xx_start_tx,
1130 .stop_rx = sc16is7xx_stop_rx,
1131 .break_ctl = sc16is7xx_break_ctl,
1132 .startup = sc16is7xx_startup,
1133 .shutdown = sc16is7xx_shutdown,
1134 .set_termios = sc16is7xx_set_termios,
1135 .type = sc16is7xx_type,
1136 .request_port = sc16is7xx_request_port,
1137 .release_port = sc16is7xx_null_void,
1138 .config_port = sc16is7xx_config_port,
1139 .verify_port = sc16is7xx_verify_port,
1140 .pm = sc16is7xx_pm,
1141 };
1142
1143 #ifdef CONFIG_GPIOLIB
sc16is7xx_gpio_get(struct gpio_chip * chip,unsigned offset)1144 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
1145 {
1146 unsigned int val;
1147 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1148 struct uart_port *port = &s->p[0].port;
1149
1150 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1151
1152 return !!(val & BIT(offset));
1153 }
1154
sc16is7xx_gpio_set(struct gpio_chip * chip,unsigned offset,int val)1155 static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
1156 {
1157 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1158 struct uart_port *port = &s->p[0].port;
1159
1160 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1161 val ? BIT(offset) : 0);
1162 }
1163
sc16is7xx_gpio_direction_input(struct gpio_chip * chip,unsigned offset)1164 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1165 unsigned offset)
1166 {
1167 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1168 struct uart_port *port = &s->p[0].port;
1169
1170 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1171
1172 return 0;
1173 }
1174
sc16is7xx_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int val)1175 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1176 unsigned offset, int val)
1177 {
1178 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1179 struct uart_port *port = &s->p[0].port;
1180 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1181
1182 if (val)
1183 state |= BIT(offset);
1184 else
1185 state &= ~BIT(offset);
1186
1187 /*
1188 * If we write IOSTATE first, and then IODIR, the output value is not
1189 * transferred to the corresponding I/O pin.
1190 * The datasheet states that each register bit will be transferred to
1191 * the corresponding I/O pin programmed as output when writing to
1192 * IOSTATE. Therefore, configure direction first with IODIR, and then
1193 * set value after with IOSTATE.
1194 */
1195 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1196 BIT(offset));
1197 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state);
1198
1199 return 0;
1200 }
1201 #endif
1202
sc16is7xx_probe(struct device * dev,const struct sc16is7xx_devtype * devtype,struct regmap * regmap,int irq)1203 static int sc16is7xx_probe(struct device *dev,
1204 const struct sc16is7xx_devtype *devtype,
1205 struct regmap *regmap, int irq)
1206 {
1207 unsigned long freq = 0, *pfreq = dev_get_platdata(dev);
1208 unsigned int val;
1209 u32 uartclk = 0;
1210 int i, ret;
1211 struct sc16is7xx_port *s;
1212
1213 if (IS_ERR(regmap))
1214 return PTR_ERR(regmap);
1215
1216 /*
1217 * This device does not have an identification register that would
1218 * tell us if we are really connected to the correct device.
1219 * The best we can do is to check if communication is at all possible.
1220 */
1221 ret = regmap_read(regmap,
1222 SC16IS7XX_LSR_REG << SC16IS7XX_REG_SHIFT, &val);
1223 if (ret < 0)
1224 return -EPROBE_DEFER;
1225
1226 /* Alloc port structure */
1227 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL);
1228 if (!s) {
1229 dev_err(dev, "Error allocating port structure\n");
1230 return -ENOMEM;
1231 }
1232
1233 /* Always ask for fixed clock rate from a property. */
1234 device_property_read_u32(dev, "clock-frequency", &uartclk);
1235
1236 s->clk = devm_clk_get_optional(dev, NULL);
1237 if (IS_ERR(s->clk))
1238 return PTR_ERR(s->clk);
1239
1240 ret = clk_prepare_enable(s->clk);
1241 if (ret)
1242 return ret;
1243
1244 freq = clk_get_rate(s->clk);
1245 if (freq == 0) {
1246 if (uartclk)
1247 freq = uartclk;
1248 if (pfreq)
1249 freq = *pfreq;
1250 if (freq)
1251 dev_dbg(dev, "Clock frequency: %luHz\n", freq);
1252 else
1253 return -EINVAL;
1254 }
1255
1256 s->regmap = regmap;
1257 s->devtype = devtype;
1258 dev_set_drvdata(dev, s);
1259 mutex_init(&s->efr_lock);
1260
1261 kthread_init_worker(&s->kworker);
1262 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker,
1263 "sc16is7xx");
1264 if (IS_ERR(s->kworker_task)) {
1265 ret = PTR_ERR(s->kworker_task);
1266 goto out_clk;
1267 }
1268 sched_set_fifo(s->kworker_task);
1269
1270 /* reset device, purging any pending irq / data */
1271 regmap_write(s->regmap, SC16IS7XX_IOCONTROL_REG << SC16IS7XX_REG_SHIFT,
1272 SC16IS7XX_IOCONTROL_SRESET_BIT);
1273
1274 for (i = 0; i < devtype->nr_uart; ++i) {
1275 s->p[i].line = i;
1276 /* Initialize port data */
1277 s->p[i].port.dev = dev;
1278 s->p[i].port.irq = irq;
1279 s->p[i].port.type = PORT_SC16IS7XX;
1280 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE;
1281 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1282 s->p[i].port.iobase = i;
1283 /*
1284 * Use all ones as membase to make sure uart_configure_port() in
1285 * serial_core.c does not abort for SPI/I2C devices where the
1286 * membase address is not applicable.
1287 */
1288 s->p[i].port.membase = (void __iomem *)~0;
1289 s->p[i].port.iotype = UPIO_PORT;
1290 s->p[i].port.uartclk = freq;
1291 s->p[i].port.rs485_config = sc16is7xx_config_rs485;
1292 s->p[i].port.ops = &sc16is7xx_ops;
1293 s->p[i].port.line = sc16is7xx_alloc_line();
1294 if (s->p[i].port.line >= SC16IS7XX_MAX_DEVS) {
1295 ret = -ENOMEM;
1296 goto out_ports;
1297 }
1298
1299 /* Disable all interrupts */
1300 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);
1301 /* Disable TX/RX */
1302 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,
1303 SC16IS7XX_EFCR_RXDISABLE_BIT |
1304 SC16IS7XX_EFCR_TXDISABLE_BIT);
1305 /* Initialize kthread work structs */
1306 kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc);
1307 kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc);
1308 /* Register port */
1309 uart_add_one_port(&sc16is7xx_uart, &s->p[i].port);
1310
1311 /* Enable EFR */
1312 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG,
1313 SC16IS7XX_LCR_CONF_MODE_B);
1314
1315 regcache_cache_bypass(s->regmap, true);
1316
1317 /* Enable write access to enhanced features */
1318 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG,
1319 SC16IS7XX_EFR_ENABLE_BIT);
1320
1321 regcache_cache_bypass(s->regmap, false);
1322
1323 /* Restore access to general registers */
1324 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00);
1325
1326 /* Go to suspend mode */
1327 sc16is7xx_power(&s->p[i].port, 0);
1328 }
1329
1330 if (dev->of_node) {
1331 struct property *prop;
1332 const __be32 *p;
1333 u32 u;
1334
1335 of_property_for_each_u32(dev->of_node, "irda-mode-ports",
1336 prop, p, u)
1337 if (u < devtype->nr_uart)
1338 s->p[u].irda_mode = true;
1339 }
1340
1341 #ifdef CONFIG_GPIOLIB
1342 if (devtype->nr_gpio) {
1343 /* Setup GPIO cotroller */
1344 s->gpio.owner = THIS_MODULE;
1345 s->gpio.parent = dev;
1346 s->gpio.label = dev_name(dev);
1347 s->gpio.direction_input = sc16is7xx_gpio_direction_input;
1348 s->gpio.get = sc16is7xx_gpio_get;
1349 s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1350 s->gpio.set = sc16is7xx_gpio_set;
1351 s->gpio.base = -1;
1352 s->gpio.ngpio = devtype->nr_gpio;
1353 s->gpio.can_sleep = 1;
1354 ret = gpiochip_add_data(&s->gpio, s);
1355 if (ret)
1356 goto out_thread;
1357 }
1358 #endif
1359
1360 /*
1361 * Setup interrupt. We first try to acquire the IRQ line as level IRQ.
1362 * If that succeeds, we can allow sharing the interrupt as well.
1363 * In case the interrupt controller doesn't support that, we fall
1364 * back to a non-shared falling-edge trigger.
1365 */
1366 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1367 IRQF_TRIGGER_LOW | IRQF_SHARED |
1368 IRQF_ONESHOT,
1369 dev_name(dev), s);
1370 if (!ret)
1371 return 0;
1372
1373 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1374 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1375 dev_name(dev), s);
1376 if (!ret)
1377 return 0;
1378
1379 #ifdef CONFIG_GPIOLIB
1380 if (devtype->nr_gpio)
1381 gpiochip_remove(&s->gpio);
1382
1383 out_thread:
1384 #endif
1385
1386 out_ports:
1387 for (i--; i >= 0; i--) {
1388 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1389 clear_bit(s->p[i].port.line, &sc16is7xx_lines);
1390 }
1391
1392 kthread_stop(s->kworker_task);
1393
1394 out_clk:
1395 clk_disable_unprepare(s->clk);
1396
1397 return ret;
1398 }
1399
sc16is7xx_remove(struct device * dev)1400 static int sc16is7xx_remove(struct device *dev)
1401 {
1402 struct sc16is7xx_port *s = dev_get_drvdata(dev);
1403 int i;
1404
1405 #ifdef CONFIG_GPIOLIB
1406 if (s->devtype->nr_gpio)
1407 gpiochip_remove(&s->gpio);
1408 #endif
1409
1410 for (i = 0; i < s->devtype->nr_uart; i++) {
1411 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1412 clear_bit(s->p[i].port.line, &sc16is7xx_lines);
1413 sc16is7xx_power(&s->p[i].port, 0);
1414 }
1415
1416 kthread_flush_worker(&s->kworker);
1417 kthread_stop(s->kworker_task);
1418
1419 clk_disable_unprepare(s->clk);
1420
1421 return 0;
1422 }
1423
1424 static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1425 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, },
1426 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, },
1427 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, },
1428 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, },
1429 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, },
1430 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, },
1431 { }
1432 };
1433 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1434
1435 static struct regmap_config regcfg = {
1436 .reg_bits = 7,
1437 .pad_bits = 1,
1438 .val_bits = 8,
1439 .cache_type = REGCACHE_RBTREE,
1440 .volatile_reg = sc16is7xx_regmap_volatile,
1441 .precious_reg = sc16is7xx_regmap_precious,
1442 };
1443
1444 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
sc16is7xx_spi_probe(struct spi_device * spi)1445 static int sc16is7xx_spi_probe(struct spi_device *spi)
1446 {
1447 const struct sc16is7xx_devtype *devtype;
1448 struct regmap *regmap;
1449 int ret;
1450
1451 /* Setup SPI bus */
1452 spi->bits_per_word = 8;
1453 /* For all variants, only mode 0 is supported */
1454 if ((spi->mode & SPI_MODE_X_MASK) != SPI_MODE_0)
1455 return dev_err_probe(&spi->dev, -EINVAL, "Unsupported SPI mode\n");
1456
1457 spi->mode = spi->mode ? : SPI_MODE_0;
1458 spi->max_speed_hz = spi->max_speed_hz ? : 4 * HZ_PER_MHZ;
1459 ret = spi_setup(spi);
1460 if (ret)
1461 return ret;
1462
1463 if (spi->dev.of_node) {
1464 devtype = device_get_match_data(&spi->dev);
1465 if (!devtype)
1466 return -ENODEV;
1467 } else {
1468 const struct spi_device_id *id_entry = spi_get_device_id(spi);
1469
1470 devtype = (struct sc16is7xx_devtype *)id_entry->driver_data;
1471 }
1472
1473 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1474 (devtype->nr_uart - 1);
1475 regmap = devm_regmap_init_spi(spi, ®cfg);
1476
1477 return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq);
1478 }
1479
sc16is7xx_spi_remove(struct spi_device * spi)1480 static int sc16is7xx_spi_remove(struct spi_device *spi)
1481 {
1482 return sc16is7xx_remove(&spi->dev);
1483 }
1484
1485 static const struct spi_device_id sc16is7xx_spi_id_table[] = {
1486 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
1487 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1488 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
1489 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1490 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1491 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1492 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1493 { }
1494 };
1495
1496 MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table);
1497
1498 static struct spi_driver sc16is7xx_spi_uart_driver = {
1499 .driver = {
1500 .name = SC16IS7XX_NAME,
1501 .of_match_table = sc16is7xx_dt_ids,
1502 },
1503 .probe = sc16is7xx_spi_probe,
1504 .remove = sc16is7xx_spi_remove,
1505 .id_table = sc16is7xx_spi_id_table,
1506 };
1507
1508 MODULE_ALIAS("spi:sc16is7xx");
1509 #endif
1510
1511 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
sc16is7xx_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)1512 static int sc16is7xx_i2c_probe(struct i2c_client *i2c,
1513 const struct i2c_device_id *id)
1514 {
1515 const struct sc16is7xx_devtype *devtype;
1516 struct regmap *regmap;
1517
1518 if (i2c->dev.of_node) {
1519 devtype = device_get_match_data(&i2c->dev);
1520 if (!devtype)
1521 return -ENODEV;
1522 } else {
1523 devtype = (struct sc16is7xx_devtype *)id->driver_data;
1524 }
1525
1526 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1527 (devtype->nr_uart - 1);
1528 regmap = devm_regmap_init_i2c(i2c, ®cfg);
1529
1530 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq);
1531 }
1532
sc16is7xx_i2c_remove(struct i2c_client * client)1533 static int sc16is7xx_i2c_remove(struct i2c_client *client)
1534 {
1535 return sc16is7xx_remove(&client->dev);
1536 }
1537
1538 static const struct i2c_device_id sc16is7xx_i2c_id_table[] = {
1539 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
1540 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1541 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
1542 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1543 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1544 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1545 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1546 { }
1547 };
1548 MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table);
1549
1550 static struct i2c_driver sc16is7xx_i2c_uart_driver = {
1551 .driver = {
1552 .name = SC16IS7XX_NAME,
1553 .of_match_table = sc16is7xx_dt_ids,
1554 },
1555 .probe = sc16is7xx_i2c_probe,
1556 .remove = sc16is7xx_i2c_remove,
1557 .id_table = sc16is7xx_i2c_id_table,
1558 };
1559
1560 #endif
1561
sc16is7xx_init(void)1562 static int __init sc16is7xx_init(void)
1563 {
1564 int ret;
1565
1566 ret = uart_register_driver(&sc16is7xx_uart);
1567 if (ret) {
1568 pr_err("Registering UART driver failed\n");
1569 return ret;
1570 }
1571
1572 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1573 ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver);
1574 if (ret < 0) {
1575 pr_err("failed to init sc16is7xx i2c --> %d\n", ret);
1576 goto err_i2c;
1577 }
1578 #endif
1579
1580 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1581 ret = spi_register_driver(&sc16is7xx_spi_uart_driver);
1582 if (ret < 0) {
1583 pr_err("failed to init sc16is7xx spi --> %d\n", ret);
1584 goto err_spi;
1585 }
1586 #endif
1587 return ret;
1588
1589 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1590 err_spi:
1591 #endif
1592 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1593 i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1594 err_i2c:
1595 #endif
1596 uart_unregister_driver(&sc16is7xx_uart);
1597 return ret;
1598 }
1599 module_init(sc16is7xx_init);
1600
sc16is7xx_exit(void)1601 static void __exit sc16is7xx_exit(void)
1602 {
1603 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1604 i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1605 #endif
1606
1607 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1608 spi_unregister_driver(&sc16is7xx_spi_uart_driver);
1609 #endif
1610 uart_unregister_driver(&sc16is7xx_uart);
1611 }
1612 module_exit(sc16is7xx_exit);
1613
1614 MODULE_LICENSE("GPL");
1615 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1616 MODULE_DESCRIPTION("SC16IS7XX serial driver");
1617