1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * core.c - ChipIdea USB IP core family device controller
4 *
5 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
6 * Copyright (C) 2020 NXP
7 *
8 * Author: David Lopo
9 * Peter Chen <peter.chen@nxp.com>
10 *
11 * Main Features:
12 * - Four transfers are supported, usbtest is passed
13 * - USB Certification for gadget: CH9 and Mass Storage are passed
14 * - Low power mode
15 * - USB wakeup
16 */
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/extcon.h>
21 #include <linux/phy/phy.h>
22 #include <linux/platform_device.h>
23 #include <linux/module.h>
24 #include <linux/idr.h>
25 #include <linux/interrupt.h>
26 #include <linux/io.h>
27 #include <linux/kernel.h>
28 #include <linux/slab.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pinctrl/consumer.h>
31 #include <linux/usb/ch9.h>
32 #include <linux/usb/gadget.h>
33 #include <linux/usb/otg.h>
34 #include <linux/usb/chipidea.h>
35 #include <linux/usb/of.h>
36 #include <linux/of.h>
37 #include <linux/regulator/consumer.h>
38 #include <linux/usb/ehci_def.h>
39
40 #include "ci.h"
41 #include "udc.h"
42 #include "bits.h"
43 #include "host.h"
44 #include "otg.h"
45 #include "otg_fsm.h"
46
47 /* Controller register map */
48 static const u8 ci_regs_nolpm[] = {
49 [CAP_CAPLENGTH] = 0x00U,
50 [CAP_HCCPARAMS] = 0x08U,
51 [CAP_DCCPARAMS] = 0x24U,
52 [CAP_TESTMODE] = 0x38U,
53 [OP_USBCMD] = 0x00U,
54 [OP_USBSTS] = 0x04U,
55 [OP_USBINTR] = 0x08U,
56 [OP_DEVICEADDR] = 0x14U,
57 [OP_ENDPTLISTADDR] = 0x18U,
58 [OP_TTCTRL] = 0x1CU,
59 [OP_BURSTSIZE] = 0x20U,
60 [OP_ULPI_VIEWPORT] = 0x30U,
61 [OP_PORTSC] = 0x44U,
62 [OP_DEVLC] = 0x84U,
63 [OP_OTGSC] = 0x64U,
64 [OP_USBMODE] = 0x68U,
65 [OP_ENDPTSETUPSTAT] = 0x6CU,
66 [OP_ENDPTPRIME] = 0x70U,
67 [OP_ENDPTFLUSH] = 0x74U,
68 [OP_ENDPTSTAT] = 0x78U,
69 [OP_ENDPTCOMPLETE] = 0x7CU,
70 [OP_ENDPTCTRL] = 0x80U,
71 };
72
73 static const u8 ci_regs_lpm[] = {
74 [CAP_CAPLENGTH] = 0x00U,
75 [CAP_HCCPARAMS] = 0x08U,
76 [CAP_DCCPARAMS] = 0x24U,
77 [CAP_TESTMODE] = 0xFCU,
78 [OP_USBCMD] = 0x00U,
79 [OP_USBSTS] = 0x04U,
80 [OP_USBINTR] = 0x08U,
81 [OP_DEVICEADDR] = 0x14U,
82 [OP_ENDPTLISTADDR] = 0x18U,
83 [OP_TTCTRL] = 0x1CU,
84 [OP_BURSTSIZE] = 0x20U,
85 [OP_ULPI_VIEWPORT] = 0x30U,
86 [OP_PORTSC] = 0x44U,
87 [OP_DEVLC] = 0x84U,
88 [OP_OTGSC] = 0xC4U,
89 [OP_USBMODE] = 0xC8U,
90 [OP_ENDPTSETUPSTAT] = 0xD8U,
91 [OP_ENDPTPRIME] = 0xDCU,
92 [OP_ENDPTFLUSH] = 0xE0U,
93 [OP_ENDPTSTAT] = 0xE4U,
94 [OP_ENDPTCOMPLETE] = 0xE8U,
95 [OP_ENDPTCTRL] = 0xECU,
96 };
97
hw_alloc_regmap(struct ci_hdrc * ci,bool is_lpm)98 static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
99 {
100 int i;
101
102 for (i = 0; i < OP_ENDPTCTRL; i++)
103 ci->hw_bank.regmap[i] =
104 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
105 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
106
107 for (; i <= OP_LAST; i++)
108 ci->hw_bank.regmap[i] = ci->hw_bank.op +
109 4 * (i - OP_ENDPTCTRL) +
110 (is_lpm
111 ? ci_regs_lpm[OP_ENDPTCTRL]
112 : ci_regs_nolpm[OP_ENDPTCTRL]);
113
114 }
115
ci_get_revision(struct ci_hdrc * ci)116 static enum ci_revision ci_get_revision(struct ci_hdrc *ci)
117 {
118 int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION);
119 enum ci_revision rev = CI_REVISION_UNKNOWN;
120
121 if (ver == 0x2) {
122 rev = hw_read_id_reg(ci, ID_ID, REVISION)
123 >> __ffs(REVISION);
124 rev += CI_REVISION_20;
125 } else if (ver == 0x0) {
126 rev = CI_REVISION_1X;
127 }
128
129 return rev;
130 }
131
132 /**
133 * hw_read_intr_enable: returns interrupt enable register
134 *
135 * @ci: the controller
136 *
137 * This function returns register data
138 */
hw_read_intr_enable(struct ci_hdrc * ci)139 u32 hw_read_intr_enable(struct ci_hdrc *ci)
140 {
141 return hw_read(ci, OP_USBINTR, ~0);
142 }
143
144 /**
145 * hw_read_intr_status: returns interrupt status register
146 *
147 * @ci: the controller
148 *
149 * This function returns register data
150 */
hw_read_intr_status(struct ci_hdrc * ci)151 u32 hw_read_intr_status(struct ci_hdrc *ci)
152 {
153 return hw_read(ci, OP_USBSTS, ~0);
154 }
155
156 /**
157 * hw_port_test_set: writes port test mode (execute without interruption)
158 * @ci: the controller
159 * @mode: new value
160 *
161 * This function returns an error code
162 */
hw_port_test_set(struct ci_hdrc * ci,u8 mode)163 int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
164 {
165 const u8 TEST_MODE_MAX = 7;
166
167 if (mode > TEST_MODE_MAX)
168 return -EINVAL;
169
170 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
171 return 0;
172 }
173
174 /**
175 * hw_port_test_get: reads port test mode value
176 *
177 * @ci: the controller
178 *
179 * This function returns port test mode value
180 */
hw_port_test_get(struct ci_hdrc * ci)181 u8 hw_port_test_get(struct ci_hdrc *ci)
182 {
183 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
184 }
185
hw_wait_phy_stable(void)186 static void hw_wait_phy_stable(void)
187 {
188 /*
189 * The phy needs some delay to output the stable status from low
190 * power mode. And for OTGSC, the status inputs are debounced
191 * using a 1 ms time constant, so, delay 2ms for controller to get
192 * the stable status, like vbus and id when the phy leaves low power.
193 */
194 usleep_range(2000, 2500);
195 }
196
197 /* The PHY enters/leaves low power mode */
ci_hdrc_enter_lpm_common(struct ci_hdrc * ci,bool enable)198 static void ci_hdrc_enter_lpm_common(struct ci_hdrc *ci, bool enable)
199 {
200 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
201 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
202
203 if (enable && !lpm)
204 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
205 PORTSC_PHCD(ci->hw_bank.lpm));
206 else if (!enable && lpm)
207 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
208 0);
209 }
210
ci_hdrc_enter_lpm(struct ci_hdrc * ci,bool enable)211 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
212 {
213 return ci->platdata->enter_lpm(ci, enable);
214 }
215
hw_device_init(struct ci_hdrc * ci,void __iomem * base)216 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
217 {
218 u32 reg;
219
220 /* bank is a module variable */
221 ci->hw_bank.abs = base;
222
223 ci->hw_bank.cap = ci->hw_bank.abs;
224 ci->hw_bank.cap += ci->platdata->capoffset;
225 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
226
227 hw_alloc_regmap(ci, false);
228 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
229 __ffs(HCCPARAMS_LEN);
230 ci->hw_bank.lpm = reg;
231 if (reg)
232 hw_alloc_regmap(ci, !!reg);
233 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
234 ci->hw_bank.size += OP_LAST;
235 ci->hw_bank.size /= sizeof(u32);
236
237 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
238 __ffs(DCCPARAMS_DEN);
239 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
240
241 if (ci->hw_ep_max > ENDPT_MAX)
242 return -ENODEV;
243
244 ci_hdrc_enter_lpm(ci, false);
245
246 /* Disable all interrupts bits */
247 hw_write(ci, OP_USBINTR, 0xffffffff, 0);
248
249 /* Clear all interrupts status bits*/
250 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
251
252 ci->rev = ci_get_revision(ci);
253
254 dev_dbg(ci->dev,
255 "revision: %d, lpm: %d; cap: %px op: %px\n",
256 ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
257
258 /* setup lock mode ? */
259
260 /* ENDPTSETUPSTAT is '0' by default */
261
262 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
263
264 return 0;
265 }
266
hw_phymode_configure(struct ci_hdrc * ci)267 void hw_phymode_configure(struct ci_hdrc *ci)
268 {
269 u32 portsc, lpm, sts = 0;
270
271 switch (ci->platdata->phy_mode) {
272 case USBPHY_INTERFACE_MODE_UTMI:
273 portsc = PORTSC_PTS(PTS_UTMI);
274 lpm = DEVLC_PTS(PTS_UTMI);
275 break;
276 case USBPHY_INTERFACE_MODE_UTMIW:
277 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
278 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
279 break;
280 case USBPHY_INTERFACE_MODE_ULPI:
281 portsc = PORTSC_PTS(PTS_ULPI);
282 lpm = DEVLC_PTS(PTS_ULPI);
283 break;
284 case USBPHY_INTERFACE_MODE_SERIAL:
285 portsc = PORTSC_PTS(PTS_SERIAL);
286 lpm = DEVLC_PTS(PTS_SERIAL);
287 sts = 1;
288 break;
289 case USBPHY_INTERFACE_MODE_HSIC:
290 portsc = PORTSC_PTS(PTS_HSIC);
291 lpm = DEVLC_PTS(PTS_HSIC);
292 break;
293 default:
294 return;
295 }
296
297 if (ci->hw_bank.lpm) {
298 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
299 if (sts)
300 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
301 } else {
302 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
303 if (sts)
304 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
305 }
306 }
307 EXPORT_SYMBOL_GPL(hw_phymode_configure);
308
309 /**
310 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
311 * interfaces
312 * @ci: the controller
313 *
314 * This function returns an error code if the phy failed to init
315 */
_ci_usb_phy_init(struct ci_hdrc * ci)316 static int _ci_usb_phy_init(struct ci_hdrc *ci)
317 {
318 int ret;
319
320 if (ci->phy) {
321 ret = phy_init(ci->phy);
322 if (ret)
323 return ret;
324
325 ret = phy_power_on(ci->phy);
326 if (ret) {
327 phy_exit(ci->phy);
328 return ret;
329 }
330 } else {
331 ret = usb_phy_init(ci->usb_phy);
332 }
333
334 return ret;
335 }
336
337 /**
338 * ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
339 * interfaces
340 * @ci: the controller
341 */
ci_usb_phy_exit(struct ci_hdrc * ci)342 static void ci_usb_phy_exit(struct ci_hdrc *ci)
343 {
344 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
345 return;
346
347 if (ci->phy) {
348 phy_power_off(ci->phy);
349 phy_exit(ci->phy);
350 } else {
351 usb_phy_shutdown(ci->usb_phy);
352 }
353 }
354
355 /**
356 * ci_usb_phy_init: initialize phy according to different phy type
357 * @ci: the controller
358 *
359 * This function returns an error code if usb_phy_init has failed
360 */
ci_usb_phy_init(struct ci_hdrc * ci)361 static int ci_usb_phy_init(struct ci_hdrc *ci)
362 {
363 int ret;
364
365 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
366 return 0;
367
368 switch (ci->platdata->phy_mode) {
369 case USBPHY_INTERFACE_MODE_UTMI:
370 case USBPHY_INTERFACE_MODE_UTMIW:
371 case USBPHY_INTERFACE_MODE_HSIC:
372 ret = _ci_usb_phy_init(ci);
373 if (!ret)
374 hw_wait_phy_stable();
375 else
376 return ret;
377 hw_phymode_configure(ci);
378 break;
379 case USBPHY_INTERFACE_MODE_ULPI:
380 case USBPHY_INTERFACE_MODE_SERIAL:
381 hw_phymode_configure(ci);
382 ret = _ci_usb_phy_init(ci);
383 if (ret)
384 return ret;
385 break;
386 default:
387 ret = _ci_usb_phy_init(ci);
388 if (!ret)
389 hw_wait_phy_stable();
390 }
391
392 return ret;
393 }
394
395
396 /**
397 * ci_platform_configure: do controller configure
398 * @ci: the controller
399 *
400 */
ci_platform_configure(struct ci_hdrc * ci)401 void ci_platform_configure(struct ci_hdrc *ci)
402 {
403 bool is_device_mode, is_host_mode;
404
405 is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC;
406 is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC;
407
408 if (is_device_mode) {
409 phy_set_mode(ci->phy, PHY_MODE_USB_DEVICE);
410
411 if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)
412 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
413 USBMODE_CI_SDIS);
414 }
415
416 if (is_host_mode) {
417 phy_set_mode(ci->phy, PHY_MODE_USB_HOST);
418
419 if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)
420 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
421 USBMODE_CI_SDIS);
422 }
423
424 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
425 if (ci->hw_bank.lpm)
426 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
427 else
428 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
429 }
430
431 if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA)
432 hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA);
433
434 hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16);
435
436 if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST)
437 hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
438 ci->platdata->ahb_burst_config);
439
440 /* override burst size, take effect only when ahb_burst_config is 0 */
441 if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) {
442 if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST)
443 hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK,
444 ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK));
445
446 if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST)
447 hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK,
448 ci->platdata->rx_burst_size);
449 }
450 }
451
452 /**
453 * hw_controller_reset: do controller reset
454 * @ci: the controller
455 *
456 * This function returns an error code
457 */
hw_controller_reset(struct ci_hdrc * ci)458 static int hw_controller_reset(struct ci_hdrc *ci)
459 {
460 int count = 0;
461
462 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
463 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) {
464 udelay(10);
465 if (count++ > 1000)
466 return -ETIMEDOUT;
467 }
468
469 return 0;
470 }
471
472 /**
473 * hw_device_reset: resets chip (execute without interruption)
474 * @ci: the controller
475 *
476 * This function returns an error code
477 */
hw_device_reset(struct ci_hdrc * ci)478 int hw_device_reset(struct ci_hdrc *ci)
479 {
480 int ret;
481
482 /* should flush & stop before reset */
483 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
484 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
485
486 ret = hw_controller_reset(ci);
487 if (ret) {
488 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret);
489 return ret;
490 }
491
492 if (ci->platdata->notify_event) {
493 ret = ci->platdata->notify_event(ci,
494 CI_HDRC_CONTROLLER_RESET_EVENT);
495 if (ret)
496 return ret;
497 }
498
499 /* USBMODE should be configured step by step */
500 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
501 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
502 /* HW >= 2.3 */
503 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
504
505 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
506 dev_err(ci->dev, "cannot enter in %s device mode\n",
507 ci_role(ci)->name);
508 dev_err(ci->dev, "lpm = %i\n", ci->hw_bank.lpm);
509 return -ENODEV;
510 }
511
512 ci_platform_configure(ci);
513
514 return 0;
515 }
516
ci_irq_handler(int irq,void * data)517 static irqreturn_t ci_irq_handler(int irq, void *data)
518 {
519 struct ci_hdrc *ci = data;
520 irqreturn_t ret = IRQ_NONE;
521 u32 otgsc = 0;
522
523 if (ci->in_lpm) {
524 /*
525 * If we already have a wakeup irq pending there,
526 * let's just return to wait resume finished firstly.
527 */
528 if (ci->wakeup_int)
529 return IRQ_HANDLED;
530
531 disable_irq_nosync(irq);
532 ci->wakeup_int = true;
533 pm_runtime_get(ci->dev);
534 return IRQ_HANDLED;
535 }
536
537 if (ci->is_otg) {
538 otgsc = hw_read_otgsc(ci, ~0);
539 if (ci_otg_is_fsm_mode(ci)) {
540 ret = ci_otg_fsm_irq(ci);
541 if (ret == IRQ_HANDLED)
542 return ret;
543 }
544 }
545
546 /*
547 * Handle id change interrupt, it indicates device/host function
548 * switch.
549 */
550 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
551 ci->id_event = true;
552 /* Clear ID change irq status */
553 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
554 ci_otg_queue_work(ci);
555 return IRQ_HANDLED;
556 }
557
558 /*
559 * Handle vbus change interrupt, it indicates device connection
560 * and disconnection events.
561 */
562 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
563 ci->b_sess_valid_event = true;
564 /* Clear BSV irq */
565 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
566 ci_otg_queue_work(ci);
567 return IRQ_HANDLED;
568 }
569
570 /* Handle device/host interrupt */
571 if (ci->role != CI_ROLE_END)
572 ret = ci_role(ci)->irq(ci);
573
574 return ret;
575 }
576
ci_irq(struct ci_hdrc * ci)577 static void ci_irq(struct ci_hdrc *ci)
578 {
579 unsigned long flags;
580
581 local_irq_save(flags);
582 ci_irq_handler(ci->irq, ci);
583 local_irq_restore(flags);
584 }
585
ci_cable_notifier(struct notifier_block * nb,unsigned long event,void * ptr)586 static int ci_cable_notifier(struct notifier_block *nb, unsigned long event,
587 void *ptr)
588 {
589 struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb);
590 struct ci_hdrc *ci = cbl->ci;
591
592 cbl->connected = event;
593 cbl->changed = true;
594
595 ci_irq(ci);
596 return NOTIFY_DONE;
597 }
598
ci_usb_role_switch_get(struct usb_role_switch * sw)599 static enum usb_role ci_usb_role_switch_get(struct usb_role_switch *sw)
600 {
601 struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw);
602 enum usb_role role;
603 unsigned long flags;
604
605 spin_lock_irqsave(&ci->lock, flags);
606 role = ci_role_to_usb_role(ci);
607 spin_unlock_irqrestore(&ci->lock, flags);
608
609 return role;
610 }
611
ci_usb_role_switch_set(struct usb_role_switch * sw,enum usb_role role)612 static int ci_usb_role_switch_set(struct usb_role_switch *sw,
613 enum usb_role role)
614 {
615 struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw);
616 struct ci_hdrc_cable *cable = NULL;
617 enum usb_role current_role = ci_role_to_usb_role(ci);
618 enum ci_role ci_role = usb_role_to_ci_role(role);
619 unsigned long flags;
620
621 if ((ci_role != CI_ROLE_END && !ci->roles[ci_role]) ||
622 (current_role == role))
623 return 0;
624
625 pm_runtime_get_sync(ci->dev);
626 /* Stop current role */
627 spin_lock_irqsave(&ci->lock, flags);
628 if (current_role == USB_ROLE_DEVICE)
629 cable = &ci->platdata->vbus_extcon;
630 else if (current_role == USB_ROLE_HOST)
631 cable = &ci->platdata->id_extcon;
632
633 if (cable) {
634 cable->changed = true;
635 cable->connected = false;
636 ci_irq(ci);
637 spin_unlock_irqrestore(&ci->lock, flags);
638 if (ci->wq && role != USB_ROLE_NONE)
639 flush_workqueue(ci->wq);
640 spin_lock_irqsave(&ci->lock, flags);
641 }
642
643 cable = NULL;
644
645 /* Start target role */
646 if (role == USB_ROLE_DEVICE)
647 cable = &ci->platdata->vbus_extcon;
648 else if (role == USB_ROLE_HOST)
649 cable = &ci->platdata->id_extcon;
650
651 if (cable) {
652 cable->changed = true;
653 cable->connected = true;
654 ci_irq(ci);
655 }
656 spin_unlock_irqrestore(&ci->lock, flags);
657 pm_runtime_put_sync(ci->dev);
658
659 return 0;
660 }
661
662 static struct usb_role_switch_desc ci_role_switch = {
663 .set = ci_usb_role_switch_set,
664 .get = ci_usb_role_switch_get,
665 .allow_userspace_control = true,
666 };
667
ci_get_platdata(struct device * dev,struct ci_hdrc_platform_data * platdata)668 static int ci_get_platdata(struct device *dev,
669 struct ci_hdrc_platform_data *platdata)
670 {
671 struct extcon_dev *ext_vbus, *ext_id;
672 struct ci_hdrc_cable *cable;
673 int ret;
674
675 if (!platdata->phy_mode)
676 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
677
678 if (!platdata->dr_mode)
679 platdata->dr_mode = usb_get_dr_mode(dev);
680
681 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
682 platdata->dr_mode = USB_DR_MODE_OTG;
683
684 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
685 /* Get the vbus regulator */
686 platdata->reg_vbus = devm_regulator_get_optional(dev, "vbus");
687 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
688 return -EPROBE_DEFER;
689 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
690 /* no vbus regulator is needed */
691 platdata->reg_vbus = NULL;
692 } else if (IS_ERR(platdata->reg_vbus)) {
693 dev_err(dev, "Getting regulator error: %ld\n",
694 PTR_ERR(platdata->reg_vbus));
695 return PTR_ERR(platdata->reg_vbus);
696 }
697 /* Get TPL support */
698 if (!platdata->tpl_support)
699 platdata->tpl_support =
700 of_usb_host_tpl_support(dev->of_node);
701 }
702
703 if (platdata->dr_mode == USB_DR_MODE_OTG) {
704 /* We can support HNP and SRP of OTG 2.0 */
705 platdata->ci_otg_caps.otg_rev = 0x0200;
706 platdata->ci_otg_caps.hnp_support = true;
707 platdata->ci_otg_caps.srp_support = true;
708
709 /* Update otg capabilities by DT properties */
710 ret = of_usb_update_otg_caps(dev->of_node,
711 &platdata->ci_otg_caps);
712 if (ret)
713 return ret;
714 }
715
716 if (usb_get_maximum_speed(dev) == USB_SPEED_FULL)
717 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
718
719 of_property_read_u32(dev->of_node, "phy-clkgate-delay-us",
720 &platdata->phy_clkgate_delay_us);
721
722 platdata->itc_setting = 1;
723
724 of_property_read_u32(dev->of_node, "itc-setting",
725 &platdata->itc_setting);
726
727 ret = of_property_read_u32(dev->of_node, "ahb-burst-config",
728 &platdata->ahb_burst_config);
729 if (!ret) {
730 platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST;
731 } else if (ret != -EINVAL) {
732 dev_err(dev, "failed to get ahb-burst-config\n");
733 return ret;
734 }
735
736 ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword",
737 &platdata->tx_burst_size);
738 if (!ret) {
739 platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST;
740 } else if (ret != -EINVAL) {
741 dev_err(dev, "failed to get tx-burst-size-dword\n");
742 return ret;
743 }
744
745 ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword",
746 &platdata->rx_burst_size);
747 if (!ret) {
748 platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST;
749 } else if (ret != -EINVAL) {
750 dev_err(dev, "failed to get rx-burst-size-dword\n");
751 return ret;
752 }
753
754 if (of_find_property(dev->of_node, "non-zero-ttctrl-ttha", NULL))
755 platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA;
756
757 ext_id = ERR_PTR(-ENODEV);
758 ext_vbus = ERR_PTR(-ENODEV);
759 if (of_property_read_bool(dev->of_node, "extcon")) {
760 /* Each one of them is not mandatory */
761 ext_vbus = extcon_get_edev_by_phandle(dev, 0);
762 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
763 return PTR_ERR(ext_vbus);
764
765 ext_id = extcon_get_edev_by_phandle(dev, 1);
766 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
767 return PTR_ERR(ext_id);
768 }
769
770 cable = &platdata->vbus_extcon;
771 cable->nb.notifier_call = ci_cable_notifier;
772 cable->edev = ext_vbus;
773
774 if (!IS_ERR(ext_vbus)) {
775 ret = extcon_get_state(cable->edev, EXTCON_USB);
776 if (ret)
777 cable->connected = true;
778 else
779 cable->connected = false;
780 }
781
782 cable = &platdata->id_extcon;
783 cable->nb.notifier_call = ci_cable_notifier;
784 cable->edev = ext_id;
785
786 if (!IS_ERR(ext_id)) {
787 ret = extcon_get_state(cable->edev, EXTCON_USB_HOST);
788 if (ret)
789 cable->connected = true;
790 else
791 cable->connected = false;
792 }
793
794 if (device_property_read_bool(dev, "usb-role-switch"))
795 ci_role_switch.fwnode = dev->fwnode;
796
797 platdata->pctl = devm_pinctrl_get(dev);
798 if (!IS_ERR(platdata->pctl)) {
799 struct pinctrl_state *p;
800
801 p = pinctrl_lookup_state(platdata->pctl, "default");
802 if (!IS_ERR(p))
803 platdata->pins_default = p;
804
805 p = pinctrl_lookup_state(platdata->pctl, "host");
806 if (!IS_ERR(p))
807 platdata->pins_host = p;
808
809 p = pinctrl_lookup_state(platdata->pctl, "device");
810 if (!IS_ERR(p))
811 platdata->pins_device = p;
812 }
813
814 if (!platdata->enter_lpm)
815 platdata->enter_lpm = ci_hdrc_enter_lpm_common;
816
817 return 0;
818 }
819
ci_extcon_register(struct ci_hdrc * ci)820 static int ci_extcon_register(struct ci_hdrc *ci)
821 {
822 struct ci_hdrc_cable *id, *vbus;
823 int ret;
824
825 id = &ci->platdata->id_extcon;
826 id->ci = ci;
827 if (!IS_ERR_OR_NULL(id->edev)) {
828 ret = devm_extcon_register_notifier(ci->dev, id->edev,
829 EXTCON_USB_HOST, &id->nb);
830 if (ret < 0) {
831 dev_err(ci->dev, "register ID failed\n");
832 return ret;
833 }
834 }
835
836 vbus = &ci->platdata->vbus_extcon;
837 vbus->ci = ci;
838 if (!IS_ERR_OR_NULL(vbus->edev)) {
839 ret = devm_extcon_register_notifier(ci->dev, vbus->edev,
840 EXTCON_USB, &vbus->nb);
841 if (ret < 0) {
842 dev_err(ci->dev, "register VBUS failed\n");
843 return ret;
844 }
845 }
846
847 return 0;
848 }
849
850 static DEFINE_IDA(ci_ida);
851
ci_hdrc_add_device(struct device * dev,struct resource * res,int nres,struct ci_hdrc_platform_data * platdata)852 struct platform_device *ci_hdrc_add_device(struct device *dev,
853 struct resource *res, int nres,
854 struct ci_hdrc_platform_data *platdata)
855 {
856 struct platform_device *pdev;
857 int id, ret;
858
859 ret = ci_get_platdata(dev, platdata);
860 if (ret)
861 return ERR_PTR(ret);
862
863 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
864 if (id < 0)
865 return ERR_PTR(id);
866
867 pdev = platform_device_alloc("ci_hdrc", id);
868 if (!pdev) {
869 ret = -ENOMEM;
870 goto put_id;
871 }
872
873 pdev->dev.parent = dev;
874
875 ret = platform_device_add_resources(pdev, res, nres);
876 if (ret)
877 goto err;
878
879 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
880 if (ret)
881 goto err;
882
883 ret = platform_device_add(pdev);
884 if (ret)
885 goto err;
886
887 return pdev;
888
889 err:
890 platform_device_put(pdev);
891 put_id:
892 ida_simple_remove(&ci_ida, id);
893 return ERR_PTR(ret);
894 }
895 EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
896
ci_hdrc_remove_device(struct platform_device * pdev)897 void ci_hdrc_remove_device(struct platform_device *pdev)
898 {
899 int id = pdev->id;
900 platform_device_unregister(pdev);
901 ida_simple_remove(&ci_ida, id);
902 }
903 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
904
905 /**
906 * ci_hdrc_query_available_role: get runtime available operation mode
907 *
908 * The glue layer can get current operation mode (host/peripheral/otg)
909 * This function should be called after ci core device has created.
910 *
911 * @pdev: the platform device of ci core.
912 *
913 * Return runtime usb_dr_mode.
914 */
ci_hdrc_query_available_role(struct platform_device * pdev)915 enum usb_dr_mode ci_hdrc_query_available_role(struct platform_device *pdev)
916 {
917 struct ci_hdrc *ci = platform_get_drvdata(pdev);
918
919 if (!ci)
920 return USB_DR_MODE_UNKNOWN;
921 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])
922 return USB_DR_MODE_OTG;
923 else if (ci->roles[CI_ROLE_HOST])
924 return USB_DR_MODE_HOST;
925 else if (ci->roles[CI_ROLE_GADGET])
926 return USB_DR_MODE_PERIPHERAL;
927 else
928 return USB_DR_MODE_UNKNOWN;
929 }
930 EXPORT_SYMBOL_GPL(ci_hdrc_query_available_role);
931
ci_role_destroy(struct ci_hdrc * ci)932 static inline void ci_role_destroy(struct ci_hdrc *ci)
933 {
934 ci_hdrc_gadget_destroy(ci);
935 ci_hdrc_host_destroy(ci);
936 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
937 ci_hdrc_otg_destroy(ci);
938 }
939
ci_get_otg_capable(struct ci_hdrc * ci)940 static void ci_get_otg_capable(struct ci_hdrc *ci)
941 {
942 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
943 ci->is_otg = false;
944 else
945 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
946 DCCPARAMS_DC | DCCPARAMS_HC)
947 == (DCCPARAMS_DC | DCCPARAMS_HC));
948 if (ci->is_otg) {
949 dev_dbg(ci->dev, "It is OTG capable controller\n");
950 /* Disable and clear all OTG irq */
951 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
952 OTGSC_INT_STATUS_BITS);
953 }
954 }
955
role_show(struct device * dev,struct device_attribute * attr,char * buf)956 static ssize_t role_show(struct device *dev, struct device_attribute *attr,
957 char *buf)
958 {
959 struct ci_hdrc *ci = dev_get_drvdata(dev);
960
961 if (ci->role != CI_ROLE_END)
962 return sprintf(buf, "%s\n", ci_role(ci)->name);
963
964 return 0;
965 }
966
role_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t n)967 static ssize_t role_store(struct device *dev,
968 struct device_attribute *attr, const char *buf, size_t n)
969 {
970 struct ci_hdrc *ci = dev_get_drvdata(dev);
971 enum ci_role role;
972 int ret;
973
974 if (!(ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])) {
975 dev_warn(dev, "Current configuration is not dual-role, quit\n");
976 return -EPERM;
977 }
978
979 for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++)
980 if (!strncmp(buf, ci->roles[role]->name,
981 strlen(ci->roles[role]->name)))
982 break;
983
984 if (role == CI_ROLE_END)
985 return -EINVAL;
986
987 mutex_lock(&ci->mutex);
988
989 if (role == ci->role) {
990 mutex_unlock(&ci->mutex);
991 return n;
992 }
993
994 pm_runtime_get_sync(dev);
995 disable_irq(ci->irq);
996 ci_role_stop(ci);
997 ret = ci_role_start(ci, role);
998 if (!ret && ci->role == CI_ROLE_GADGET)
999 ci_handle_vbus_change(ci);
1000 enable_irq(ci->irq);
1001 pm_runtime_put_sync(dev);
1002 mutex_unlock(&ci->mutex);
1003
1004 return (ret == 0) ? n : ret;
1005 }
1006 static DEVICE_ATTR_RW(role);
1007
1008 static struct attribute *ci_attrs[] = {
1009 &dev_attr_role.attr,
1010 NULL,
1011 };
1012 ATTRIBUTE_GROUPS(ci);
1013
ci_hdrc_probe(struct platform_device * pdev)1014 static int ci_hdrc_probe(struct platform_device *pdev)
1015 {
1016 struct device *dev = &pdev->dev;
1017 struct ci_hdrc *ci;
1018 struct resource *res;
1019 void __iomem *base;
1020 int ret;
1021 enum usb_dr_mode dr_mode;
1022
1023 if (!dev_get_platdata(dev)) {
1024 dev_err(dev, "platform data missing\n");
1025 return -ENODEV;
1026 }
1027
1028 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1029 base = devm_ioremap_resource(dev, res);
1030 if (IS_ERR(base))
1031 return PTR_ERR(base);
1032
1033 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
1034 if (!ci)
1035 return -ENOMEM;
1036
1037 spin_lock_init(&ci->lock);
1038 mutex_init(&ci->mutex);
1039 ci->dev = dev;
1040 ci->platdata = dev_get_platdata(dev);
1041 ci->imx28_write_fix = !!(ci->platdata->flags &
1042 CI_HDRC_IMX28_WRITE_FIX);
1043 ci->supports_runtime_pm = !!(ci->platdata->flags &
1044 CI_HDRC_SUPPORTS_RUNTIME_PM);
1045 platform_set_drvdata(pdev, ci);
1046
1047 ret = hw_device_init(ci, base);
1048 if (ret < 0) {
1049 dev_err(dev, "can't initialize hardware\n");
1050 return -ENODEV;
1051 }
1052
1053 ret = ci_ulpi_init(ci);
1054 if (ret)
1055 return ret;
1056
1057 if (ci->platdata->phy) {
1058 ci->phy = ci->platdata->phy;
1059 } else if (ci->platdata->usb_phy) {
1060 ci->usb_phy = ci->platdata->usb_phy;
1061 } else {
1062 /* Look for a generic PHY first */
1063 ci->phy = devm_phy_get(dev->parent, "usb-phy");
1064
1065 if (PTR_ERR(ci->phy) == -EPROBE_DEFER) {
1066 ret = -EPROBE_DEFER;
1067 goto ulpi_exit;
1068 } else if (IS_ERR(ci->phy)) {
1069 ci->phy = NULL;
1070 }
1071
1072 /* Look for a legacy USB PHY from device-tree next */
1073 if (!ci->phy) {
1074 ci->usb_phy = devm_usb_get_phy_by_phandle(dev->parent,
1075 "phys", 0);
1076
1077 if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) {
1078 ret = -EPROBE_DEFER;
1079 goto ulpi_exit;
1080 } else if (IS_ERR(ci->usb_phy)) {
1081 ci->usb_phy = NULL;
1082 }
1083 }
1084
1085 /* Look for any registered legacy USB PHY as last resort */
1086 if (!ci->phy && !ci->usb_phy) {
1087 ci->usb_phy = devm_usb_get_phy(dev->parent,
1088 USB_PHY_TYPE_USB2);
1089
1090 if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) {
1091 ret = -EPROBE_DEFER;
1092 goto ulpi_exit;
1093 } else if (IS_ERR(ci->usb_phy)) {
1094 ci->usb_phy = NULL;
1095 }
1096 }
1097
1098 /* No USB PHY was found in the end */
1099 if (!ci->phy && !ci->usb_phy) {
1100 ret = -ENXIO;
1101 goto ulpi_exit;
1102 }
1103 }
1104
1105 ret = ci_usb_phy_init(ci);
1106 if (ret) {
1107 dev_err(dev, "unable to init phy: %d\n", ret);
1108 goto ulpi_exit;
1109 }
1110
1111 ci->hw_bank.phys = res->start;
1112
1113 ci->irq = platform_get_irq(pdev, 0);
1114 if (ci->irq < 0) {
1115 ret = ci->irq;
1116 goto deinit_phy;
1117 }
1118
1119 ci_get_otg_capable(ci);
1120
1121 dr_mode = ci->platdata->dr_mode;
1122 /* initialize role(s) before the interrupt is requested */
1123 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
1124 ret = ci_hdrc_host_init(ci);
1125 if (ret) {
1126 if (ret == -ENXIO)
1127 dev_info(dev, "doesn't support host\n");
1128 else
1129 goto deinit_phy;
1130 }
1131 }
1132
1133 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
1134 ret = ci_hdrc_gadget_init(ci);
1135 if (ret) {
1136 if (ret == -ENXIO)
1137 dev_info(dev, "doesn't support gadget\n");
1138 else
1139 goto deinit_host;
1140 }
1141 }
1142
1143 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
1144 dev_err(dev, "no supported roles\n");
1145 ret = -ENODEV;
1146 goto deinit_gadget;
1147 }
1148
1149 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
1150 ret = ci_hdrc_otg_init(ci);
1151 if (ret) {
1152 dev_err(dev, "init otg fails, ret = %d\n", ret);
1153 goto deinit_gadget;
1154 }
1155 }
1156
1157 if (ci_role_switch.fwnode) {
1158 ci_role_switch.driver_data = ci;
1159 ci->role_switch = usb_role_switch_register(dev,
1160 &ci_role_switch);
1161 if (IS_ERR(ci->role_switch)) {
1162 ret = PTR_ERR(ci->role_switch);
1163 goto deinit_otg;
1164 }
1165 }
1166
1167 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
1168 if (ci->is_otg) {
1169 ci->role = ci_otg_role(ci);
1170 /* Enable ID change irq */
1171 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
1172 } else {
1173 /*
1174 * If the controller is not OTG capable, but support
1175 * role switch, the defalt role is gadget, and the
1176 * user can switch it through debugfs.
1177 */
1178 ci->role = CI_ROLE_GADGET;
1179 }
1180 } else {
1181 ci->role = ci->roles[CI_ROLE_HOST]
1182 ? CI_ROLE_HOST
1183 : CI_ROLE_GADGET;
1184 }
1185
1186 if (!ci_otg_is_fsm_mode(ci)) {
1187 /* only update vbus status for peripheral */
1188 if (ci->role == CI_ROLE_GADGET) {
1189 /* Pull down DP for possible charger detection */
1190 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
1191 ci_handle_vbus_change(ci);
1192 }
1193
1194 ret = ci_role_start(ci, ci->role);
1195 if (ret) {
1196 dev_err(dev, "can't start %s role\n",
1197 ci_role(ci)->name);
1198 goto stop;
1199 }
1200 }
1201
1202 ret = devm_request_irq(dev, ci->irq, ci_irq_handler, IRQF_SHARED,
1203 ci->platdata->name, ci);
1204 if (ret)
1205 goto stop;
1206
1207 ret = ci_extcon_register(ci);
1208 if (ret)
1209 goto stop;
1210
1211 if (ci->supports_runtime_pm) {
1212 pm_runtime_set_active(&pdev->dev);
1213 pm_runtime_enable(&pdev->dev);
1214 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
1215 pm_runtime_mark_last_busy(ci->dev);
1216 pm_runtime_use_autosuspend(&pdev->dev);
1217 }
1218
1219 if (ci_otg_is_fsm_mode(ci))
1220 ci_hdrc_otg_fsm_start(ci);
1221
1222 device_set_wakeup_capable(&pdev->dev, true);
1223 dbg_create_files(ci);
1224
1225 return 0;
1226
1227 stop:
1228 if (ci->role_switch)
1229 usb_role_switch_unregister(ci->role_switch);
1230 deinit_otg:
1231 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
1232 ci_hdrc_otg_destroy(ci);
1233 deinit_gadget:
1234 ci_hdrc_gadget_destroy(ci);
1235 deinit_host:
1236 ci_hdrc_host_destroy(ci);
1237 deinit_phy:
1238 ci_usb_phy_exit(ci);
1239 ulpi_exit:
1240 ci_ulpi_exit(ci);
1241
1242 return ret;
1243 }
1244
ci_hdrc_remove(struct platform_device * pdev)1245 static int ci_hdrc_remove(struct platform_device *pdev)
1246 {
1247 struct ci_hdrc *ci = platform_get_drvdata(pdev);
1248
1249 if (ci->role_switch)
1250 usb_role_switch_unregister(ci->role_switch);
1251
1252 if (ci->supports_runtime_pm) {
1253 pm_runtime_get_sync(&pdev->dev);
1254 pm_runtime_disable(&pdev->dev);
1255 pm_runtime_put_noidle(&pdev->dev);
1256 }
1257
1258 dbg_remove_files(ci);
1259 ci_role_destroy(ci);
1260 ci_hdrc_enter_lpm(ci, true);
1261 ci_usb_phy_exit(ci);
1262 ci_ulpi_exit(ci);
1263
1264 return 0;
1265 }
1266
1267 #ifdef CONFIG_PM
1268 /* Prepare wakeup by SRP before suspend */
ci_otg_fsm_suspend_for_srp(struct ci_hdrc * ci)1269 static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci)
1270 {
1271 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1272 !hw_read_otgsc(ci, OTGSC_ID)) {
1273 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
1274 PORTSC_PP);
1275 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN,
1276 PORTSC_WKCN);
1277 }
1278 }
1279
1280 /* Handle SRP when wakeup by data pulse */
ci_otg_fsm_wakeup_by_srp(struct ci_hdrc * ci)1281 static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci)
1282 {
1283 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1284 (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) {
1285 if (!hw_read_otgsc(ci, OTGSC_ID)) {
1286 ci->fsm.a_srp_det = 1;
1287 ci->fsm.a_bus_drop = 0;
1288 } else {
1289 ci->fsm.id = 1;
1290 }
1291 ci_otg_queue_work(ci);
1292 }
1293 }
1294
ci_controller_suspend(struct ci_hdrc * ci)1295 static void ci_controller_suspend(struct ci_hdrc *ci)
1296 {
1297 disable_irq(ci->irq);
1298 ci_hdrc_enter_lpm(ci, true);
1299 if (ci->platdata->phy_clkgate_delay_us)
1300 usleep_range(ci->platdata->phy_clkgate_delay_us,
1301 ci->platdata->phy_clkgate_delay_us + 50);
1302 usb_phy_set_suspend(ci->usb_phy, 1);
1303 ci->in_lpm = true;
1304 enable_irq(ci->irq);
1305 }
1306
1307 /*
1308 * Handle the wakeup interrupt triggered by extcon connector
1309 * We need to call ci_irq again for extcon since the first
1310 * interrupt (wakeup int) only let the controller be out of
1311 * low power mode, but not handle any interrupts.
1312 */
ci_extcon_wakeup_int(struct ci_hdrc * ci)1313 static void ci_extcon_wakeup_int(struct ci_hdrc *ci)
1314 {
1315 struct ci_hdrc_cable *cable_id, *cable_vbus;
1316 u32 otgsc = hw_read_otgsc(ci, ~0);
1317
1318 cable_id = &ci->platdata->id_extcon;
1319 cable_vbus = &ci->platdata->vbus_extcon;
1320
1321 if (!IS_ERR(cable_id->edev) && ci->is_otg &&
1322 (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS))
1323 ci_irq(ci);
1324
1325 if (!IS_ERR(cable_vbus->edev) && ci->is_otg &&
1326 (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS))
1327 ci_irq(ci);
1328 }
1329
ci_controller_resume(struct device * dev)1330 static int ci_controller_resume(struct device *dev)
1331 {
1332 struct ci_hdrc *ci = dev_get_drvdata(dev);
1333 int ret;
1334
1335 dev_dbg(dev, "at %s\n", __func__);
1336
1337 if (!ci->in_lpm) {
1338 WARN_ON(1);
1339 return 0;
1340 }
1341
1342 ci_hdrc_enter_lpm(ci, false);
1343
1344 ret = ci_ulpi_resume(ci);
1345 if (ret)
1346 return ret;
1347
1348 if (ci->usb_phy) {
1349 usb_phy_set_suspend(ci->usb_phy, 0);
1350 usb_phy_set_wakeup(ci->usb_phy, false);
1351 hw_wait_phy_stable();
1352 }
1353
1354 ci->in_lpm = false;
1355 if (ci->wakeup_int) {
1356 ci->wakeup_int = false;
1357 pm_runtime_mark_last_busy(ci->dev);
1358 pm_runtime_put_autosuspend(ci->dev);
1359 enable_irq(ci->irq);
1360 if (ci_otg_is_fsm_mode(ci))
1361 ci_otg_fsm_wakeup_by_srp(ci);
1362 ci_extcon_wakeup_int(ci);
1363 }
1364
1365 return 0;
1366 }
1367
1368 #ifdef CONFIG_PM_SLEEP
ci_suspend(struct device * dev)1369 static int ci_suspend(struct device *dev)
1370 {
1371 struct ci_hdrc *ci = dev_get_drvdata(dev);
1372
1373 if (ci->wq)
1374 flush_workqueue(ci->wq);
1375 /*
1376 * Controller needs to be active during suspend, otherwise the core
1377 * may run resume when the parent is at suspend if other driver's
1378 * suspend fails, it occurs before parent's suspend has not started,
1379 * but the core suspend has finished.
1380 */
1381 if (ci->in_lpm)
1382 pm_runtime_resume(dev);
1383
1384 if (ci->in_lpm) {
1385 WARN_ON(1);
1386 return 0;
1387 }
1388
1389 if (device_may_wakeup(dev)) {
1390 if (ci_otg_is_fsm_mode(ci))
1391 ci_otg_fsm_suspend_for_srp(ci);
1392
1393 usb_phy_set_wakeup(ci->usb_phy, true);
1394 enable_irq_wake(ci->irq);
1395 }
1396
1397 ci_controller_suspend(ci);
1398
1399 return 0;
1400 }
1401
ci_resume(struct device * dev)1402 static int ci_resume(struct device *dev)
1403 {
1404 struct ci_hdrc *ci = dev_get_drvdata(dev);
1405 int ret;
1406
1407 if (device_may_wakeup(dev))
1408 disable_irq_wake(ci->irq);
1409
1410 ret = ci_controller_resume(dev);
1411 if (ret)
1412 return ret;
1413
1414 if (ci->supports_runtime_pm) {
1415 pm_runtime_disable(dev);
1416 pm_runtime_set_active(dev);
1417 pm_runtime_enable(dev);
1418 }
1419
1420 return ret;
1421 }
1422 #endif /* CONFIG_PM_SLEEP */
1423
ci_runtime_suspend(struct device * dev)1424 static int ci_runtime_suspend(struct device *dev)
1425 {
1426 struct ci_hdrc *ci = dev_get_drvdata(dev);
1427
1428 dev_dbg(dev, "at %s\n", __func__);
1429
1430 if (ci->in_lpm) {
1431 WARN_ON(1);
1432 return 0;
1433 }
1434
1435 if (ci_otg_is_fsm_mode(ci))
1436 ci_otg_fsm_suspend_for_srp(ci);
1437
1438 usb_phy_set_wakeup(ci->usb_phy, true);
1439 ci_controller_suspend(ci);
1440
1441 return 0;
1442 }
1443
ci_runtime_resume(struct device * dev)1444 static int ci_runtime_resume(struct device *dev)
1445 {
1446 return ci_controller_resume(dev);
1447 }
1448
1449 #endif /* CONFIG_PM */
1450 static const struct dev_pm_ops ci_pm_ops = {
1451 SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
1452 SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
1453 };
1454
1455 static struct platform_driver ci_hdrc_driver = {
1456 .probe = ci_hdrc_probe,
1457 .remove = ci_hdrc_remove,
1458 .driver = {
1459 .name = "ci_hdrc",
1460 .pm = &ci_pm_ops,
1461 .dev_groups = ci_groups,
1462 },
1463 };
1464
ci_hdrc_platform_register(void)1465 static int __init ci_hdrc_platform_register(void)
1466 {
1467 ci_hdrc_host_driver_init();
1468 return platform_driver_register(&ci_hdrc_driver);
1469 }
1470 module_init(ci_hdrc_platform_register);
1471
ci_hdrc_platform_unregister(void)1472 static void __exit ci_hdrc_platform_unregister(void)
1473 {
1474 platform_driver_unregister(&ci_hdrc_driver);
1475 }
1476 module_exit(ci_hdrc_platform_unregister);
1477
1478 MODULE_ALIAS("platform:ci_hdrc");
1479 MODULE_LICENSE("GPL v2");
1480 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
1481 MODULE_DESCRIPTION("ChipIdea HDRC Driver");
1482