1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * dwc3-pci.c - PCI Specific glue layer
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/slab.h>
14 #include <linux/pci.h>
15 #include <linux/workqueue.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/platform_device.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/gpio/machine.h>
20 #include <linux/acpi.h>
21 #include <linux/delay.h>
22
23 #define PCI_DEVICE_ID_INTEL_BYT 0x0f37
24 #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e
25 #define PCI_DEVICE_ID_INTEL_BSW 0x22b7
26 #define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30
27 #define PCI_DEVICE_ID_INTEL_SPTH 0xa130
28 #define PCI_DEVICE_ID_INTEL_BXT 0x0aaa
29 #define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa
30 #define PCI_DEVICE_ID_INTEL_APL 0x5aaa
31 #define PCI_DEVICE_ID_INTEL_KBP 0xa2b0
32 #define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee
33 #define PCI_DEVICE_ID_INTEL_CMLH 0x06ee
34 #define PCI_DEVICE_ID_INTEL_GLK 0x31aa
35 #define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee
36 #define PCI_DEVICE_ID_INTEL_CNPH 0xa36e
37 #define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0
38 #define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee
39 #define PCI_DEVICE_ID_INTEL_EHL 0x4b7e
40 #define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee
41 #define PCI_DEVICE_ID_INTEL_TGPH 0x43ee
42 #define PCI_DEVICE_ID_INTEL_JSP 0x4dee
43 #define PCI_DEVICE_ID_INTEL_ADLP 0x51ee
44 #define PCI_DEVICE_ID_INTEL_ADLM 0x54ee
45 #define PCI_DEVICE_ID_INTEL_ADLS 0x7ae1
46 #define PCI_DEVICE_ID_INTEL_RPL 0xa70e
47 #define PCI_DEVICE_ID_INTEL_RPLS 0x7a61
48 #define PCI_DEVICE_ID_INTEL_MTLM 0x7eb1
49 #define PCI_DEVICE_ID_INTEL_MTLP 0x7ec1
50 #define PCI_DEVICE_ID_INTEL_MTLS 0x7f6f
51 #define PCI_DEVICE_ID_INTEL_MTL 0x7e7e
52 #define PCI_DEVICE_ID_INTEL_TGL 0x9a15
53 #define PCI_DEVICE_ID_AMD_MR 0x163a
54
55 #define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
56 #define PCI_INTEL_BXT_FUNC_PMU_PWR 4
57 #define PCI_INTEL_BXT_STATE_D0 0
58 #define PCI_INTEL_BXT_STATE_D3 3
59
60 #define GP_RWBAR 1
61 #define GP_RWREG1 0xa0
62 #define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17)
63
64 /**
65 * struct dwc3_pci - Driver private structure
66 * @dwc3: child dwc3 platform_device
67 * @pci: our link to PCI bus
68 * @guid: _DSM GUID
69 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
70 * @wakeup_work: work for asynchronous resume
71 */
72 struct dwc3_pci {
73 struct platform_device *dwc3;
74 struct pci_dev *pci;
75
76 guid_t guid;
77
78 unsigned int has_dsm_for_pm:1;
79 struct work_struct wakeup_work;
80 };
81
82 static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
83 static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
84
85 static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
86 { "reset-gpios", &reset_gpios, 1 },
87 { "cs-gpios", &cs_gpios, 1 },
88 { },
89 };
90
91 static struct gpiod_lookup_table platform_bytcr_gpios = {
92 .dev_id = "0000:00:16.0",
93 .table = {
94 GPIO_LOOKUP("INT33FC:00", 54, "cs", GPIO_ACTIVE_HIGH),
95 GPIO_LOOKUP("INT33FC:02", 14, "reset", GPIO_ACTIVE_HIGH),
96 {}
97 },
98 };
99
dwc3_byt_enable_ulpi_refclock(struct pci_dev * pci)100 static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci)
101 {
102 void __iomem *reg;
103 u32 value;
104
105 reg = pcim_iomap(pci, GP_RWBAR, 0);
106 if (!reg)
107 return -ENOMEM;
108
109 value = readl(reg + GP_RWREG1);
110 if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE))
111 goto unmap; /* ULPI refclk already enabled */
112
113 value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE;
114 writel(value, reg + GP_RWREG1);
115 /* This comes from the Intel Android x86 tree w/o any explanation */
116 msleep(100);
117 unmap:
118 pcim_iounmap(pci, reg);
119 return 0;
120 }
121
122 static const struct property_entry dwc3_pci_intel_properties[] = {
123 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
124 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
125 {}
126 };
127
128 static const struct property_entry dwc3_pci_intel_byt_properties[] = {
129 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
130 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
131 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
132 {}
133 };
134
135 static const struct property_entry dwc3_pci_mrfld_properties[] = {
136 PROPERTY_ENTRY_STRING("dr_mode", "otg"),
137 PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"),
138 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
139 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
140 PROPERTY_ENTRY_BOOL("snps,usb2-gadget-lpm-disable"),
141 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
142 {}
143 };
144
145 static const struct property_entry dwc3_pci_amd_properties[] = {
146 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
147 PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
148 PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
149 PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
150 PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
151 PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
152 PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
153 PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
154 PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
155 PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
156 PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
157 /* FIXME these quirks should be removed when AMD NL tapes out */
158 PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
159 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
160 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
161 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
162 {}
163 };
164
165 static const struct property_entry dwc3_pci_mr_properties[] = {
166 PROPERTY_ENTRY_STRING("dr_mode", "otg"),
167 PROPERTY_ENTRY_BOOL("usb-role-switch"),
168 PROPERTY_ENTRY_STRING("role-switch-default-mode", "host"),
169 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
170 {}
171 };
172
173 static const struct software_node dwc3_pci_intel_swnode = {
174 .properties = dwc3_pci_intel_properties,
175 };
176
177 static const struct software_node dwc3_pci_intel_byt_swnode = {
178 .properties = dwc3_pci_intel_byt_properties,
179 };
180
181 static const struct software_node dwc3_pci_intel_mrfld_swnode = {
182 .properties = dwc3_pci_mrfld_properties,
183 };
184
185 static const struct software_node dwc3_pci_amd_swnode = {
186 .properties = dwc3_pci_amd_properties,
187 };
188
189 static const struct software_node dwc3_pci_amd_mr_swnode = {
190 .properties = dwc3_pci_mr_properties,
191 };
192
dwc3_pci_quirks(struct dwc3_pci * dwc,const struct software_node * swnode)193 static int dwc3_pci_quirks(struct dwc3_pci *dwc,
194 const struct software_node *swnode)
195 {
196 struct pci_dev *pdev = dwc->pci;
197
198 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
199 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT ||
200 pdev->device == PCI_DEVICE_ID_INTEL_BXT_M ||
201 pdev->device == PCI_DEVICE_ID_INTEL_EHL) {
202 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid);
203 dwc->has_dsm_for_pm = true;
204 }
205
206 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
207 struct gpio_desc *gpio;
208 int ret;
209
210 /* On BYT the FW does not always enable the refclock */
211 ret = dwc3_byt_enable_ulpi_refclock(pdev);
212 if (ret)
213 return ret;
214
215 ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
216 acpi_dwc3_byt_gpios);
217 if (ret)
218 dev_dbg(&pdev->dev, "failed to add mapping table\n");
219
220 /*
221 * A lot of BYT devices lack ACPI resource entries for
222 * the GPIOs. If the ACPI entry for the GPIO controller
223 * is present add a fallback mapping to the reference
224 * design GPIOs which all boards seem to use.
225 */
226 if (acpi_dev_present("INT33FC", NULL, -1))
227 gpiod_add_lookup_table(&platform_bytcr_gpios);
228
229 /*
230 * These GPIOs will turn on the USB2 PHY. Note that we have to
231 * put the gpio descriptors again here because the phy driver
232 * might want to grab them, too.
233 */
234 gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
235 if (IS_ERR(gpio))
236 return PTR_ERR(gpio);
237
238 gpiod_set_value_cansleep(gpio, 1);
239 gpiod_put(gpio);
240
241 gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
242 if (IS_ERR(gpio))
243 return PTR_ERR(gpio);
244
245 if (gpio) {
246 gpiod_set_value_cansleep(gpio, 1);
247 gpiod_put(gpio);
248 usleep_range(10000, 11000);
249 }
250 }
251 }
252
253 return device_add_software_node(&dwc->dwc3->dev, swnode);
254 }
255
256 #ifdef CONFIG_PM
dwc3_pci_resume_work(struct work_struct * work)257 static void dwc3_pci_resume_work(struct work_struct *work)
258 {
259 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work);
260 struct platform_device *dwc3 = dwc->dwc3;
261 int ret;
262
263 ret = pm_runtime_get_sync(&dwc3->dev);
264 if (ret < 0) {
265 pm_runtime_put_sync_autosuspend(&dwc3->dev);
266 return;
267 }
268
269 pm_runtime_mark_last_busy(&dwc3->dev);
270 pm_runtime_put_sync_autosuspend(&dwc3->dev);
271 }
272 #endif
273
dwc3_pci_probe(struct pci_dev * pci,const struct pci_device_id * id)274 static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
275 {
276 struct dwc3_pci *dwc;
277 struct resource res[2];
278 int ret;
279 struct device *dev = &pci->dev;
280
281 ret = pcim_enable_device(pci);
282 if (ret) {
283 dev_err(dev, "failed to enable pci device\n");
284 return -ENODEV;
285 }
286
287 pci_set_master(pci);
288
289 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
290 if (!dwc)
291 return -ENOMEM;
292
293 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
294 if (!dwc->dwc3)
295 return -ENOMEM;
296
297 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
298
299 res[0].start = pci_resource_start(pci, 0);
300 res[0].end = pci_resource_end(pci, 0);
301 res[0].name = "dwc_usb3";
302 res[0].flags = IORESOURCE_MEM;
303
304 res[1].start = pci->irq;
305 res[1].name = "dwc_usb3";
306 res[1].flags = IORESOURCE_IRQ;
307
308 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
309 if (ret) {
310 dev_err(dev, "couldn't add resources to dwc3 device\n");
311 goto err;
312 }
313
314 dwc->pci = pci;
315 dwc->dwc3->dev.parent = dev;
316 ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));
317
318 ret = dwc3_pci_quirks(dwc, (void *)id->driver_data);
319 if (ret)
320 goto err;
321
322 ret = platform_device_add(dwc->dwc3);
323 if (ret) {
324 dev_err(dev, "failed to register dwc3 device\n");
325 goto err;
326 }
327
328 device_init_wakeup(dev, true);
329 pci_set_drvdata(pci, dwc);
330 pm_runtime_put(dev);
331 #ifdef CONFIG_PM
332 INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work);
333 #endif
334
335 return 0;
336 err:
337 device_remove_software_node(&dwc->dwc3->dev);
338 platform_device_put(dwc->dwc3);
339 return ret;
340 }
341
dwc3_pci_remove(struct pci_dev * pci)342 static void dwc3_pci_remove(struct pci_dev *pci)
343 {
344 struct dwc3_pci *dwc = pci_get_drvdata(pci);
345 struct pci_dev *pdev = dwc->pci;
346
347 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT)
348 gpiod_remove_lookup_table(&platform_bytcr_gpios);
349 #ifdef CONFIG_PM
350 cancel_work_sync(&dwc->wakeup_work);
351 #endif
352 device_init_wakeup(&pci->dev, false);
353 pm_runtime_get(&pci->dev);
354 device_remove_software_node(&dwc->dwc3->dev);
355 platform_device_unregister(dwc->dwc3);
356 }
357
358 static const struct pci_device_id dwc3_pci_id_table[] = {
359 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW),
360 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
361
362 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT),
363 (kernel_ulong_t) &dwc3_pci_intel_byt_swnode, },
364
365 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD),
366 (kernel_ulong_t) &dwc3_pci_intel_mrfld_swnode, },
367
368 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP),
369 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
370
371 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH),
372 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
373
374 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP),
375 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
376
377 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH),
378 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
379
380 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT),
381 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
382
383 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M),
384 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
385
386 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL),
387 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
388
389 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP),
390 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
391
392 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK),
393 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
394
395 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP),
396 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
397
398 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH),
399 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
400
401 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPV),
402 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
403
404 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP),
405 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
406
407 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_EHL),
408 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
409
410 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP),
411 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
412
413 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPH),
414 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
415
416 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_JSP),
417 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
418
419 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLP),
420 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
421
422 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLM),
423 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
424
425 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLS),
426 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
427
428 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPL),
429 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
430
431 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPLS),
432 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
433
434 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTLM),
435 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
436
437 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTLP),
438 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
439
440 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTLS),
441 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
442
443 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL),
444 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
445
446 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL),
447 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
448
449 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB),
450 (kernel_ulong_t) &dwc3_pci_amd_swnode, },
451
452 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_MR),
453 (kernel_ulong_t)&dwc3_pci_amd_mr_swnode, },
454
455 { } /* Terminating Entry */
456 };
457 MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
458
459 #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP)
dwc3_pci_dsm(struct dwc3_pci * dwc,int param)460 static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
461 {
462 union acpi_object *obj;
463 union acpi_object tmp;
464 union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
465
466 if (!dwc->has_dsm_for_pm)
467 return 0;
468
469 tmp.type = ACPI_TYPE_INTEGER;
470 tmp.integer.value = param;
471
472 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid,
473 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
474 if (!obj) {
475 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
476 return -EIO;
477 }
478
479 ACPI_FREE(obj);
480
481 return 0;
482 }
483 #endif /* CONFIG_PM || CONFIG_PM_SLEEP */
484
485 #ifdef CONFIG_PM
dwc3_pci_runtime_suspend(struct device * dev)486 static int dwc3_pci_runtime_suspend(struct device *dev)
487 {
488 struct dwc3_pci *dwc = dev_get_drvdata(dev);
489
490 if (device_can_wakeup(dev))
491 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
492
493 return -EBUSY;
494 }
495
dwc3_pci_runtime_resume(struct device * dev)496 static int dwc3_pci_runtime_resume(struct device *dev)
497 {
498 struct dwc3_pci *dwc = dev_get_drvdata(dev);
499 int ret;
500
501 ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
502 if (ret)
503 return ret;
504
505 queue_work(pm_wq, &dwc->wakeup_work);
506
507 return 0;
508 }
509 #endif /* CONFIG_PM */
510
511 #ifdef CONFIG_PM_SLEEP
dwc3_pci_suspend(struct device * dev)512 static int dwc3_pci_suspend(struct device *dev)
513 {
514 struct dwc3_pci *dwc = dev_get_drvdata(dev);
515
516 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
517 }
518
dwc3_pci_resume(struct device * dev)519 static int dwc3_pci_resume(struct device *dev)
520 {
521 struct dwc3_pci *dwc = dev_get_drvdata(dev);
522
523 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
524 }
525 #endif /* CONFIG_PM_SLEEP */
526
527 static const struct dev_pm_ops dwc3_pci_dev_pm_ops = {
528 SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
529 SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
530 NULL)
531 };
532
533 static struct pci_driver dwc3_pci_driver = {
534 .name = "dwc3-pci",
535 .id_table = dwc3_pci_id_table,
536 .probe = dwc3_pci_probe,
537 .remove = dwc3_pci_remove,
538 .driver = {
539 .pm = &dwc3_pci_dev_pm_ops,
540 }
541 };
542
543 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
544 MODULE_LICENSE("GPL v2");
545 MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
546
547 module_pci_driver(dwc3_pci_driver);
548