1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MediaTek xHCI Host Controller Driver
4 *
5 * Copyright (c) 2015 MediaTek Inc.
6 * Author:
7 * Chunfeng Yun <chunfeng.yun@mediatek.com>
8 */
9
10 #include <linux/bitfield.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/iopoll.h>
13 #include <linux/kernel.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/pm_wakeirq.h>
20 #include <linux/regmap.h>
21 #include <linux/regulator/consumer.h>
22
23 #include "xhci.h"
24 #include "xhci-mtk.h"
25
26 /* ip_pw_ctrl0 register */
27 #define CTRL0_IP_SW_RST BIT(0)
28
29 /* ip_pw_ctrl1 register */
30 #define CTRL1_IP_HOST_PDN BIT(0)
31
32 /* ip_pw_ctrl2 register */
33 #define CTRL2_IP_DEV_PDN BIT(0)
34
35 /* ip_pw_sts1 register */
36 #define STS1_IP_SLEEP_STS BIT(30)
37 #define STS1_U3_MAC_RST BIT(16)
38 #define STS1_XHCI_RST BIT(11)
39 #define STS1_SYS125_RST BIT(10)
40 #define STS1_REF_RST BIT(8)
41 #define STS1_SYSPLL_STABLE BIT(0)
42
43 /* ip_xhci_cap register */
44 #define CAP_U3_PORT_NUM(p) ((p) & 0xff)
45 #define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff)
46
47 /* u3_ctrl_p register */
48 #define CTRL_U3_PORT_HOST_SEL BIT(2)
49 #define CTRL_U3_PORT_PDN BIT(1)
50 #define CTRL_U3_PORT_DIS BIT(0)
51
52 /* u2_ctrl_p register */
53 #define CTRL_U2_PORT_HOST_SEL BIT(2)
54 #define CTRL_U2_PORT_PDN BIT(1)
55 #define CTRL_U2_PORT_DIS BIT(0)
56
57 /* u2_phy_pll register */
58 #define CTRL_U2_FORCE_PLL_STB BIT(28)
59
60 /* xHCI CSR */
61 #define LS_EOF_CFG 0x930
62 #define LSEOF_OFFSET 0x89
63
64 #define FS_EOF_CFG 0x934
65 #define FSEOF_OFFSET 0x2e
66
67 #define SS_GEN1_EOF_CFG 0x93c
68 #define SSG1EOF_OFFSET 0x78
69
70 #define HFCNTR_CFG 0x944
71 #define ITP_DELTA_CLK (0xa << 1)
72 #define ITP_DELTA_CLK_MASK GENMASK(5, 1)
73 #define FRMCNT_LEV1_RANG (0x12b << 8)
74 #define FRMCNT_LEV1_RANG_MASK GENMASK(19, 8)
75
76 #define HSCH_CFG1 0x960
77 #define SCH3_RXFIFO_DEPTH_MASK GENMASK(21, 20)
78
79 #define SS_GEN2_EOF_CFG 0x990
80 #define SSG2EOF_OFFSET 0x3c
81
82 #define XSEOF_OFFSET_MASK GENMASK(11, 0)
83
84 /* usb remote wakeup registers in syscon */
85
86 /* mt8173 etc */
87 #define PERI_WK_CTRL1 0x4
88 #define WC1_IS_C(x) (((x) & 0xf) << 26) /* cycle debounce */
89 #define WC1_IS_EN BIT(25)
90 #define WC1_IS_P BIT(6) /* polarity for ip sleep */
91
92 /* mt8183 */
93 #define PERI_WK_CTRL0 0x0
94 #define WC0_IS_C(x) ((u32)(((x) & 0xf) << 28)) /* cycle debounce */
95 #define WC0_IS_P BIT(12) /* polarity */
96 #define WC0_IS_EN BIT(6)
97
98 /* mt8192 */
99 #define WC0_SSUSB0_CDEN BIT(6)
100 #define WC0_IS_SPM_EN BIT(1)
101
102 /* mt2712 etc */
103 #define PERI_SSUSB_SPM_CTRL 0x0
104 #define SSC_IP_SLEEP_EN BIT(4)
105 #define SSC_SPM_INT_EN BIT(1)
106
107 #define SCH_FIFO_TO_KB(x) ((x) >> 10)
108
109 enum ssusb_uwk_vers {
110 SSUSB_UWK_V1 = 1,
111 SSUSB_UWK_V2,
112 SSUSB_UWK_V1_1 = 101, /* specific revision 1.01 */
113 SSUSB_UWK_V1_2, /* specific revision 1.2 */
114 };
115
116 /*
117 * MT8195 has 4 controllers, the controller1~3's default SOF/ITP interval
118 * is calculated from the frame counter clock 24M, but in fact, the clock
119 * is 48M, add workaround for it.
120 */
xhci_mtk_set_frame_interval(struct xhci_hcd_mtk * mtk)121 static void xhci_mtk_set_frame_interval(struct xhci_hcd_mtk *mtk)
122 {
123 struct device *dev = mtk->dev;
124 struct usb_hcd *hcd = mtk->hcd;
125 u32 value;
126
127 if (!of_device_is_compatible(dev->of_node, "mediatek,mt8195-xhci"))
128 return;
129
130 value = readl(hcd->regs + HFCNTR_CFG);
131 value &= ~(ITP_DELTA_CLK_MASK | FRMCNT_LEV1_RANG_MASK);
132 value |= (ITP_DELTA_CLK | FRMCNT_LEV1_RANG);
133 writel(value, hcd->regs + HFCNTR_CFG);
134
135 value = readl(hcd->regs + LS_EOF_CFG);
136 value &= ~XSEOF_OFFSET_MASK;
137 value |= LSEOF_OFFSET;
138 writel(value, hcd->regs + LS_EOF_CFG);
139
140 value = readl(hcd->regs + FS_EOF_CFG);
141 value &= ~XSEOF_OFFSET_MASK;
142 value |= FSEOF_OFFSET;
143 writel(value, hcd->regs + FS_EOF_CFG);
144
145 value = readl(hcd->regs + SS_GEN1_EOF_CFG);
146 value &= ~XSEOF_OFFSET_MASK;
147 value |= SSG1EOF_OFFSET;
148 writel(value, hcd->regs + SS_GEN1_EOF_CFG);
149
150 value = readl(hcd->regs + SS_GEN2_EOF_CFG);
151 value &= ~XSEOF_OFFSET_MASK;
152 value |= SSG2EOF_OFFSET;
153 writel(value, hcd->regs + SS_GEN2_EOF_CFG);
154 }
155
156 /*
157 * workaround: usb3.2 gen1 isoc rx hw issue
158 * host send out unexpected ACK afer device fininsh a burst transfer with
159 * a short packet.
160 */
xhci_mtk_rxfifo_depth_set(struct xhci_hcd_mtk * mtk)161 static void xhci_mtk_rxfifo_depth_set(struct xhci_hcd_mtk *mtk)
162 {
163 struct usb_hcd *hcd = mtk->hcd;
164 u32 value;
165
166 if (!mtk->rxfifo_depth)
167 return;
168
169 value = readl(hcd->regs + HSCH_CFG1);
170 value &= ~SCH3_RXFIFO_DEPTH_MASK;
171 value |= FIELD_PREP(SCH3_RXFIFO_DEPTH_MASK,
172 SCH_FIFO_TO_KB(mtk->rxfifo_depth) - 1);
173 writel(value, hcd->regs + HSCH_CFG1);
174 }
175
xhci_mtk_init_quirk(struct xhci_hcd_mtk * mtk)176 static void xhci_mtk_init_quirk(struct xhci_hcd_mtk *mtk)
177 {
178 /* workaround only for mt8195 */
179 xhci_mtk_set_frame_interval(mtk);
180
181 /* workaround for SoCs using SSUSB about before IPM v1.6.0 */
182 xhci_mtk_rxfifo_depth_set(mtk);
183 }
184
xhci_mtk_host_enable(struct xhci_hcd_mtk * mtk)185 static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
186 {
187 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
188 u32 value, check_val;
189 int u3_ports_disabled = 0;
190 int ret;
191 int i;
192
193 if (!mtk->has_ippc)
194 return 0;
195
196 /* power on host ip */
197 value = readl(&ippc->ip_pw_ctr1);
198 value &= ~CTRL1_IP_HOST_PDN;
199 writel(value, &ippc->ip_pw_ctr1);
200
201 /* power on and enable u3 ports except skipped ones */
202 for (i = 0; i < mtk->num_u3_ports; i++) {
203 if ((0x1 << i) & mtk->u3p_dis_msk) {
204 u3_ports_disabled++;
205 continue;
206 }
207
208 value = readl(&ippc->u3_ctrl_p[i]);
209 value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS);
210 value |= CTRL_U3_PORT_HOST_SEL;
211 writel(value, &ippc->u3_ctrl_p[i]);
212 }
213
214 /* power on and enable all u2 ports except skipped ones */
215 for (i = 0; i < mtk->num_u2_ports; i++) {
216 if (BIT(i) & mtk->u2p_dis_msk)
217 continue;
218
219 value = readl(&ippc->u2_ctrl_p[i]);
220 value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS);
221 value |= CTRL_U2_PORT_HOST_SEL;
222 writel(value, &ippc->u2_ctrl_p[i]);
223 }
224
225 /*
226 * wait for clocks to be stable, and clock domains reset to
227 * be inactive after power on and enable ports
228 */
229 check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
230 STS1_SYS125_RST | STS1_XHCI_RST;
231
232 if (mtk->num_u3_ports > u3_ports_disabled)
233 check_val |= STS1_U3_MAC_RST;
234
235 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
236 (check_val == (value & check_val)), 100, 20000);
237 if (ret) {
238 dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value);
239 return ret;
240 }
241
242 return 0;
243 }
244
xhci_mtk_host_disable(struct xhci_hcd_mtk * mtk)245 static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk)
246 {
247 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
248 u32 value;
249 int ret;
250 int i;
251
252 if (!mtk->has_ippc)
253 return 0;
254
255 /* power down u3 ports except skipped ones */
256 for (i = 0; i < mtk->num_u3_ports; i++) {
257 if ((0x1 << i) & mtk->u3p_dis_msk)
258 continue;
259
260 value = readl(&ippc->u3_ctrl_p[i]);
261 value |= CTRL_U3_PORT_PDN;
262 writel(value, &ippc->u3_ctrl_p[i]);
263 }
264
265 /* power down all u2 ports except skipped ones */
266 for (i = 0; i < mtk->num_u2_ports; i++) {
267 if (BIT(i) & mtk->u2p_dis_msk)
268 continue;
269
270 value = readl(&ippc->u2_ctrl_p[i]);
271 value |= CTRL_U2_PORT_PDN;
272 writel(value, &ippc->u2_ctrl_p[i]);
273 }
274
275 /* power down host ip */
276 value = readl(&ippc->ip_pw_ctr1);
277 value |= CTRL1_IP_HOST_PDN;
278 writel(value, &ippc->ip_pw_ctr1);
279
280 /* wait for host ip to sleep */
281 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
282 (value & STS1_IP_SLEEP_STS), 100, 100000);
283 if (ret) {
284 dev_err(mtk->dev, "ip sleep failed!!!\n");
285 return ret;
286 }
287 return 0;
288 }
289
xhci_mtk_ssusb_config(struct xhci_hcd_mtk * mtk)290 static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk)
291 {
292 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
293 u32 value;
294
295 if (!mtk->has_ippc)
296 return 0;
297
298 /* reset whole ip */
299 value = readl(&ippc->ip_pw_ctr0);
300 value |= CTRL0_IP_SW_RST;
301 writel(value, &ippc->ip_pw_ctr0);
302 udelay(1);
303 value = readl(&ippc->ip_pw_ctr0);
304 value &= ~CTRL0_IP_SW_RST;
305 writel(value, &ippc->ip_pw_ctr0);
306
307 /*
308 * device ip is default power-on in fact
309 * power down device ip, otherwise ip-sleep will fail
310 */
311 value = readl(&ippc->ip_pw_ctr2);
312 value |= CTRL2_IP_DEV_PDN;
313 writel(value, &ippc->ip_pw_ctr2);
314
315 value = readl(&ippc->ip_xhci_cap);
316 mtk->num_u3_ports = CAP_U3_PORT_NUM(value);
317 mtk->num_u2_ports = CAP_U2_PORT_NUM(value);
318 dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__,
319 mtk->num_u2_ports, mtk->num_u3_ports);
320
321 return xhci_mtk_host_enable(mtk);
322 }
323
324 /* only clocks can be turn off for ip-sleep wakeup mode */
usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk * mtk,bool enable)325 static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable)
326 {
327 u32 reg, msk, val;
328
329 switch (mtk->uwk_vers) {
330 case SSUSB_UWK_V1:
331 reg = mtk->uwk_reg_base + PERI_WK_CTRL1;
332 msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P;
333 val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0;
334 break;
335 case SSUSB_UWK_V1_1:
336 reg = mtk->uwk_reg_base + PERI_WK_CTRL0;
337 msk = WC0_IS_EN | WC0_IS_C(0xf) | WC0_IS_P;
338 val = enable ? (WC0_IS_EN | WC0_IS_C(0x8)) : 0;
339 break;
340 case SSUSB_UWK_V1_2:
341 reg = mtk->uwk_reg_base + PERI_WK_CTRL0;
342 msk = WC0_SSUSB0_CDEN | WC0_IS_SPM_EN;
343 val = enable ? msk : 0;
344 break;
345 case SSUSB_UWK_V2:
346 reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL;
347 msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN;
348 val = enable ? msk : 0;
349 break;
350 default:
351 return;
352 }
353 regmap_update_bits(mtk->uwk, reg, msk, val);
354 }
355
usb_wakeup_of_property_parse(struct xhci_hcd_mtk * mtk,struct device_node * dn)356 static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk,
357 struct device_node *dn)
358 {
359 struct of_phandle_args args;
360 int ret;
361
362 /* Wakeup function is optional */
363 mtk->uwk_en = of_property_read_bool(dn, "wakeup-source");
364 if (!mtk->uwk_en)
365 return 0;
366
367 ret = of_parse_phandle_with_fixed_args(dn,
368 "mediatek,syscon-wakeup", 2, 0, &args);
369 if (ret)
370 return ret;
371
372 mtk->uwk_reg_base = args.args[0];
373 mtk->uwk_vers = args.args[1];
374 mtk->uwk = syscon_node_to_regmap(args.np);
375 of_node_put(args.np);
376 dev_info(mtk->dev, "uwk - reg:0x%x, version:%d\n",
377 mtk->uwk_reg_base, mtk->uwk_vers);
378
379 return PTR_ERR_OR_ZERO(mtk->uwk);
380 }
381
usb_wakeup_set(struct xhci_hcd_mtk * mtk,bool enable)382 static void usb_wakeup_set(struct xhci_hcd_mtk *mtk, bool enable)
383 {
384 if (mtk->uwk_en)
385 usb_wakeup_ip_sleep_set(mtk, enable);
386 }
387
xhci_mtk_clks_get(struct xhci_hcd_mtk * mtk)388 static int xhci_mtk_clks_get(struct xhci_hcd_mtk *mtk)
389 {
390 struct clk_bulk_data *clks = mtk->clks;
391
392 clks[0].id = "sys_ck";
393 clks[1].id = "xhci_ck";
394 clks[2].id = "ref_ck";
395 clks[3].id = "mcu_ck";
396 clks[4].id = "dma_ck";
397
398 return devm_clk_bulk_get_optional(mtk->dev, BULK_CLKS_NUM, clks);
399 }
400
xhci_mtk_ldos_enable(struct xhci_hcd_mtk * mtk)401 static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk)
402 {
403 int ret;
404
405 ret = regulator_enable(mtk->vbus);
406 if (ret) {
407 dev_err(mtk->dev, "failed to enable vbus\n");
408 return ret;
409 }
410
411 ret = regulator_enable(mtk->vusb33);
412 if (ret) {
413 dev_err(mtk->dev, "failed to enable vusb33\n");
414 regulator_disable(mtk->vbus);
415 return ret;
416 }
417 return 0;
418 }
419
xhci_mtk_ldos_disable(struct xhci_hcd_mtk * mtk)420 static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk)
421 {
422 regulator_disable(mtk->vbus);
423 regulator_disable(mtk->vusb33);
424 }
425
xhci_mtk_quirks(struct device * dev,struct xhci_hcd * xhci)426 static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci)
427 {
428 struct usb_hcd *hcd = xhci_to_hcd(xhci);
429 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
430
431 /*
432 * As of now platform drivers don't provide MSI support so we ensure
433 * here that the generic code does not try to make a pci_dev from our
434 * dev struct in order to setup MSI
435 */
436 xhci->quirks |= XHCI_PLAT;
437 xhci->quirks |= XHCI_MTK_HOST;
438 /*
439 * MTK host controller gives a spurious successful event after a
440 * short transfer. Ignore it.
441 */
442 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
443 if (mtk->lpm_support)
444 xhci->quirks |= XHCI_LPM_SUPPORT;
445 if (mtk->u2_lpm_disable)
446 xhci->quirks |= XHCI_HW_LPM_DISABLE;
447
448 /*
449 * MTK xHCI 0.96: PSA is 1 by default even if doesn't support stream,
450 * and it's 3 when support it.
451 */
452 if (xhci->hci_version < 0x100 && HCC_MAX_PSA(xhci->hcc_params) == 4)
453 xhci->quirks |= XHCI_BROKEN_STREAMS;
454 }
455
456 /* called during probe() after chip reset completes */
xhci_mtk_setup(struct usb_hcd * hcd)457 static int xhci_mtk_setup(struct usb_hcd *hcd)
458 {
459 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
460 int ret;
461
462 if (usb_hcd_is_primary_hcd(hcd)) {
463 ret = xhci_mtk_ssusb_config(mtk);
464 if (ret)
465 return ret;
466
467 xhci_mtk_init_quirk(mtk);
468 }
469
470 ret = xhci_gen_setup(hcd, xhci_mtk_quirks);
471 if (ret)
472 return ret;
473
474 if (usb_hcd_is_primary_hcd(hcd)) {
475 ret = xhci_mtk_sch_init(mtk);
476 if (ret)
477 return ret;
478 }
479
480 return ret;
481 }
482
483 static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = {
484 .reset = xhci_mtk_setup,
485 .add_endpoint = xhci_mtk_add_ep,
486 .drop_endpoint = xhci_mtk_drop_ep,
487 .check_bandwidth = xhci_mtk_check_bandwidth,
488 .reset_bandwidth = xhci_mtk_reset_bandwidth,
489 };
490
491 static struct hc_driver __read_mostly xhci_mtk_hc_driver;
492
xhci_mtk_probe(struct platform_device * pdev)493 static int xhci_mtk_probe(struct platform_device *pdev)
494 {
495 struct device *dev = &pdev->dev;
496 struct device_node *node = dev->of_node;
497 struct xhci_hcd_mtk *mtk;
498 const struct hc_driver *driver;
499 struct xhci_hcd *xhci;
500 struct resource *res;
501 struct usb_hcd *hcd;
502 int ret = -ENODEV;
503 int wakeup_irq;
504 int irq;
505
506 if (usb_disabled())
507 return -ENODEV;
508
509 driver = &xhci_mtk_hc_driver;
510 mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
511 if (!mtk)
512 return -ENOMEM;
513
514 mtk->dev = dev;
515 mtk->vbus = devm_regulator_get(dev, "vbus");
516 if (IS_ERR(mtk->vbus)) {
517 dev_err(dev, "fail to get vbus\n");
518 return PTR_ERR(mtk->vbus);
519 }
520
521 mtk->vusb33 = devm_regulator_get(dev, "vusb33");
522 if (IS_ERR(mtk->vusb33)) {
523 dev_err(dev, "fail to get vusb33\n");
524 return PTR_ERR(mtk->vusb33);
525 }
526
527 ret = xhci_mtk_clks_get(mtk);
528 if (ret)
529 return ret;
530
531 irq = platform_get_irq_byname_optional(pdev, "host");
532 if (irq < 0) {
533 if (irq == -EPROBE_DEFER)
534 return irq;
535
536 /* for backward compatibility */
537 irq = platform_get_irq(pdev, 0);
538 if (irq < 0)
539 return irq;
540 }
541
542 wakeup_irq = platform_get_irq_byname_optional(pdev, "wakeup");
543 if (wakeup_irq == -EPROBE_DEFER)
544 return wakeup_irq;
545
546 mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
547 mtk->u2_lpm_disable = of_property_read_bool(node, "usb2-lpm-disable");
548 /* optional property, ignore the error if it does not exist */
549 of_property_read_u32(node, "mediatek,u3p-dis-msk",
550 &mtk->u3p_dis_msk);
551 of_property_read_u32(node, "mediatek,u2p-dis-msk",
552 &mtk->u2p_dis_msk);
553
554 of_property_read_u32(node, "rx-fifo-depth", &mtk->rxfifo_depth);
555
556 ret = usb_wakeup_of_property_parse(mtk, node);
557 if (ret) {
558 dev_err(dev, "failed to parse uwk property\n");
559 return ret;
560 }
561
562 pm_runtime_set_active(dev);
563 pm_runtime_use_autosuspend(dev);
564 pm_runtime_set_autosuspend_delay(dev, 4000);
565 pm_runtime_enable(dev);
566 pm_runtime_get_sync(dev);
567
568 ret = xhci_mtk_ldos_enable(mtk);
569 if (ret)
570 goto disable_pm;
571
572 ret = clk_bulk_prepare_enable(BULK_CLKS_NUM, mtk->clks);
573 if (ret)
574 goto disable_ldos;
575
576 hcd = usb_create_hcd(driver, dev, dev_name(dev));
577 if (!hcd) {
578 ret = -ENOMEM;
579 goto disable_clk;
580 }
581
582 /*
583 * USB 2.0 roothub is stored in the platform_device.
584 * Swap it with mtk HCD.
585 */
586 mtk->hcd = platform_get_drvdata(pdev);
587 platform_set_drvdata(pdev, mtk);
588
589 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac");
590 hcd->regs = devm_ioremap_resource(dev, res);
591 if (IS_ERR(hcd->regs)) {
592 ret = PTR_ERR(hcd->regs);
593 goto put_usb2_hcd;
594 }
595 hcd->rsrc_start = res->start;
596 hcd->rsrc_len = resource_size(res);
597
598 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
599 if (res) { /* ippc register is optional */
600 mtk->ippc_regs = devm_ioremap_resource(dev, res);
601 if (IS_ERR(mtk->ippc_regs)) {
602 ret = PTR_ERR(mtk->ippc_regs);
603 goto put_usb2_hcd;
604 }
605 mtk->has_ippc = true;
606 }
607
608 device_init_wakeup(dev, true);
609 dma_set_max_seg_size(dev, UINT_MAX);
610
611 xhci = hcd_to_xhci(hcd);
612 xhci->main_hcd = hcd;
613
614 /*
615 * imod_interval is the interrupt moderation value in nanoseconds.
616 * The increment interval is 8 times as much as that defined in
617 * the xHCI spec on MTK's controller.
618 */
619 xhci->imod_interval = 5000;
620 device_property_read_u32(dev, "imod-interval-ns", &xhci->imod_interval);
621
622 xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
623 dev_name(dev), hcd);
624 if (!xhci->shared_hcd) {
625 ret = -ENOMEM;
626 goto disable_device_wakeup;
627 }
628
629 ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
630 if (ret)
631 goto put_usb3_hcd;
632
633 if (HCC_MAX_PSA(xhci->hcc_params) >= 4 &&
634 !(xhci->quirks & XHCI_BROKEN_STREAMS))
635 xhci->shared_hcd->can_do_streams = 1;
636
637 ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
638 if (ret)
639 goto dealloc_usb2_hcd;
640
641 if (wakeup_irq > 0) {
642 ret = dev_pm_set_dedicated_wake_irq(dev, wakeup_irq);
643 if (ret) {
644 dev_err(dev, "set wakeup irq %d failed\n", wakeup_irq);
645 goto dealloc_usb3_hcd;
646 }
647 dev_info(dev, "wakeup irq %d\n", wakeup_irq);
648 }
649
650 device_enable_async_suspend(dev);
651 pm_runtime_mark_last_busy(dev);
652 pm_runtime_put_autosuspend(dev);
653 pm_runtime_forbid(dev);
654
655 return 0;
656
657 dealloc_usb3_hcd:
658 usb_remove_hcd(xhci->shared_hcd);
659
660 dealloc_usb2_hcd:
661 usb_remove_hcd(hcd);
662
663 put_usb3_hcd:
664 xhci_mtk_sch_exit(mtk);
665 usb_put_hcd(xhci->shared_hcd);
666
667 disable_device_wakeup:
668 device_init_wakeup(dev, false);
669
670 put_usb2_hcd:
671 usb_put_hcd(hcd);
672
673 disable_clk:
674 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
675
676 disable_ldos:
677 xhci_mtk_ldos_disable(mtk);
678
679 disable_pm:
680 pm_runtime_put_noidle(dev);
681 pm_runtime_disable(dev);
682 return ret;
683 }
684
xhci_mtk_remove(struct platform_device * pdev)685 static int xhci_mtk_remove(struct platform_device *pdev)
686 {
687 struct xhci_hcd_mtk *mtk = platform_get_drvdata(pdev);
688 struct usb_hcd *hcd = mtk->hcd;
689 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
690 struct usb_hcd *shared_hcd = xhci->shared_hcd;
691 struct device *dev = &pdev->dev;
692
693 pm_runtime_get_sync(dev);
694 xhci->xhc_state |= XHCI_STATE_REMOVING;
695 dev_pm_clear_wake_irq(dev);
696 device_init_wakeup(dev, false);
697
698 usb_remove_hcd(shared_hcd);
699 xhci->shared_hcd = NULL;
700 usb_remove_hcd(hcd);
701 usb_put_hcd(shared_hcd);
702 usb_put_hcd(hcd);
703 xhci_mtk_sch_exit(mtk);
704 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
705 xhci_mtk_ldos_disable(mtk);
706
707 pm_runtime_disable(dev);
708 pm_runtime_put_noidle(dev);
709 pm_runtime_set_suspended(dev);
710
711 return 0;
712 }
713
xhci_mtk_suspend(struct device * dev)714 static int __maybe_unused xhci_mtk_suspend(struct device *dev)
715 {
716 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
717 struct usb_hcd *hcd = mtk->hcd;
718 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
719 int ret;
720
721 xhci_dbg(xhci, "%s: stop port polling\n", __func__);
722 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
723 del_timer_sync(&hcd->rh_timer);
724 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
725 del_timer_sync(&xhci->shared_hcd->rh_timer);
726
727 ret = xhci_mtk_host_disable(mtk);
728 if (ret)
729 goto restart_poll_rh;
730
731 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
732 usb_wakeup_set(mtk, true);
733 return 0;
734
735 restart_poll_rh:
736 xhci_dbg(xhci, "%s: restart port polling\n", __func__);
737 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
738 usb_hcd_poll_rh_status(xhci->shared_hcd);
739 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
740 usb_hcd_poll_rh_status(hcd);
741 return ret;
742 }
743
xhci_mtk_resume(struct device * dev)744 static int __maybe_unused xhci_mtk_resume(struct device *dev)
745 {
746 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
747 struct usb_hcd *hcd = mtk->hcd;
748 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
749 int ret;
750
751 usb_wakeup_set(mtk, false);
752 ret = clk_bulk_prepare_enable(BULK_CLKS_NUM, mtk->clks);
753 if (ret)
754 goto enable_wakeup;
755
756 ret = xhci_mtk_host_enable(mtk);
757 if (ret)
758 goto disable_clks;
759
760 xhci_dbg(xhci, "%s: restart port polling\n", __func__);
761 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
762 usb_hcd_poll_rh_status(xhci->shared_hcd);
763 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
764 usb_hcd_poll_rh_status(hcd);
765 return 0;
766
767 disable_clks:
768 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
769 enable_wakeup:
770 usb_wakeup_set(mtk, true);
771 return ret;
772 }
773
xhci_mtk_runtime_suspend(struct device * dev)774 static int __maybe_unused xhci_mtk_runtime_suspend(struct device *dev)
775 {
776 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
777 struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd);
778 int ret = 0;
779
780 if (xhci->xhc_state)
781 return -ESHUTDOWN;
782
783 if (device_may_wakeup(dev))
784 ret = xhci_mtk_suspend(dev);
785
786 /* -EBUSY: let PM automatically reschedule another autosuspend */
787 return ret ? -EBUSY : 0;
788 }
789
xhci_mtk_runtime_resume(struct device * dev)790 static int __maybe_unused xhci_mtk_runtime_resume(struct device *dev)
791 {
792 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
793 struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd);
794 int ret = 0;
795
796 if (xhci->xhc_state)
797 return -ESHUTDOWN;
798
799 if (device_may_wakeup(dev))
800 ret = xhci_mtk_resume(dev);
801
802 return ret;
803 }
804
805 static const struct dev_pm_ops xhci_mtk_pm_ops = {
806 SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume)
807 SET_RUNTIME_PM_OPS(xhci_mtk_runtime_suspend,
808 xhci_mtk_runtime_resume, NULL)
809 };
810
811 #define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL)
812
813 static const struct of_device_id mtk_xhci_of_match[] = {
814 { .compatible = "mediatek,mt8173-xhci"},
815 { .compatible = "mediatek,mt8195-xhci"},
816 { .compatible = "mediatek,mtk-xhci"},
817 { },
818 };
819 MODULE_DEVICE_TABLE(of, mtk_xhci_of_match);
820
821 static struct platform_driver mtk_xhci_driver = {
822 .probe = xhci_mtk_probe,
823 .remove = xhci_mtk_remove,
824 .driver = {
825 .name = "xhci-mtk",
826 .pm = DEV_PM_OPS,
827 .of_match_table = mtk_xhci_of_match,
828 },
829 };
830
xhci_mtk_init(void)831 static int __init xhci_mtk_init(void)
832 {
833 xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides);
834 return platform_driver_register(&mtk_xhci_driver);
835 }
836 module_init(xhci_mtk_init);
837
xhci_mtk_exit(void)838 static void __exit xhci_mtk_exit(void)
839 {
840 platform_driver_unregister(&mtk_xhci_driver);
841 }
842 module_exit(xhci_mtk_exit);
843
844 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
845 MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
846 MODULE_LICENSE("GPL v2");
847