1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for the NXP ISP1760 chip
4 *
5 * However, the code might contain some bugs. What doesn't work for sure is:
6 * - ISO
7 * - OTG
8 e The interrupt line is configured as active low, level.
9 *
10 * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
11 *
12 * (c) 2011 Arvid Brodin <arvid.brodin@enea.com>
13 *
14 * Copyright 2021 Linaro, Rui Miguel Silva <rui.silva@linaro.org>
15 *
16 */
17 #include <linux/gpio/consumer.h>
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/slab.h>
21 #include <linux/list.h>
22 #include <linux/usb.h>
23 #include <linux/usb/hcd.h>
24 #include <linux/debugfs.h>
25 #include <linux/uaccess.h>
26 #include <linux/io.h>
27 #include <linux/iopoll.h>
28 #include <linux/mm.h>
29 #include <linux/timer.h>
30 #include <asm/unaligned.h>
31 #include <asm/cacheflush.h>
32
33 #include "isp1760-core.h"
34 #include "isp1760-hcd.h"
35 #include "isp1760-regs.h"
36
37 static struct kmem_cache *qtd_cachep;
38 static struct kmem_cache *qh_cachep;
39 static struct kmem_cache *urb_listitem_cachep;
40
41 typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh,
42 struct isp1760_qtd *qtd);
43
hcd_to_priv(struct usb_hcd * hcd)44 static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
45 {
46 return *(struct isp1760_hcd **)hcd->hcd_priv;
47 }
48
49 #define dw_to_le32(x) (cpu_to_le32((__force u32)x))
50 #define le32_to_dw(x) ((__force __dw)(le32_to_cpu(x)))
51
52 /* urb state*/
53 #define DELETE_URB (0x0008)
54 #define NO_TRANSFER_ACTIVE (0xffffffff)
55
56 /* Philips Proprietary Transfer Descriptor (PTD) */
57 typedef __u32 __bitwise __dw;
58 struct ptd {
59 __dw dw0;
60 __dw dw1;
61 __dw dw2;
62 __dw dw3;
63 __dw dw4;
64 __dw dw5;
65 __dw dw6;
66 __dw dw7;
67 };
68
69 struct ptd_le32 {
70 __le32 dw0;
71 __le32 dw1;
72 __le32 dw2;
73 __le32 dw3;
74 __le32 dw4;
75 __le32 dw5;
76 __le32 dw6;
77 __le32 dw7;
78 };
79
80 #define PTD_OFFSET 0x0400
81 #define ISO_PTD_OFFSET 0x0400
82 #define INT_PTD_OFFSET 0x0800
83 #define ATL_PTD_OFFSET 0x0c00
84 #define PAYLOAD_OFFSET 0x1000
85
86 #define ISP_BANK_0 0x00
87 #define ISP_BANK_1 0x01
88 #define ISP_BANK_2 0x02
89 #define ISP_BANK_3 0x03
90
91 #define TO_DW(x) ((__force __dw)x)
92 #define TO_U32(x) ((__force u32)x)
93
94 /* ATL */
95 /* DW0 */
96 #define DW0_VALID_BIT TO_DW(1)
97 #define FROM_DW0_VALID(x) (TO_U32(x) & 0x01)
98 #define TO_DW0_LENGTH(x) TO_DW((((u32)x) << 3))
99 #define TO_DW0_MAXPACKET(x) TO_DW((((u32)x) << 18))
100 #define TO_DW0_MULTI(x) TO_DW((((u32)x) << 29))
101 #define TO_DW0_ENDPOINT(x) TO_DW((((u32)x) << 31))
102 /* DW1 */
103 #define TO_DW1_DEVICE_ADDR(x) TO_DW((((u32)x) << 3))
104 #define TO_DW1_PID_TOKEN(x) TO_DW((((u32)x) << 10))
105 #define DW1_TRANS_BULK TO_DW(((u32)2 << 12))
106 #define DW1_TRANS_INT TO_DW(((u32)3 << 12))
107 #define DW1_TRANS_SPLIT TO_DW(((u32)1 << 14))
108 #define DW1_SE_USB_LOSPEED TO_DW(((u32)2 << 16))
109 #define TO_DW1_PORT_NUM(x) TO_DW((((u32)x) << 18))
110 #define TO_DW1_HUB_NUM(x) TO_DW((((u32)x) << 25))
111 /* DW2 */
112 #define TO_DW2_DATA_START_ADDR(x) TO_DW((((u32)x) << 8))
113 #define TO_DW2_RL(x) TO_DW(((x) << 25))
114 #define FROM_DW2_RL(x) ((TO_U32(x) >> 25) & 0xf)
115 /* DW3 */
116 #define FROM_DW3_NRBYTESTRANSFERRED(x) TO_U32((x) & 0x3fff)
117 #define FROM_DW3_SCS_NRBYTESTRANSFERRED(x) TO_U32((x) & 0x07ff)
118 #define TO_DW3_NAKCOUNT(x) TO_DW(((x) << 19))
119 #define FROM_DW3_NAKCOUNT(x) ((TO_U32(x) >> 19) & 0xf)
120 #define TO_DW3_CERR(x) TO_DW(((x) << 23))
121 #define FROM_DW3_CERR(x) ((TO_U32(x) >> 23) & 0x3)
122 #define TO_DW3_DATA_TOGGLE(x) TO_DW(((x) << 25))
123 #define FROM_DW3_DATA_TOGGLE(x) ((TO_U32(x) >> 25) & 0x1)
124 #define TO_DW3_PING(x) TO_DW(((x) << 26))
125 #define FROM_DW3_PING(x) ((TO_U32(x) >> 26) & 0x1)
126 #define DW3_ERROR_BIT TO_DW((1 << 28))
127 #define DW3_BABBLE_BIT TO_DW((1 << 29))
128 #define DW3_HALT_BIT TO_DW((1 << 30))
129 #define DW3_ACTIVE_BIT TO_DW((1 << 31))
130 #define FROM_DW3_ACTIVE(x) ((TO_U32(x) >> 31) & 0x01)
131
132 #define INT_UNDERRUN (1 << 2)
133 #define INT_BABBLE (1 << 1)
134 #define INT_EXACT (1 << 0)
135
136 #define SETUP_PID (2)
137 #define IN_PID (1)
138 #define OUT_PID (0)
139
140 /* Errata 1 */
141 #define RL_COUNTER (0)
142 #define NAK_COUNTER (0)
143 #define ERR_COUNTER (3)
144
145 struct isp1760_qtd {
146 u8 packet_type;
147 void *data_buffer;
148 u32 payload_addr;
149
150 /* the rest is HCD-private */
151 struct list_head qtd_list;
152 struct urb *urb;
153 size_t length;
154 size_t actual_length;
155
156 /* QTD_ENQUEUED: waiting for transfer (inactive) */
157 /* QTD_PAYLOAD_ALLOC: chip mem has been allocated for payload */
158 /* QTD_XFER_STARTED: valid ptd has been written to isp176x - only
159 interrupt handler may touch this qtd! */
160 /* QTD_XFER_COMPLETE: payload has been transferred successfully */
161 /* QTD_RETIRE: transfer error/abort qtd */
162 #define QTD_ENQUEUED 0
163 #define QTD_PAYLOAD_ALLOC 1
164 #define QTD_XFER_STARTED 2
165 #define QTD_XFER_COMPLETE 3
166 #define QTD_RETIRE 4
167 u32 status;
168 };
169
170 /* Queue head, one for each active endpoint */
171 struct isp1760_qh {
172 struct list_head qh_list;
173 struct list_head qtd_list;
174 u32 toggle;
175 u32 ping;
176 int slot;
177 int tt_buffer_dirty; /* See USB2.0 spec section 11.17.5 */
178 };
179
180 struct urb_listitem {
181 struct list_head urb_list;
182 struct urb *urb;
183 };
184
185 static const u32 isp176x_hc_portsc1_fields[] = {
186 [PORT_OWNER] = BIT(13),
187 [PORT_POWER] = BIT(12),
188 [PORT_LSTATUS] = BIT(10),
189 [PORT_RESET] = BIT(8),
190 [PORT_SUSPEND] = BIT(7),
191 [PORT_RESUME] = BIT(6),
192 [PORT_PE] = BIT(2),
193 [PORT_CSC] = BIT(1),
194 [PORT_CONNECT] = BIT(0),
195 };
196
197 /*
198 * Access functions for isp176x registers regmap fields
199 */
isp1760_hcd_read(struct usb_hcd * hcd,u32 field)200 static u32 isp1760_hcd_read(struct usb_hcd *hcd, u32 field)
201 {
202 struct isp1760_hcd *priv = hcd_to_priv(hcd);
203
204 return isp1760_field_read(priv->fields, field);
205 }
206
207 /*
208 * We need, in isp176x, to write directly the values to the portsc1
209 * register so it will make the other values to trigger.
210 */
isp1760_hcd_portsc1_set_clear(struct isp1760_hcd * priv,u32 field,u32 val)211 static void isp1760_hcd_portsc1_set_clear(struct isp1760_hcd *priv, u32 field,
212 u32 val)
213 {
214 u32 bit = isp176x_hc_portsc1_fields[field];
215 u16 portsc1_reg = priv->is_isp1763 ? ISP1763_HC_PORTSC1 :
216 ISP176x_HC_PORTSC1;
217 u32 port_status = readl(priv->base + portsc1_reg);
218
219 if (val)
220 writel(port_status | bit, priv->base + portsc1_reg);
221 else
222 writel(port_status & ~bit, priv->base + portsc1_reg);
223 }
224
isp1760_hcd_write(struct usb_hcd * hcd,u32 field,u32 val)225 static void isp1760_hcd_write(struct usb_hcd *hcd, u32 field, u32 val)
226 {
227 struct isp1760_hcd *priv = hcd_to_priv(hcd);
228
229 if (unlikely((field >= PORT_OWNER && field <= PORT_CONNECT)))
230 return isp1760_hcd_portsc1_set_clear(priv, field, val);
231
232 isp1760_field_write(priv->fields, field, val);
233 }
234
isp1760_hcd_set(struct usb_hcd * hcd,u32 field)235 static void isp1760_hcd_set(struct usb_hcd *hcd, u32 field)
236 {
237 isp1760_hcd_write(hcd, field, 0xFFFFFFFF);
238 }
239
isp1760_hcd_clear(struct usb_hcd * hcd,u32 field)240 static void isp1760_hcd_clear(struct usb_hcd *hcd, u32 field)
241 {
242 isp1760_hcd_write(hcd, field, 0);
243 }
244
isp1760_hcd_set_and_wait(struct usb_hcd * hcd,u32 field,u32 timeout_us)245 static int isp1760_hcd_set_and_wait(struct usb_hcd *hcd, u32 field,
246 u32 timeout_us)
247 {
248 struct isp1760_hcd *priv = hcd_to_priv(hcd);
249 u32 val;
250
251 isp1760_hcd_set(hcd, field);
252
253 return regmap_field_read_poll_timeout(priv->fields[field], val,
254 val, 0, timeout_us);
255 }
256
isp1760_hcd_set_and_wait_swap(struct usb_hcd * hcd,u32 field,u32 timeout_us)257 static int isp1760_hcd_set_and_wait_swap(struct usb_hcd *hcd, u32 field,
258 u32 timeout_us)
259 {
260 struct isp1760_hcd *priv = hcd_to_priv(hcd);
261 u32 val;
262
263 isp1760_hcd_set(hcd, field);
264
265 return regmap_field_read_poll_timeout(priv->fields[field], val,
266 !val, 0, timeout_us);
267 }
268
isp1760_hcd_clear_and_wait(struct usb_hcd * hcd,u32 field,u32 timeout_us)269 static int isp1760_hcd_clear_and_wait(struct usb_hcd *hcd, u32 field,
270 u32 timeout_us)
271 {
272 struct isp1760_hcd *priv = hcd_to_priv(hcd);
273 u32 val;
274
275 isp1760_hcd_clear(hcd, field);
276
277 return regmap_field_read_poll_timeout(priv->fields[field], val,
278 !val, 0, timeout_us);
279 }
280
isp1760_hcd_is_set(struct usb_hcd * hcd,u32 field)281 static bool isp1760_hcd_is_set(struct usb_hcd *hcd, u32 field)
282 {
283 return !!isp1760_hcd_read(hcd, field);
284 }
285
isp1760_hcd_ppc_is_set(struct usb_hcd * hcd)286 static bool isp1760_hcd_ppc_is_set(struct usb_hcd *hcd)
287 {
288 struct isp1760_hcd *priv = hcd_to_priv(hcd);
289
290 if (priv->is_isp1763)
291 return true;
292
293 return isp1760_hcd_is_set(hcd, HCS_PPC);
294 }
295
isp1760_hcd_n_ports(struct usb_hcd * hcd)296 static u32 isp1760_hcd_n_ports(struct usb_hcd *hcd)
297 {
298 struct isp1760_hcd *priv = hcd_to_priv(hcd);
299
300 if (priv->is_isp1763)
301 return 1;
302
303 return isp1760_hcd_read(hcd, HCS_N_PORTS);
304 }
305
306 /*
307 * Access functions for isp176x memory (offset >= 0x0400).
308 *
309 * bank_reads8() reads memory locations prefetched by an earlier write to
310 * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi-
311 * bank optimizations, you should use the more generic mem_read() below.
312 *
313 * For access to ptd memory, use the specialized ptd_read() and ptd_write()
314 * below.
315 *
316 * These functions copy via MMIO data to/from the device. memcpy_{to|from}io()
317 * doesn't quite work because some people have to enforce 32-bit access
318 */
bank_reads8(void __iomem * src_base,u32 src_offset,u32 bank_addr,__u32 * dst,u32 bytes)319 static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr,
320 __u32 *dst, u32 bytes)
321 {
322 __u32 __iomem *src;
323 u32 val;
324 __u8 *src_byteptr;
325 __u8 *dst_byteptr;
326
327 src = src_base + (bank_addr | src_offset);
328
329 if (src_offset < PAYLOAD_OFFSET) {
330 while (bytes >= 4) {
331 *dst = readl_relaxed(src);
332 bytes -= 4;
333 src++;
334 dst++;
335 }
336 } else {
337 while (bytes >= 4) {
338 *dst = __raw_readl(src);
339 bytes -= 4;
340 src++;
341 dst++;
342 }
343 }
344
345 if (!bytes)
346 return;
347
348 /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
349 * allocated.
350 */
351 if (src_offset < PAYLOAD_OFFSET)
352 val = readl_relaxed(src);
353 else
354 val = __raw_readl(src);
355
356 dst_byteptr = (void *) dst;
357 src_byteptr = (void *) &val;
358 while (bytes > 0) {
359 *dst_byteptr = *src_byteptr;
360 dst_byteptr++;
361 src_byteptr++;
362 bytes--;
363 }
364 }
365
isp1760_mem_read(struct usb_hcd * hcd,u32 src_offset,void * dst,u32 bytes)366 static void isp1760_mem_read(struct usb_hcd *hcd, u32 src_offset, void *dst,
367 u32 bytes)
368 {
369 struct isp1760_hcd *priv = hcd_to_priv(hcd);
370
371 isp1760_reg_write(priv->regs, ISP176x_HC_MEMORY, src_offset);
372 ndelay(100);
373
374 bank_reads8(priv->base, src_offset, ISP_BANK_0, dst, bytes);
375 }
376
377 /*
378 * ISP1763 does not have the banks direct host controller memory access,
379 * needs to use the HC_DATA register. Add data read/write according to this,
380 * and also adjust 16bit access.
381 */
isp1763_mem_read(struct usb_hcd * hcd,u16 srcaddr,u16 * dstptr,u32 bytes)382 static void isp1763_mem_read(struct usb_hcd *hcd, u16 srcaddr,
383 u16 *dstptr, u32 bytes)
384 {
385 struct isp1760_hcd *priv = hcd_to_priv(hcd);
386
387 /* Write the starting device address to the hcd memory register */
388 isp1760_reg_write(priv->regs, ISP1763_HC_MEMORY, srcaddr);
389 ndelay(100); /* Delay between consecutive access */
390
391 /* As long there are at least 16-bit to read ... */
392 while (bytes >= 2) {
393 *dstptr = __raw_readw(priv->base + ISP1763_HC_DATA);
394 bytes -= 2;
395 dstptr++;
396 }
397
398 /* If there are no more bytes to read, return */
399 if (bytes <= 0)
400 return;
401
402 *((u8 *)dstptr) = (u8)(readw(priv->base + ISP1763_HC_DATA) & 0xFF);
403 }
404
mem_read(struct usb_hcd * hcd,u32 src_offset,__u32 * dst,u32 bytes)405 static void mem_read(struct usb_hcd *hcd, u32 src_offset, __u32 *dst,
406 u32 bytes)
407 {
408 struct isp1760_hcd *priv = hcd_to_priv(hcd);
409
410 if (!priv->is_isp1763)
411 return isp1760_mem_read(hcd, src_offset, (u16 *)dst, bytes);
412
413 isp1763_mem_read(hcd, (u16)src_offset, (u16 *)dst, bytes);
414 }
415
isp1760_mem_write(void __iomem * dst_base,u32 dst_offset,__u32 const * src,u32 bytes)416 static void isp1760_mem_write(void __iomem *dst_base, u32 dst_offset,
417 __u32 const *src, u32 bytes)
418 {
419 __u32 __iomem *dst;
420
421 dst = dst_base + dst_offset;
422
423 if (dst_offset < PAYLOAD_OFFSET) {
424 while (bytes >= 4) {
425 writel_relaxed(*src, dst);
426 bytes -= 4;
427 src++;
428 dst++;
429 }
430 } else {
431 while (bytes >= 4) {
432 __raw_writel(*src, dst);
433 bytes -= 4;
434 src++;
435 dst++;
436 }
437 }
438
439 if (!bytes)
440 return;
441 /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the
442 * extra bytes should not be read by the HW.
443 */
444
445 if (dst_offset < PAYLOAD_OFFSET)
446 writel_relaxed(*src, dst);
447 else
448 __raw_writel(*src, dst);
449 }
450
isp1763_mem_write(struct usb_hcd * hcd,u16 dstaddr,u16 * src,u32 bytes)451 static void isp1763_mem_write(struct usb_hcd *hcd, u16 dstaddr, u16 *src,
452 u32 bytes)
453 {
454 struct isp1760_hcd *priv = hcd_to_priv(hcd);
455
456 /* Write the starting device address to the hcd memory register */
457 isp1760_reg_write(priv->regs, ISP1763_HC_MEMORY, dstaddr);
458 ndelay(100); /* Delay between consecutive access */
459
460 while (bytes >= 2) {
461 /* Get and write the data; then adjust the data ptr and len */
462 __raw_writew(*src, priv->base + ISP1763_HC_DATA);
463 bytes -= 2;
464 src++;
465 }
466
467 /* If there are no more bytes to process, return */
468 if (bytes <= 0)
469 return;
470
471 /*
472 * The only way to get here is if there is a single byte left,
473 * get it and write it to the data reg;
474 */
475 writew(*((u8 *)src), priv->base + ISP1763_HC_DATA);
476 }
477
mem_write(struct usb_hcd * hcd,u32 dst_offset,__u32 * src,u32 bytes)478 static void mem_write(struct usb_hcd *hcd, u32 dst_offset, __u32 *src,
479 u32 bytes)
480 {
481 struct isp1760_hcd *priv = hcd_to_priv(hcd);
482
483 if (!priv->is_isp1763)
484 return isp1760_mem_write(priv->base, dst_offset, src, bytes);
485
486 isp1763_mem_write(hcd, dst_offset, (u16 *)src, bytes);
487 }
488
489 /*
490 * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET,
491 * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32.
492 */
isp1760_ptd_read(struct usb_hcd * hcd,u32 ptd_offset,u32 slot,struct ptd * ptd)493 static void isp1760_ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot,
494 struct ptd *ptd)
495 {
496 u16 src_offset = ptd_offset + slot * sizeof(*ptd);
497 struct isp1760_hcd *priv = hcd_to_priv(hcd);
498
499 isp1760_reg_write(priv->regs, ISP176x_HC_MEMORY, src_offset);
500 ndelay(90);
501
502 bank_reads8(priv->base, src_offset, ISP_BANK_0, (void *)ptd,
503 sizeof(*ptd));
504 }
505
isp1763_ptd_read(struct usb_hcd * hcd,u32 ptd_offset,u32 slot,struct ptd * ptd)506 static void isp1763_ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot,
507 struct ptd *ptd)
508 {
509 u16 src_offset = ptd_offset + slot * sizeof(*ptd);
510 struct ptd_le32 le32_ptd;
511
512 isp1763_mem_read(hcd, src_offset, (u16 *)&le32_ptd, sizeof(le32_ptd));
513 /* Normalize the data obtained */
514 ptd->dw0 = le32_to_dw(le32_ptd.dw0);
515 ptd->dw1 = le32_to_dw(le32_ptd.dw1);
516 ptd->dw2 = le32_to_dw(le32_ptd.dw2);
517 ptd->dw3 = le32_to_dw(le32_ptd.dw3);
518 ptd->dw4 = le32_to_dw(le32_ptd.dw4);
519 ptd->dw5 = le32_to_dw(le32_ptd.dw5);
520 ptd->dw6 = le32_to_dw(le32_ptd.dw6);
521 ptd->dw7 = le32_to_dw(le32_ptd.dw7);
522 }
523
ptd_read(struct usb_hcd * hcd,u32 ptd_offset,u32 slot,struct ptd * ptd)524 static void ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot,
525 struct ptd *ptd)
526 {
527 struct isp1760_hcd *priv = hcd_to_priv(hcd);
528
529 if (!priv->is_isp1763)
530 return isp1760_ptd_read(hcd, ptd_offset, slot, ptd);
531
532 isp1763_ptd_read(hcd, ptd_offset, slot, ptd);
533 }
534
isp1763_ptd_write(struct usb_hcd * hcd,u32 ptd_offset,u32 slot,struct ptd * cpu_ptd)535 static void isp1763_ptd_write(struct usb_hcd *hcd, u32 ptd_offset, u32 slot,
536 struct ptd *cpu_ptd)
537 {
538 u16 dst_offset = ptd_offset + slot * sizeof(*cpu_ptd);
539 struct ptd_le32 ptd;
540
541 ptd.dw0 = dw_to_le32(cpu_ptd->dw0);
542 ptd.dw1 = dw_to_le32(cpu_ptd->dw1);
543 ptd.dw2 = dw_to_le32(cpu_ptd->dw2);
544 ptd.dw3 = dw_to_le32(cpu_ptd->dw3);
545 ptd.dw4 = dw_to_le32(cpu_ptd->dw4);
546 ptd.dw5 = dw_to_le32(cpu_ptd->dw5);
547 ptd.dw6 = dw_to_le32(cpu_ptd->dw6);
548 ptd.dw7 = dw_to_le32(cpu_ptd->dw7);
549
550 isp1763_mem_write(hcd, dst_offset, (u16 *)&ptd.dw0,
551 8 * sizeof(ptd.dw0));
552 }
553
isp1760_ptd_write(void __iomem * base,u32 ptd_offset,u32 slot,struct ptd * ptd)554 static void isp1760_ptd_write(void __iomem *base, u32 ptd_offset, u32 slot,
555 struct ptd *ptd)
556 {
557 u32 dst_offset = ptd_offset + slot * sizeof(*ptd);
558
559 /*
560 * Make sure dw0 gets written last (after other dw's and after payload)
561 * since it contains the enable bit
562 */
563 isp1760_mem_write(base, dst_offset + sizeof(ptd->dw0),
564 (__force u32 *)&ptd->dw1, 7 * sizeof(ptd->dw1));
565 wmb();
566 isp1760_mem_write(base, dst_offset, (__force u32 *)&ptd->dw0,
567 sizeof(ptd->dw0));
568 }
569
ptd_write(struct usb_hcd * hcd,u32 ptd_offset,u32 slot,struct ptd * ptd)570 static void ptd_write(struct usb_hcd *hcd, u32 ptd_offset, u32 slot,
571 struct ptd *ptd)
572 {
573 struct isp1760_hcd *priv = hcd_to_priv(hcd);
574
575 if (!priv->is_isp1763)
576 return isp1760_ptd_write(priv->base, ptd_offset, slot, ptd);
577
578 isp1763_ptd_write(hcd, ptd_offset, slot, ptd);
579 }
580
581 /* memory management of the 60kb on the chip from 0x1000 to 0xffff */
init_memory(struct isp1760_hcd * priv)582 static void init_memory(struct isp1760_hcd *priv)
583 {
584 const struct isp1760_memory_layout *mem = priv->memory_layout;
585 int i, j, curr;
586 u32 payload_addr;
587
588 payload_addr = PAYLOAD_OFFSET;
589
590 for (i = 0, curr = 0; i < ARRAY_SIZE(mem->blocks); i++, curr += j) {
591 for (j = 0; j < mem->blocks[i]; j++) {
592 priv->memory_pool[curr + j].start = payload_addr;
593 priv->memory_pool[curr + j].size = mem->blocks_size[i];
594 priv->memory_pool[curr + j].free = 1;
595 payload_addr += priv->memory_pool[curr + j].size;
596 }
597 }
598
599 WARN_ON(payload_addr - priv->memory_pool[0].start >
600 mem->payload_area_size);
601 }
602
alloc_mem(struct usb_hcd * hcd,struct isp1760_qtd * qtd)603 static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
604 {
605 struct isp1760_hcd *priv = hcd_to_priv(hcd);
606 const struct isp1760_memory_layout *mem = priv->memory_layout;
607 int i;
608
609 WARN_ON(qtd->payload_addr);
610
611 if (!qtd->length)
612 return;
613
614 for (i = 0; i < mem->payload_blocks; i++) {
615 if (priv->memory_pool[i].size >= qtd->length &&
616 priv->memory_pool[i].free) {
617 priv->memory_pool[i].free = 0;
618 qtd->payload_addr = priv->memory_pool[i].start;
619 return;
620 }
621 }
622 }
623
free_mem(struct usb_hcd * hcd,struct isp1760_qtd * qtd)624 static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
625 {
626 struct isp1760_hcd *priv = hcd_to_priv(hcd);
627 const struct isp1760_memory_layout *mem = priv->memory_layout;
628 int i;
629
630 if (!qtd->payload_addr)
631 return;
632
633 for (i = 0; i < mem->payload_blocks; i++) {
634 if (priv->memory_pool[i].start == qtd->payload_addr) {
635 WARN_ON(priv->memory_pool[i].free);
636 priv->memory_pool[i].free = 1;
637 qtd->payload_addr = 0;
638 return;
639 }
640 }
641
642 dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n",
643 __func__, qtd->payload_addr);
644 WARN_ON(1);
645 qtd->payload_addr = 0;
646 }
647
648 /* reset a non-running (STS_HALT == 1) controller */
ehci_reset(struct usb_hcd * hcd)649 static int ehci_reset(struct usb_hcd *hcd)
650 {
651 struct isp1760_hcd *priv = hcd_to_priv(hcd);
652
653 hcd->state = HC_STATE_HALT;
654 priv->next_statechange = jiffies;
655
656 return isp1760_hcd_set_and_wait_swap(hcd, CMD_RESET, 250 * 1000);
657 }
658
qh_alloc(gfp_t flags)659 static struct isp1760_qh *qh_alloc(gfp_t flags)
660 {
661 struct isp1760_qh *qh;
662
663 qh = kmem_cache_zalloc(qh_cachep, flags);
664 if (!qh)
665 return NULL;
666
667 INIT_LIST_HEAD(&qh->qh_list);
668 INIT_LIST_HEAD(&qh->qtd_list);
669 qh->slot = -1;
670
671 return qh;
672 }
673
qh_free(struct isp1760_qh * qh)674 static void qh_free(struct isp1760_qh *qh)
675 {
676 WARN_ON(!list_empty(&qh->qtd_list));
677 WARN_ON(qh->slot > -1);
678 kmem_cache_free(qh_cachep, qh);
679 }
680
681 /* one-time init, only for memory state */
priv_init(struct usb_hcd * hcd)682 static int priv_init(struct usb_hcd *hcd)
683 {
684 struct isp1760_hcd *priv = hcd_to_priv(hcd);
685 u32 isoc_cache;
686 u32 isoc_thres;
687 int i;
688
689 spin_lock_init(&priv->lock);
690
691 for (i = 0; i < QH_END; i++)
692 INIT_LIST_HEAD(&priv->qh_list[i]);
693
694 /*
695 * hw default: 1K periodic list heads, one per frame.
696 * periodic_size can shrink by USBCMD update if hcc_params allows.
697 */
698 priv->periodic_size = DEFAULT_I_TDPS;
699
700 if (priv->is_isp1763) {
701 priv->i_thresh = 2;
702 return 0;
703 }
704
705 /* controllers may cache some of the periodic schedule ... */
706 isoc_cache = isp1760_hcd_read(hcd, HCC_ISOC_CACHE);
707 isoc_thres = isp1760_hcd_read(hcd, HCC_ISOC_THRES);
708
709 /* full frame cache */
710 if (isoc_cache)
711 priv->i_thresh = 8;
712 else /* N microframes cached */
713 priv->i_thresh = 2 + isoc_thres;
714
715 return 0;
716 }
717
isp1760_hc_setup(struct usb_hcd * hcd)718 static int isp1760_hc_setup(struct usb_hcd *hcd)
719 {
720 struct isp1760_hcd *priv = hcd_to_priv(hcd);
721 u32 atx_reset;
722 int result;
723 u32 scratch;
724 u32 pattern;
725
726 if (priv->is_isp1763)
727 pattern = 0xcafe;
728 else
729 pattern = 0xdeadcafe;
730
731 isp1760_hcd_write(hcd, HC_SCRATCH, pattern);
732
733 /*
734 * we do not care about the read value here we just want to
735 * change bus pattern.
736 */
737 isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH);
738 scratch = isp1760_hcd_read(hcd, HC_SCRATCH);
739 if (scratch != pattern) {
740 dev_err(hcd->self.controller, "Scratch test failed. 0x%08x\n",
741 scratch);
742 return -ENODEV;
743 }
744
745 /*
746 * The RESET_HC bit in the SW_RESET register is supposed to reset the
747 * host controller without touching the CPU interface registers, but at
748 * least on the ISP1761 it seems to behave as the RESET_ALL bit and
749 * reset the whole device. We thus can't use it here, so let's reset
750 * the host controller through the EHCI USB Command register. The device
751 * has been reset in core code anyway, so this shouldn't matter.
752 */
753 isp1760_hcd_clear(hcd, ISO_BUF_FILL);
754 isp1760_hcd_clear(hcd, INT_BUF_FILL);
755 isp1760_hcd_clear(hcd, ATL_BUF_FILL);
756
757 isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP);
758 isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP);
759 isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP);
760
761 result = ehci_reset(hcd);
762 if (result)
763 return result;
764
765 /* Step 11 passed */
766
767 /* ATL reset */
768 if (priv->is_isp1763)
769 atx_reset = SW_RESET_RESET_ATX;
770 else
771 atx_reset = ALL_ATX_RESET;
772
773 isp1760_hcd_set(hcd, atx_reset);
774 mdelay(10);
775 isp1760_hcd_clear(hcd, atx_reset);
776
777 if (priv->is_isp1763) {
778 isp1760_hcd_set(hcd, HW_OTG_DISABLE);
779 isp1760_hcd_set(hcd, HW_SW_SEL_HC_DC_CLEAR);
780 isp1760_hcd_set(hcd, HW_HC_2_DIS_CLEAR);
781 mdelay(10);
782
783 isp1760_hcd_set(hcd, HW_INTF_LOCK);
784 }
785
786 isp1760_hcd_set(hcd, HC_INT_IRQ_ENABLE);
787 isp1760_hcd_set(hcd, HC_ATL_IRQ_ENABLE);
788
789 return priv_init(hcd);
790 }
791
base_to_chip(u32 base)792 static u32 base_to_chip(u32 base)
793 {
794 return ((base - 0x400) >> 3);
795 }
796
last_qtd_of_urb(struct isp1760_qtd * qtd,struct isp1760_qh * qh)797 static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh)
798 {
799 struct urb *urb;
800
801 if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
802 return 1;
803
804 urb = qtd->urb;
805 qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list);
806 return (qtd->urb != urb);
807 }
808
809 /* magic numbers that can affect system performance */
810 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
811 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
812 #define EHCI_TUNE_RL_TT 0
813 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
814 #define EHCI_TUNE_MULT_TT 1
815 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
816
create_ptd_atl(struct isp1760_qh * qh,struct isp1760_qtd * qtd,struct ptd * ptd)817 static void create_ptd_atl(struct isp1760_qh *qh,
818 struct isp1760_qtd *qtd, struct ptd *ptd)
819 {
820 u32 maxpacket;
821 u32 multi;
822 u32 rl = RL_COUNTER;
823 u32 nak = NAK_COUNTER;
824
825 memset(ptd, 0, sizeof(*ptd));
826
827 /* according to 3.6.2, max packet len can not be > 0x400 */
828 maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe,
829 usb_pipeout(qtd->urb->pipe));
830 multi = 1 + ((maxpacket >> 11) & 0x3);
831 maxpacket &= 0x7ff;
832
833 /* DW0 */
834 ptd->dw0 = DW0_VALID_BIT;
835 ptd->dw0 |= TO_DW0_LENGTH(qtd->length);
836 ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket);
837 ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe));
838
839 /* DW1 */
840 ptd->dw1 = TO_DW((usb_pipeendpoint(qtd->urb->pipe) >> 1));
841 ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe));
842 ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type);
843
844 if (usb_pipebulk(qtd->urb->pipe))
845 ptd->dw1 |= DW1_TRANS_BULK;
846 else if (usb_pipeint(qtd->urb->pipe))
847 ptd->dw1 |= DW1_TRANS_INT;
848
849 if (qtd->urb->dev->speed != USB_SPEED_HIGH) {
850 /* split transaction */
851
852 ptd->dw1 |= DW1_TRANS_SPLIT;
853 if (qtd->urb->dev->speed == USB_SPEED_LOW)
854 ptd->dw1 |= DW1_SE_USB_LOSPEED;
855
856 ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport);
857 ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum);
858
859 /* SE bit for Split INT transfers */
860 if (usb_pipeint(qtd->urb->pipe) &&
861 (qtd->urb->dev->speed == USB_SPEED_LOW))
862 ptd->dw1 |= DW1_SE_USB_LOSPEED;
863
864 rl = 0;
865 nak = 0;
866 } else {
867 ptd->dw0 |= TO_DW0_MULTI(multi);
868 if (usb_pipecontrol(qtd->urb->pipe) ||
869 usb_pipebulk(qtd->urb->pipe))
870 ptd->dw3 |= TO_DW3_PING(qh->ping);
871 }
872 /* DW2 */
873 ptd->dw2 = 0;
874 ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr));
875 ptd->dw2 |= TO_DW2_RL(rl);
876
877 /* DW3 */
878 ptd->dw3 |= TO_DW3_NAKCOUNT(nak);
879 ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle);
880 if (usb_pipecontrol(qtd->urb->pipe)) {
881 if (qtd->data_buffer == qtd->urb->setup_packet)
882 ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1);
883 else if (last_qtd_of_urb(qtd, qh))
884 ptd->dw3 |= TO_DW3_DATA_TOGGLE(1);
885 }
886
887 ptd->dw3 |= DW3_ACTIVE_BIT;
888 /* Cerr */
889 ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER);
890 }
891
transform_add_int(struct isp1760_qh * qh,struct isp1760_qtd * qtd,struct ptd * ptd)892 static void transform_add_int(struct isp1760_qh *qh,
893 struct isp1760_qtd *qtd, struct ptd *ptd)
894 {
895 u32 usof;
896 u32 period;
897
898 /*
899 * Most of this is guessing. ISP1761 datasheet is quite unclear, and
900 * the algorithm from the original Philips driver code, which was
901 * pretty much used in this driver before as well, is quite horrendous
902 * and, i believe, incorrect. The code below follows the datasheet and
903 * USB2.0 spec as far as I can tell, and plug/unplug seems to be much
904 * more reliable this way (fingers crossed...).
905 */
906
907 if (qtd->urb->dev->speed == USB_SPEED_HIGH) {
908 /* urb->interval is in units of microframes (1/8 ms) */
909 period = qtd->urb->interval >> 3;
910
911 if (qtd->urb->interval > 4)
912 usof = 0x01; /* One bit set =>
913 interval 1 ms * uFrame-match */
914 else if (qtd->urb->interval > 2)
915 usof = 0x22; /* Two bits set => interval 1/2 ms */
916 else if (qtd->urb->interval > 1)
917 usof = 0x55; /* Four bits set => interval 1/4 ms */
918 else
919 usof = 0xff; /* All bits set => interval 1/8 ms */
920 } else {
921 /* urb->interval is in units of frames (1 ms) */
922 period = qtd->urb->interval;
923 usof = 0x0f; /* Execute Start Split on any of the
924 four first uFrames */
925
926 /*
927 * First 8 bits in dw5 is uSCS and "specifies which uSOF the
928 * complete split needs to be sent. Valid only for IN." Also,
929 * "All bits can be set to one for every transfer." (p 82,
930 * ISP1761 data sheet.) 0x1c is from Philips driver. Where did
931 * that number come from? 0xff seems to work fine...
932 */
933 /* ptd->dw5 = 0x1c; */
934 ptd->dw5 = TO_DW(0xff); /* Execute Complete Split on any uFrame */
935 }
936
937 period = period >> 1;/* Ensure equal or shorter period than requested */
938 period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */
939
940 ptd->dw2 |= TO_DW(period);
941 ptd->dw4 = TO_DW(usof);
942 }
943
create_ptd_int(struct isp1760_qh * qh,struct isp1760_qtd * qtd,struct ptd * ptd)944 static void create_ptd_int(struct isp1760_qh *qh,
945 struct isp1760_qtd *qtd, struct ptd *ptd)
946 {
947 create_ptd_atl(qh, qtd, ptd);
948 transform_add_int(qh, qtd, ptd);
949 }
950
isp1760_urb_done(struct usb_hcd * hcd,struct urb * urb)951 static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb)
952 __releases(priv->lock)
953 __acquires(priv->lock)
954 {
955 struct isp1760_hcd *priv = hcd_to_priv(hcd);
956
957 if (!urb->unlinked) {
958 if (urb->status == -EINPROGRESS)
959 urb->status = 0;
960 }
961
962 if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) {
963 void *ptr;
964 for (ptr = urb->transfer_buffer;
965 ptr < urb->transfer_buffer + urb->transfer_buffer_length;
966 ptr += PAGE_SIZE)
967 flush_dcache_page(virt_to_page(ptr));
968 }
969
970 /* complete() can reenter this HCD */
971 usb_hcd_unlink_urb_from_ep(hcd, urb);
972 spin_unlock(&priv->lock);
973 usb_hcd_giveback_urb(hcd, urb, urb->status);
974 spin_lock(&priv->lock);
975 }
976
qtd_alloc(gfp_t flags,struct urb * urb,u8 packet_type)977 static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb,
978 u8 packet_type)
979 {
980 struct isp1760_qtd *qtd;
981
982 qtd = kmem_cache_zalloc(qtd_cachep, flags);
983 if (!qtd)
984 return NULL;
985
986 INIT_LIST_HEAD(&qtd->qtd_list);
987 qtd->urb = urb;
988 qtd->packet_type = packet_type;
989 qtd->status = QTD_ENQUEUED;
990 qtd->actual_length = 0;
991
992 return qtd;
993 }
994
qtd_free(struct isp1760_qtd * qtd)995 static void qtd_free(struct isp1760_qtd *qtd)
996 {
997 WARN_ON(qtd->payload_addr);
998 kmem_cache_free(qtd_cachep, qtd);
999 }
1000
start_bus_transfer(struct usb_hcd * hcd,u32 ptd_offset,int slot,struct isp1760_slotinfo * slots,struct isp1760_qtd * qtd,struct isp1760_qh * qh,struct ptd * ptd)1001 static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot,
1002 struct isp1760_slotinfo *slots,
1003 struct isp1760_qtd *qtd, struct isp1760_qh *qh,
1004 struct ptd *ptd)
1005 {
1006 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1007 const struct isp1760_memory_layout *mem = priv->memory_layout;
1008 int skip_map;
1009
1010 WARN_ON((slot < 0) || (slot > mem->slot_num - 1));
1011 WARN_ON(qtd->length && !qtd->payload_addr);
1012 WARN_ON(slots[slot].qtd);
1013 WARN_ON(slots[slot].qh);
1014 WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC);
1015
1016 if (priv->is_isp1763)
1017 ndelay(100);
1018
1019 /* Make sure done map has not triggered from some unlinked transfer */
1020 if (ptd_offset == ATL_PTD_OFFSET) {
1021 skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP);
1022 isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP,
1023 skip_map | (1 << slot));
1024 priv->atl_done_map |= isp1760_hcd_read(hcd, HC_ATL_PTD_DONEMAP);
1025 priv->atl_done_map &= ~(1 << slot);
1026 } else {
1027 skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP);
1028 isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP,
1029 skip_map | (1 << slot));
1030 priv->int_done_map |= isp1760_hcd_read(hcd, HC_INT_PTD_DONEMAP);
1031 priv->int_done_map &= ~(1 << slot);
1032 }
1033
1034 skip_map &= ~(1 << slot);
1035 qh->slot = slot;
1036 qtd->status = QTD_XFER_STARTED;
1037 slots[slot].timestamp = jiffies;
1038 slots[slot].qtd = qtd;
1039 slots[slot].qh = qh;
1040 ptd_write(hcd, ptd_offset, slot, ptd);
1041
1042 if (ptd_offset == ATL_PTD_OFFSET)
1043 isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP, skip_map);
1044 else
1045 isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP, skip_map);
1046 }
1047
is_short_bulk(struct isp1760_qtd * qtd)1048 static int is_short_bulk(struct isp1760_qtd *qtd)
1049 {
1050 return (usb_pipebulk(qtd->urb->pipe) &&
1051 (qtd->actual_length < qtd->length));
1052 }
1053
collect_qtds(struct usb_hcd * hcd,struct isp1760_qh * qh,struct list_head * urb_list)1054 static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh,
1055 struct list_head *urb_list)
1056 {
1057 struct isp1760_qtd *qtd, *qtd_next;
1058 struct urb_listitem *urb_listitem;
1059 int last_qtd;
1060
1061 list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) {
1062 if (qtd->status < QTD_XFER_COMPLETE)
1063 break;
1064
1065 last_qtd = last_qtd_of_urb(qtd, qh);
1066
1067 if ((!last_qtd) && (qtd->status == QTD_RETIRE))
1068 qtd_next->status = QTD_RETIRE;
1069
1070 if (qtd->status == QTD_XFER_COMPLETE) {
1071 if (qtd->actual_length) {
1072 switch (qtd->packet_type) {
1073 case IN_PID:
1074 mem_read(hcd, qtd->payload_addr,
1075 qtd->data_buffer,
1076 qtd->actual_length);
1077 fallthrough;
1078 case OUT_PID:
1079 qtd->urb->actual_length +=
1080 qtd->actual_length;
1081 fallthrough;
1082 case SETUP_PID:
1083 break;
1084 }
1085 }
1086
1087 if (is_short_bulk(qtd)) {
1088 if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK)
1089 qtd->urb->status = -EREMOTEIO;
1090 if (!last_qtd)
1091 qtd_next->status = QTD_RETIRE;
1092 }
1093 }
1094
1095 if (qtd->payload_addr)
1096 free_mem(hcd, qtd);
1097
1098 if (last_qtd) {
1099 if ((qtd->status == QTD_RETIRE) &&
1100 (qtd->urb->status == -EINPROGRESS))
1101 qtd->urb->status = -EPIPE;
1102 /* Defer calling of urb_done() since it releases lock */
1103 urb_listitem = kmem_cache_zalloc(urb_listitem_cachep,
1104 GFP_ATOMIC);
1105 if (unlikely(!urb_listitem))
1106 break; /* Try again on next call */
1107 urb_listitem->urb = qtd->urb;
1108 list_add_tail(&urb_listitem->urb_list, urb_list);
1109 }
1110
1111 list_del(&qtd->qtd_list);
1112 qtd_free(qtd);
1113 }
1114 }
1115
1116 #define ENQUEUE_DEPTH 2
enqueue_qtds(struct usb_hcd * hcd,struct isp1760_qh * qh)1117 static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh)
1118 {
1119 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1120 const struct isp1760_memory_layout *mem = priv->memory_layout;
1121 int slot_num = mem->slot_num;
1122 int ptd_offset;
1123 struct isp1760_slotinfo *slots;
1124 int curr_slot, free_slot;
1125 int n;
1126 struct ptd ptd;
1127 struct isp1760_qtd *qtd;
1128
1129 if (unlikely(list_empty(&qh->qtd_list))) {
1130 WARN_ON(1);
1131 return;
1132 }
1133
1134 /* Make sure this endpoint's TT buffer is clean before queueing ptds */
1135 if (qh->tt_buffer_dirty)
1136 return;
1137
1138 if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd,
1139 qtd_list)->urb->pipe)) {
1140 ptd_offset = INT_PTD_OFFSET;
1141 slots = priv->int_slots;
1142 } else {
1143 ptd_offset = ATL_PTD_OFFSET;
1144 slots = priv->atl_slots;
1145 }
1146
1147 free_slot = -1;
1148 for (curr_slot = 0; curr_slot < slot_num; curr_slot++) {
1149 if ((free_slot == -1) && (slots[curr_slot].qtd == NULL))
1150 free_slot = curr_slot;
1151 if (slots[curr_slot].qh == qh)
1152 break;
1153 }
1154
1155 n = 0;
1156 list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
1157 if (qtd->status == QTD_ENQUEUED) {
1158 WARN_ON(qtd->payload_addr);
1159 alloc_mem(hcd, qtd);
1160 if ((qtd->length) && (!qtd->payload_addr))
1161 break;
1162
1163 if (qtd->length && (qtd->packet_type == SETUP_PID ||
1164 qtd->packet_type == OUT_PID)) {
1165 mem_write(hcd, qtd->payload_addr,
1166 qtd->data_buffer, qtd->length);
1167 }
1168
1169 qtd->status = QTD_PAYLOAD_ALLOC;
1170 }
1171
1172 if (qtd->status == QTD_PAYLOAD_ALLOC) {
1173 /*
1174 if ((curr_slot > 31) && (free_slot == -1))
1175 dev_dbg(hcd->self.controller, "%s: No slot "
1176 "available for transfer\n", __func__);
1177 */
1178 /* Start xfer for this endpoint if not already done */
1179 if ((curr_slot > slot_num - 1) && (free_slot > -1)) {
1180 if (usb_pipeint(qtd->urb->pipe))
1181 create_ptd_int(qh, qtd, &ptd);
1182 else
1183 create_ptd_atl(qh, qtd, &ptd);
1184
1185 start_bus_transfer(hcd, ptd_offset, free_slot,
1186 slots, qtd, qh, &ptd);
1187 curr_slot = free_slot;
1188 }
1189
1190 n++;
1191 if (n >= ENQUEUE_DEPTH)
1192 break;
1193 }
1194 }
1195 }
1196
schedule_ptds(struct usb_hcd * hcd)1197 static void schedule_ptds(struct usb_hcd *hcd)
1198 {
1199 struct isp1760_hcd *priv;
1200 struct isp1760_qh *qh, *qh_next;
1201 struct list_head *ep_queue;
1202 LIST_HEAD(urb_list);
1203 struct urb_listitem *urb_listitem, *urb_listitem_next;
1204 int i;
1205
1206 if (!hcd) {
1207 WARN_ON(1);
1208 return;
1209 }
1210
1211 priv = hcd_to_priv(hcd);
1212
1213 /*
1214 * check finished/retired xfers, transfer payloads, call urb_done()
1215 */
1216 for (i = 0; i < QH_END; i++) {
1217 ep_queue = &priv->qh_list[i];
1218 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) {
1219 collect_qtds(hcd, qh, &urb_list);
1220 if (list_empty(&qh->qtd_list))
1221 list_del(&qh->qh_list);
1222 }
1223 }
1224
1225 list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list,
1226 urb_list) {
1227 isp1760_urb_done(hcd, urb_listitem->urb);
1228 kmem_cache_free(urb_listitem_cachep, urb_listitem);
1229 }
1230
1231 /*
1232 * Schedule packets for transfer.
1233 *
1234 * According to USB2.0 specification:
1235 *
1236 * 1st prio: interrupt xfers, up to 80 % of bandwidth
1237 * 2nd prio: control xfers
1238 * 3rd prio: bulk xfers
1239 *
1240 * ... but let's use a simpler scheme here (mostly because ISP1761 doc
1241 * is very unclear on how to prioritize traffic):
1242 *
1243 * 1) Enqueue any queued control transfers, as long as payload chip mem
1244 * and PTD ATL slots are available.
1245 * 2) Enqueue any queued INT transfers, as long as payload chip mem
1246 * and PTD INT slots are available.
1247 * 3) Enqueue any queued bulk transfers, as long as payload chip mem
1248 * and PTD ATL slots are available.
1249 *
1250 * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between
1251 * conservation of chip mem and performance.
1252 *
1253 * I'm sure this scheme could be improved upon!
1254 */
1255 for (i = 0; i < QH_END; i++) {
1256 ep_queue = &priv->qh_list[i];
1257 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list)
1258 enqueue_qtds(hcd, qh);
1259 }
1260 }
1261
1262 #define PTD_STATE_QTD_DONE 1
1263 #define PTD_STATE_QTD_RELOAD 2
1264 #define PTD_STATE_URB_RETIRE 3
1265
check_int_transfer(struct usb_hcd * hcd,struct ptd * ptd,struct urb * urb)1266 static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1267 struct urb *urb)
1268 {
1269 u32 dw4;
1270 int i;
1271
1272 dw4 = TO_U32(ptd->dw4);
1273 dw4 >>= 8;
1274
1275 /* FIXME: ISP1761 datasheet does not say what to do with these. Do we
1276 need to handle these errors? Is it done in hardware? */
1277
1278 if (ptd->dw3 & DW3_HALT_BIT) {
1279
1280 urb->status = -EPROTO; /* Default unknown error */
1281
1282 for (i = 0; i < 8; i++) {
1283 switch (dw4 & 0x7) {
1284 case INT_UNDERRUN:
1285 dev_dbg(hcd->self.controller, "%s: underrun "
1286 "during uFrame %d\n",
1287 __func__, i);
1288 urb->status = -ECOMM; /* Could not write data */
1289 break;
1290 case INT_EXACT:
1291 dev_dbg(hcd->self.controller, "%s: transaction "
1292 "error during uFrame %d\n",
1293 __func__, i);
1294 urb->status = -EPROTO; /* timeout, bad CRC, PID
1295 error etc. */
1296 break;
1297 case INT_BABBLE:
1298 dev_dbg(hcd->self.controller, "%s: babble "
1299 "error during uFrame %d\n",
1300 __func__, i);
1301 urb->status = -EOVERFLOW;
1302 break;
1303 }
1304 dw4 >>= 3;
1305 }
1306
1307 return PTD_STATE_URB_RETIRE;
1308 }
1309
1310 return PTD_STATE_QTD_DONE;
1311 }
1312
check_atl_transfer(struct usb_hcd * hcd,struct ptd * ptd,struct urb * urb)1313 static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1314 struct urb *urb)
1315 {
1316 WARN_ON(!ptd);
1317 if (ptd->dw3 & DW3_HALT_BIT) {
1318 if (ptd->dw3 & DW3_BABBLE_BIT)
1319 urb->status = -EOVERFLOW;
1320 else if (FROM_DW3_CERR(ptd->dw3))
1321 urb->status = -EPIPE; /* Stall */
1322 else
1323 urb->status = -EPROTO; /* Unknown */
1324 /*
1325 dev_dbg(hcd->self.controller, "%s: ptd error:\n"
1326 " dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n"
1327 " dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n",
1328 __func__,
1329 ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3,
1330 ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7);
1331 */
1332 return PTD_STATE_URB_RETIRE;
1333 }
1334
1335 if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1336 /* Transfer Error, *but* active and no HALT -> reload */
1337 dev_dbg(hcd->self.controller, "PID error; reloading ptd\n");
1338 return PTD_STATE_QTD_RELOAD;
1339 }
1340
1341 if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1342 /*
1343 * NAKs are handled in HW by the chip. Usually if the
1344 * device is not able to send data fast enough.
1345 * This happens mostly on slower hardware.
1346 */
1347 return PTD_STATE_QTD_RELOAD;
1348 }
1349
1350 return PTD_STATE_QTD_DONE;
1351 }
1352
handle_done_ptds(struct usb_hcd * hcd)1353 static void handle_done_ptds(struct usb_hcd *hcd)
1354 {
1355 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1356 struct ptd ptd;
1357 struct isp1760_qh *qh;
1358 int slot;
1359 int state;
1360 struct isp1760_slotinfo *slots;
1361 u32 ptd_offset;
1362 struct isp1760_qtd *qtd;
1363 int modified;
1364 int skip_map;
1365
1366 skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP);
1367 priv->int_done_map &= ~skip_map;
1368 skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP);
1369 priv->atl_done_map &= ~skip_map;
1370
1371 modified = priv->int_done_map || priv->atl_done_map;
1372
1373 while (priv->int_done_map || priv->atl_done_map) {
1374 if (priv->int_done_map) {
1375 /* INT ptd */
1376 slot = __ffs(priv->int_done_map);
1377 priv->int_done_map &= ~(1 << slot);
1378 slots = priv->int_slots;
1379 /* This should not trigger, and could be removed if
1380 noone have any problems with it triggering: */
1381 if (!slots[slot].qh) {
1382 WARN_ON(1);
1383 continue;
1384 }
1385 ptd_offset = INT_PTD_OFFSET;
1386 ptd_read(hcd, INT_PTD_OFFSET, slot, &ptd);
1387 state = check_int_transfer(hcd, &ptd,
1388 slots[slot].qtd->urb);
1389 } else {
1390 /* ATL ptd */
1391 slot = __ffs(priv->atl_done_map);
1392 priv->atl_done_map &= ~(1 << slot);
1393 slots = priv->atl_slots;
1394 /* This should not trigger, and could be removed if
1395 noone have any problems with it triggering: */
1396 if (!slots[slot].qh) {
1397 WARN_ON(1);
1398 continue;
1399 }
1400 ptd_offset = ATL_PTD_OFFSET;
1401 ptd_read(hcd, ATL_PTD_OFFSET, slot, &ptd);
1402 state = check_atl_transfer(hcd, &ptd,
1403 slots[slot].qtd->urb);
1404 }
1405
1406 qtd = slots[slot].qtd;
1407 slots[slot].qtd = NULL;
1408 qh = slots[slot].qh;
1409 slots[slot].qh = NULL;
1410 qh->slot = -1;
1411
1412 WARN_ON(qtd->status != QTD_XFER_STARTED);
1413
1414 switch (state) {
1415 case PTD_STATE_QTD_DONE:
1416 if ((usb_pipeint(qtd->urb->pipe)) &&
1417 (qtd->urb->dev->speed != USB_SPEED_HIGH))
1418 qtd->actual_length =
1419 FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3);
1420 else
1421 qtd->actual_length =
1422 FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3);
1423
1424 qtd->status = QTD_XFER_COMPLETE;
1425 if (list_is_last(&qtd->qtd_list, &qh->qtd_list) ||
1426 is_short_bulk(qtd))
1427 qtd = NULL;
1428 else
1429 qtd = list_entry(qtd->qtd_list.next,
1430 typeof(*qtd), qtd_list);
1431
1432 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1433 qh->ping = FROM_DW3_PING(ptd.dw3);
1434 break;
1435
1436 case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */
1437 qtd->status = QTD_PAYLOAD_ALLOC;
1438 ptd.dw0 |= DW0_VALID_BIT;
1439 /* RL counter = ERR counter */
1440 ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf);
1441 ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2));
1442 ptd.dw3 &= ~TO_DW3_CERR(3);
1443 ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER);
1444 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1445 qh->ping = FROM_DW3_PING(ptd.dw3);
1446 break;
1447
1448 case PTD_STATE_URB_RETIRE:
1449 qtd->status = QTD_RETIRE;
1450 if ((qtd->urb->dev->speed != USB_SPEED_HIGH) &&
1451 (qtd->urb->status != -EPIPE) &&
1452 (qtd->urb->status != -EREMOTEIO)) {
1453 qh->tt_buffer_dirty = 1;
1454 if (usb_hub_clear_tt_buffer(qtd->urb))
1455 /* Clear failed; let's hope things work
1456 anyway */
1457 qh->tt_buffer_dirty = 0;
1458 }
1459 qtd = NULL;
1460 qh->toggle = 0;
1461 qh->ping = 0;
1462 break;
1463
1464 default:
1465 WARN_ON(1);
1466 continue;
1467 }
1468
1469 if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) {
1470 if (slots == priv->int_slots) {
1471 if (state == PTD_STATE_QTD_RELOAD)
1472 dev_err(hcd->self.controller,
1473 "%s: PTD_STATE_QTD_RELOAD on "
1474 "interrupt packet\n", __func__);
1475 if (state != PTD_STATE_QTD_RELOAD)
1476 create_ptd_int(qh, qtd, &ptd);
1477 } else {
1478 if (state != PTD_STATE_QTD_RELOAD)
1479 create_ptd_atl(qh, qtd, &ptd);
1480 }
1481
1482 start_bus_transfer(hcd, ptd_offset, slot, slots, qtd,
1483 qh, &ptd);
1484 }
1485 }
1486
1487 if (modified)
1488 schedule_ptds(hcd);
1489 }
1490
isp1760_irq(struct usb_hcd * hcd)1491 static irqreturn_t isp1760_irq(struct usb_hcd *hcd)
1492 {
1493 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1494 irqreturn_t irqret = IRQ_NONE;
1495 u32 int_reg;
1496 u32 imask;
1497
1498 spin_lock(&priv->lock);
1499
1500 if (!(hcd->state & HC_STATE_RUNNING))
1501 goto leave;
1502
1503 imask = isp1760_hcd_read(hcd, HC_INTERRUPT);
1504 if (unlikely(!imask))
1505 goto leave;
1506
1507 int_reg = priv->is_isp1763 ? ISP1763_HC_INTERRUPT :
1508 ISP176x_HC_INTERRUPT;
1509 isp1760_reg_write(priv->regs, int_reg, imask);
1510
1511 priv->int_done_map |= isp1760_hcd_read(hcd, HC_INT_PTD_DONEMAP);
1512 priv->atl_done_map |= isp1760_hcd_read(hcd, HC_ATL_PTD_DONEMAP);
1513
1514 handle_done_ptds(hcd);
1515
1516 irqret = IRQ_HANDLED;
1517
1518 leave:
1519 spin_unlock(&priv->lock);
1520
1521 return irqret;
1522 }
1523
1524 /*
1525 * Workaround for problem described in chip errata 2:
1526 *
1527 * Sometimes interrupts are not generated when ATL (not INT?) completion occurs.
1528 * One solution suggested in the errata is to use SOF interrupts _instead_of_
1529 * ATL done interrupts (the "instead of" might be important since it seems
1530 * enabling ATL interrupts also causes the chip to sometimes - rarely - "forget"
1531 * to set the PTD's done bit in addition to not generating an interrupt!).
1532 *
1533 * So if we use SOF + ATL interrupts, we sometimes get stale PTDs since their
1534 * done bit is not being set. This is bad - it blocks the endpoint until reboot.
1535 *
1536 * If we use SOF interrupts only, we get latency between ptd completion and the
1537 * actual handling. This is very noticeable in testusb runs which takes several
1538 * minutes longer without ATL interrupts.
1539 *
1540 * A better solution is to run the code below every SLOT_CHECK_PERIOD ms. If it
1541 * finds active ATL slots which are older than SLOT_TIMEOUT ms, it checks the
1542 * slot's ACTIVE and VALID bits. If these are not set, the ptd is considered
1543 * completed and its done map bit is set.
1544 *
1545 * The values of SLOT_TIMEOUT and SLOT_CHECK_PERIOD have been arbitrarily chosen
1546 * not to cause too much lag when this HW bug occurs, while still hopefully
1547 * ensuring that the check does not falsely trigger.
1548 */
1549 #define SLOT_TIMEOUT 300
1550 #define SLOT_CHECK_PERIOD 200
1551 static struct timer_list errata2_timer;
1552 static struct usb_hcd *errata2_timer_hcd;
1553
errata2_function(struct timer_list * unused)1554 static void errata2_function(struct timer_list *unused)
1555 {
1556 struct usb_hcd *hcd = errata2_timer_hcd;
1557 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1558 const struct isp1760_memory_layout *mem = priv->memory_layout;
1559 int slot;
1560 struct ptd ptd;
1561 unsigned long spinflags;
1562
1563 spin_lock_irqsave(&priv->lock, spinflags);
1564
1565 for (slot = 0; slot < mem->slot_num; slot++)
1566 if (priv->atl_slots[slot].qh && time_after(jiffies,
1567 priv->atl_slots[slot].timestamp +
1568 msecs_to_jiffies(SLOT_TIMEOUT))) {
1569 ptd_read(hcd, ATL_PTD_OFFSET, slot, &ptd);
1570 if (!FROM_DW0_VALID(ptd.dw0) &&
1571 !FROM_DW3_ACTIVE(ptd.dw3))
1572 priv->atl_done_map |= 1 << slot;
1573 }
1574
1575 if (priv->atl_done_map)
1576 handle_done_ptds(hcd);
1577
1578 spin_unlock_irqrestore(&priv->lock, spinflags);
1579
1580 errata2_timer.expires = jiffies + msecs_to_jiffies(SLOT_CHECK_PERIOD);
1581 add_timer(&errata2_timer);
1582 }
1583
isp1763_run(struct usb_hcd * hcd)1584 static int isp1763_run(struct usb_hcd *hcd)
1585 {
1586 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1587 int retval;
1588 u32 chipid_h;
1589 u32 chipid_l;
1590 u32 chip_rev;
1591 u32 ptd_atl_int;
1592 u32 ptd_iso;
1593
1594 hcd->uses_new_polling = 1;
1595 hcd->state = HC_STATE_RUNNING;
1596
1597 chipid_h = isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH);
1598 chipid_l = isp1760_hcd_read(hcd, HC_CHIP_ID_LOW);
1599 chip_rev = isp1760_hcd_read(hcd, HC_CHIP_REV);
1600 dev_info(hcd->self.controller, "USB ISP %02x%02x HW rev. %d started\n",
1601 chipid_h, chipid_l, chip_rev);
1602
1603 isp1760_hcd_clear(hcd, ISO_BUF_FILL);
1604 isp1760_hcd_clear(hcd, INT_BUF_FILL);
1605 isp1760_hcd_clear(hcd, ATL_BUF_FILL);
1606
1607 isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP);
1608 isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP);
1609 isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP);
1610 ndelay(100);
1611 isp1760_hcd_clear(hcd, HC_ATL_PTD_DONEMAP);
1612 isp1760_hcd_clear(hcd, HC_INT_PTD_DONEMAP);
1613 isp1760_hcd_clear(hcd, HC_ISO_PTD_DONEMAP);
1614
1615 isp1760_hcd_set(hcd, HW_OTG_DISABLE);
1616 isp1760_reg_write(priv->regs, ISP1763_HC_OTG_CTRL_CLEAR, BIT(7));
1617 isp1760_reg_write(priv->regs, ISP1763_HC_OTG_CTRL_CLEAR, BIT(15));
1618 mdelay(10);
1619
1620 isp1760_hcd_set(hcd, HC_INT_IRQ_ENABLE);
1621 isp1760_hcd_set(hcd, HC_ATL_IRQ_ENABLE);
1622
1623 isp1760_hcd_set(hcd, HW_GLOBAL_INTR_EN);
1624
1625 isp1760_hcd_clear(hcd, HC_ATL_IRQ_MASK_AND);
1626 isp1760_hcd_clear(hcd, HC_INT_IRQ_MASK_AND);
1627 isp1760_hcd_clear(hcd, HC_ISO_IRQ_MASK_AND);
1628
1629 isp1760_hcd_set(hcd, HC_ATL_IRQ_MASK_OR);
1630 isp1760_hcd_set(hcd, HC_INT_IRQ_MASK_OR);
1631 isp1760_hcd_set(hcd, HC_ISO_IRQ_MASK_OR);
1632
1633 ptd_atl_int = 0x8000;
1634 ptd_iso = 0x0001;
1635
1636 isp1760_hcd_write(hcd, HC_ATL_PTD_LASTPTD, ptd_atl_int);
1637 isp1760_hcd_write(hcd, HC_INT_PTD_LASTPTD, ptd_atl_int);
1638 isp1760_hcd_write(hcd, HC_ISO_PTD_LASTPTD, ptd_iso);
1639
1640 isp1760_hcd_set(hcd, ATL_BUF_FILL);
1641 isp1760_hcd_set(hcd, INT_BUF_FILL);
1642
1643 isp1760_hcd_clear(hcd, CMD_LRESET);
1644 isp1760_hcd_clear(hcd, CMD_RESET);
1645
1646 retval = isp1760_hcd_set_and_wait(hcd, CMD_RUN, 250 * 1000);
1647 if (retval)
1648 return retval;
1649
1650 down_write(&ehci_cf_port_reset_rwsem);
1651 retval = isp1760_hcd_set_and_wait(hcd, FLAG_CF, 250 * 1000);
1652 up_write(&ehci_cf_port_reset_rwsem);
1653 if (retval)
1654 return retval;
1655
1656 return 0;
1657 }
1658
isp1760_run(struct usb_hcd * hcd)1659 static int isp1760_run(struct usb_hcd *hcd)
1660 {
1661 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1662 int retval;
1663 u32 chipid_h;
1664 u32 chipid_l;
1665 u32 chip_rev;
1666 u32 ptd_atl_int;
1667 u32 ptd_iso;
1668
1669 /*
1670 * ISP1763 have some differences in the setup and order to enable
1671 * the ports, disable otg, setup buffers, and ATL, INT, ISO status.
1672 * So, just handle it a separate sequence.
1673 */
1674 if (priv->is_isp1763)
1675 return isp1763_run(hcd);
1676
1677 hcd->uses_new_polling = 1;
1678
1679 hcd->state = HC_STATE_RUNNING;
1680
1681 /* Set PTD interrupt AND & OR maps */
1682 isp1760_hcd_clear(hcd, HC_ATL_IRQ_MASK_AND);
1683 isp1760_hcd_clear(hcd, HC_INT_IRQ_MASK_AND);
1684 isp1760_hcd_clear(hcd, HC_ISO_IRQ_MASK_AND);
1685
1686 isp1760_hcd_set(hcd, HC_ATL_IRQ_MASK_OR);
1687 isp1760_hcd_set(hcd, HC_INT_IRQ_MASK_OR);
1688 isp1760_hcd_set(hcd, HC_ISO_IRQ_MASK_OR);
1689
1690 /* step 23 passed */
1691
1692 isp1760_hcd_set(hcd, HW_GLOBAL_INTR_EN);
1693
1694 isp1760_hcd_clear(hcd, CMD_LRESET);
1695 isp1760_hcd_clear(hcd, CMD_RESET);
1696
1697 retval = isp1760_hcd_set_and_wait(hcd, CMD_RUN, 250 * 1000);
1698 if (retval)
1699 return retval;
1700
1701 /*
1702 * XXX
1703 * Spec says to write FLAG_CF as last config action, priv code grabs
1704 * the semaphore while doing so.
1705 */
1706 down_write(&ehci_cf_port_reset_rwsem);
1707
1708 retval = isp1760_hcd_set_and_wait(hcd, FLAG_CF, 250 * 1000);
1709 up_write(&ehci_cf_port_reset_rwsem);
1710 if (retval)
1711 return retval;
1712
1713 errata2_timer_hcd = hcd;
1714 timer_setup(&errata2_timer, errata2_function, 0);
1715 errata2_timer.expires = jiffies + msecs_to_jiffies(SLOT_CHECK_PERIOD);
1716 add_timer(&errata2_timer);
1717
1718 chipid_h = isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH);
1719 chipid_l = isp1760_hcd_read(hcd, HC_CHIP_ID_LOW);
1720 chip_rev = isp1760_hcd_read(hcd, HC_CHIP_REV);
1721 dev_info(hcd->self.controller, "USB ISP %02x%02x HW rev. %d started\n",
1722 chipid_h, chipid_l, chip_rev);
1723
1724 /* PTD Register Init Part 2, Step 28 */
1725
1726 /* Setup registers controlling PTD checking */
1727 ptd_atl_int = 0x80000000;
1728 ptd_iso = 0x00000001;
1729
1730 isp1760_hcd_write(hcd, HC_ATL_PTD_LASTPTD, ptd_atl_int);
1731 isp1760_hcd_write(hcd, HC_INT_PTD_LASTPTD, ptd_atl_int);
1732 isp1760_hcd_write(hcd, HC_ISO_PTD_LASTPTD, ptd_iso);
1733
1734 isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP);
1735 isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP);
1736 isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP);
1737
1738 isp1760_hcd_set(hcd, ATL_BUF_FILL);
1739 isp1760_hcd_set(hcd, INT_BUF_FILL);
1740
1741 /* GRR this is run-once init(), being done every time the HC starts.
1742 * So long as they're part of class devices, we can't do it init()
1743 * since the class device isn't created that early.
1744 */
1745 return 0;
1746 }
1747
qtd_fill(struct isp1760_qtd * qtd,void * databuffer,size_t len)1748 static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len)
1749 {
1750 qtd->data_buffer = databuffer;
1751
1752 qtd->length = len;
1753
1754 return qtd->length;
1755 }
1756
qtd_list_free(struct list_head * qtd_list)1757 static void qtd_list_free(struct list_head *qtd_list)
1758 {
1759 struct isp1760_qtd *qtd, *qtd_next;
1760
1761 list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) {
1762 list_del(&qtd->qtd_list);
1763 qtd_free(qtd);
1764 }
1765 }
1766
1767 /*
1768 * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize.
1769 * Also calculate the PID type (SETUP/IN/OUT) for each packet.
1770 */
1771 #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
packetize_urb(struct usb_hcd * hcd,struct urb * urb,struct list_head * head,gfp_t flags)1772 static void packetize_urb(struct usb_hcd *hcd,
1773 struct urb *urb, struct list_head *head, gfp_t flags)
1774 {
1775 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1776 const struct isp1760_memory_layout *mem = priv->memory_layout;
1777 struct isp1760_qtd *qtd;
1778 void *buf;
1779 int len, maxpacketsize;
1780 u8 packet_type;
1781
1782 /*
1783 * URBs map to sequences of QTDs: one logical transaction
1784 */
1785
1786 if (!urb->transfer_buffer && urb->transfer_buffer_length) {
1787 /* XXX This looks like usb storage / SCSI bug */
1788 dev_err(hcd->self.controller,
1789 "buf is null, dma is %08lx len is %d\n",
1790 (long unsigned)urb->transfer_dma,
1791 urb->transfer_buffer_length);
1792 WARN_ON(1);
1793 }
1794
1795 if (usb_pipein(urb->pipe))
1796 packet_type = IN_PID;
1797 else
1798 packet_type = OUT_PID;
1799
1800 if (usb_pipecontrol(urb->pipe)) {
1801 qtd = qtd_alloc(flags, urb, SETUP_PID);
1802 if (!qtd)
1803 goto cleanup;
1804 qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest));
1805 list_add_tail(&qtd->qtd_list, head);
1806
1807 /* for zero length DATA stages, STATUS is always IN */
1808 if (urb->transfer_buffer_length == 0)
1809 packet_type = IN_PID;
1810 }
1811
1812 maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe,
1813 usb_pipeout(urb->pipe)));
1814
1815 /*
1816 * buffer gets wrapped in one or more qtds;
1817 * last one may be "short" (including zero len)
1818 * and may serve as a control status ack
1819 */
1820 buf = urb->transfer_buffer;
1821 len = urb->transfer_buffer_length;
1822
1823 for (;;) {
1824 int this_qtd_len;
1825
1826 qtd = qtd_alloc(flags, urb, packet_type);
1827 if (!qtd)
1828 goto cleanup;
1829
1830 if (len > mem->blocks_size[ISP176x_BLOCK_NUM - 1])
1831 this_qtd_len = mem->blocks_size[ISP176x_BLOCK_NUM - 1];
1832 else
1833 this_qtd_len = len;
1834
1835 this_qtd_len = qtd_fill(qtd, buf, this_qtd_len);
1836 list_add_tail(&qtd->qtd_list, head);
1837
1838 len -= this_qtd_len;
1839 buf += this_qtd_len;
1840
1841 if (len <= 0)
1842 break;
1843 }
1844
1845 /*
1846 * control requests may need a terminating data "status" ack;
1847 * bulk ones may need a terminating short packet (zero length).
1848 */
1849 if (urb->transfer_buffer_length != 0) {
1850 int one_more = 0;
1851
1852 if (usb_pipecontrol(urb->pipe)) {
1853 one_more = 1;
1854 if (packet_type == IN_PID)
1855 packet_type = OUT_PID;
1856 else
1857 packet_type = IN_PID;
1858 } else if (usb_pipebulk(urb->pipe) && maxpacketsize
1859 && (urb->transfer_flags & URB_ZERO_PACKET)
1860 && !(urb->transfer_buffer_length %
1861 maxpacketsize)) {
1862 one_more = 1;
1863 }
1864 if (one_more) {
1865 qtd = qtd_alloc(flags, urb, packet_type);
1866 if (!qtd)
1867 goto cleanup;
1868
1869 /* never any data in such packets */
1870 qtd_fill(qtd, NULL, 0);
1871 list_add_tail(&qtd->qtd_list, head);
1872 }
1873 }
1874
1875 return;
1876
1877 cleanup:
1878 qtd_list_free(head);
1879 }
1880
isp1760_urb_enqueue(struct usb_hcd * hcd,struct urb * urb,gfp_t mem_flags)1881 static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
1882 gfp_t mem_flags)
1883 {
1884 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1885 struct list_head *ep_queue;
1886 struct isp1760_qh *qh, *qhit;
1887 unsigned long spinflags;
1888 LIST_HEAD(new_qtds);
1889 int retval;
1890 int qh_in_queue;
1891
1892 switch (usb_pipetype(urb->pipe)) {
1893 case PIPE_CONTROL:
1894 ep_queue = &priv->qh_list[QH_CONTROL];
1895 break;
1896 case PIPE_BULK:
1897 ep_queue = &priv->qh_list[QH_BULK];
1898 break;
1899 case PIPE_INTERRUPT:
1900 if (urb->interval < 0)
1901 return -EINVAL;
1902 /* FIXME: Check bandwidth */
1903 ep_queue = &priv->qh_list[QH_INTERRUPT];
1904 break;
1905 case PIPE_ISOCHRONOUS:
1906 dev_err(hcd->self.controller, "%s: isochronous USB packets "
1907 "not yet supported\n",
1908 __func__);
1909 return -EPIPE;
1910 default:
1911 dev_err(hcd->self.controller, "%s: unknown pipe type\n",
1912 __func__);
1913 return -EPIPE;
1914 }
1915
1916 if (usb_pipein(urb->pipe))
1917 urb->actual_length = 0;
1918
1919 packetize_urb(hcd, urb, &new_qtds, mem_flags);
1920 if (list_empty(&new_qtds))
1921 return -ENOMEM;
1922
1923 spin_lock_irqsave(&priv->lock, spinflags);
1924
1925 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
1926 retval = -ESHUTDOWN;
1927 qtd_list_free(&new_qtds);
1928 goto out;
1929 }
1930 retval = usb_hcd_link_urb_to_ep(hcd, urb);
1931 if (retval) {
1932 qtd_list_free(&new_qtds);
1933 goto out;
1934 }
1935
1936 qh = urb->ep->hcpriv;
1937 if (qh) {
1938 qh_in_queue = 0;
1939 list_for_each_entry(qhit, ep_queue, qh_list) {
1940 if (qhit == qh) {
1941 qh_in_queue = 1;
1942 break;
1943 }
1944 }
1945 if (!qh_in_queue)
1946 list_add_tail(&qh->qh_list, ep_queue);
1947 } else {
1948 qh = qh_alloc(GFP_ATOMIC);
1949 if (!qh) {
1950 retval = -ENOMEM;
1951 usb_hcd_unlink_urb_from_ep(hcd, urb);
1952 qtd_list_free(&new_qtds);
1953 goto out;
1954 }
1955 list_add_tail(&qh->qh_list, ep_queue);
1956 urb->ep->hcpriv = qh;
1957 }
1958
1959 list_splice_tail(&new_qtds, &qh->qtd_list);
1960 schedule_ptds(hcd);
1961
1962 out:
1963 spin_unlock_irqrestore(&priv->lock, spinflags);
1964 return retval;
1965 }
1966
kill_transfer(struct usb_hcd * hcd,struct urb * urb,struct isp1760_qh * qh)1967 static void kill_transfer(struct usb_hcd *hcd, struct urb *urb,
1968 struct isp1760_qh *qh)
1969 {
1970 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1971 int skip_map;
1972
1973 WARN_ON(qh->slot == -1);
1974
1975 /* We need to forcefully reclaim the slot since some transfers never
1976 return, e.g. interrupt transfers and NAKed bulk transfers. */
1977 if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) {
1978 if (qh->slot != -1) {
1979 skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP);
1980 skip_map |= (1 << qh->slot);
1981 isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP, skip_map);
1982 ndelay(100);
1983 }
1984 priv->atl_slots[qh->slot].qh = NULL;
1985 priv->atl_slots[qh->slot].qtd = NULL;
1986 } else {
1987 if (qh->slot != -1) {
1988 skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP);
1989 skip_map |= (1 << qh->slot);
1990 isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP, skip_map);
1991 }
1992 priv->int_slots[qh->slot].qh = NULL;
1993 priv->int_slots[qh->slot].qtd = NULL;
1994 }
1995
1996 qh->slot = -1;
1997 }
1998
1999 /*
2000 * Retire the qtds beginning at 'qtd' and belonging all to the same urb, killing
2001 * any active transfer belonging to the urb in the process.
2002 */
dequeue_urb_from_qtd(struct usb_hcd * hcd,struct isp1760_qh * qh,struct isp1760_qtd * qtd)2003 static void dequeue_urb_from_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh,
2004 struct isp1760_qtd *qtd)
2005 {
2006 struct urb *urb;
2007 int urb_was_running;
2008
2009 urb = qtd->urb;
2010 urb_was_running = 0;
2011 list_for_each_entry_from(qtd, &qh->qtd_list, qtd_list) {
2012 if (qtd->urb != urb)
2013 break;
2014
2015 if (qtd->status >= QTD_XFER_STARTED)
2016 urb_was_running = 1;
2017 if (last_qtd_of_urb(qtd, qh) &&
2018 (qtd->status >= QTD_XFER_COMPLETE))
2019 urb_was_running = 0;
2020
2021 if (qtd->status == QTD_XFER_STARTED)
2022 kill_transfer(hcd, urb, qh);
2023 qtd->status = QTD_RETIRE;
2024 }
2025
2026 if ((urb->dev->speed != USB_SPEED_HIGH) && urb_was_running) {
2027 qh->tt_buffer_dirty = 1;
2028 if (usb_hub_clear_tt_buffer(urb))
2029 /* Clear failed; let's hope things work anyway */
2030 qh->tt_buffer_dirty = 0;
2031 }
2032 }
2033
isp1760_urb_dequeue(struct usb_hcd * hcd,struct urb * urb,int status)2034 static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
2035 int status)
2036 {
2037 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2038 unsigned long spinflags;
2039 struct isp1760_qh *qh;
2040 struct isp1760_qtd *qtd;
2041 int retval = 0;
2042
2043 spin_lock_irqsave(&priv->lock, spinflags);
2044 retval = usb_hcd_check_unlink_urb(hcd, urb, status);
2045 if (retval)
2046 goto out;
2047
2048 qh = urb->ep->hcpriv;
2049 if (!qh) {
2050 retval = -EINVAL;
2051 goto out;
2052 }
2053
2054 list_for_each_entry(qtd, &qh->qtd_list, qtd_list)
2055 if (qtd->urb == urb) {
2056 dequeue_urb_from_qtd(hcd, qh, qtd);
2057 list_move(&qtd->qtd_list, &qh->qtd_list);
2058 break;
2059 }
2060
2061 urb->status = status;
2062 schedule_ptds(hcd);
2063
2064 out:
2065 spin_unlock_irqrestore(&priv->lock, spinflags);
2066 return retval;
2067 }
2068
isp1760_endpoint_disable(struct usb_hcd * hcd,struct usb_host_endpoint * ep)2069 static void isp1760_endpoint_disable(struct usb_hcd *hcd,
2070 struct usb_host_endpoint *ep)
2071 {
2072 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2073 unsigned long spinflags;
2074 struct isp1760_qh *qh, *qh_iter;
2075 int i;
2076
2077 spin_lock_irqsave(&priv->lock, spinflags);
2078
2079 qh = ep->hcpriv;
2080 if (!qh)
2081 goto out;
2082
2083 WARN_ON(!list_empty(&qh->qtd_list));
2084
2085 for (i = 0; i < QH_END; i++)
2086 list_for_each_entry(qh_iter, &priv->qh_list[i], qh_list)
2087 if (qh_iter == qh) {
2088 list_del(&qh_iter->qh_list);
2089 i = QH_END;
2090 break;
2091 }
2092 qh_free(qh);
2093 ep->hcpriv = NULL;
2094
2095 schedule_ptds(hcd);
2096
2097 out:
2098 spin_unlock_irqrestore(&priv->lock, spinflags);
2099 }
2100
isp1760_hub_status_data(struct usb_hcd * hcd,char * buf)2101 static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
2102 {
2103 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2104 u32 status = 0;
2105 int retval = 1;
2106 unsigned long flags;
2107
2108 /* if !PM, root hub timers won't get shut down ... */
2109 if (!HC_IS_RUNNING(hcd->state))
2110 return 0;
2111
2112 /* init status to no-changes */
2113 buf[0] = 0;
2114
2115 spin_lock_irqsave(&priv->lock, flags);
2116
2117 if (isp1760_hcd_is_set(hcd, PORT_OWNER) &&
2118 isp1760_hcd_is_set(hcd, PORT_CSC)) {
2119 isp1760_hcd_clear(hcd, PORT_CSC);
2120 goto done;
2121 }
2122
2123 /*
2124 * Return status information even for ports with OWNER set.
2125 * Otherwise hub_wq wouldn't see the disconnect event when a
2126 * high-speed device is switched over to the companion
2127 * controller by the user.
2128 */
2129 if (isp1760_hcd_is_set(hcd, PORT_CSC) ||
2130 (isp1760_hcd_is_set(hcd, PORT_RESUME) &&
2131 time_after_eq(jiffies, priv->reset_done))) {
2132 buf [0] |= 1 << (0 + 1);
2133 status = STS_PCD;
2134 }
2135 /* FIXME autosuspend idle root hubs */
2136 done:
2137 spin_unlock_irqrestore(&priv->lock, flags);
2138 return status ? retval : 0;
2139 }
2140
isp1760_hub_descriptor(struct isp1760_hcd * priv,struct usb_hub_descriptor * desc)2141 static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
2142 struct usb_hub_descriptor *desc)
2143 {
2144 int ports;
2145 u16 temp;
2146
2147 ports = isp1760_hcd_n_ports(priv->hcd);
2148
2149 desc->bDescriptorType = USB_DT_HUB;
2150 /* priv 1.0, 2.3.9 says 20ms max */
2151 desc->bPwrOn2PwrGood = 10;
2152 desc->bHubContrCurrent = 0;
2153
2154 desc->bNbrPorts = ports;
2155 temp = 1 + (ports / 8);
2156 desc->bDescLength = 7 + 2 * temp;
2157
2158 /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */
2159 memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
2160 memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
2161
2162 /* per-port overcurrent reporting */
2163 temp = HUB_CHAR_INDV_PORT_OCPM;
2164 if (isp1760_hcd_ppc_is_set(priv->hcd))
2165 /* per-port power control */
2166 temp |= HUB_CHAR_INDV_PORT_LPSM;
2167 else
2168 /* no power switching */
2169 temp |= HUB_CHAR_NO_LPSM;
2170 desc->wHubCharacteristics = cpu_to_le16(temp);
2171 }
2172
2173 #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
2174
check_reset_complete(struct usb_hcd * hcd,int index)2175 static void check_reset_complete(struct usb_hcd *hcd, int index)
2176 {
2177 if (!(isp1760_hcd_is_set(hcd, PORT_CONNECT)))
2178 return;
2179
2180 /* if reset finished and it's still not enabled -- handoff */
2181 if (!isp1760_hcd_is_set(hcd, PORT_PE)) {
2182 dev_info(hcd->self.controller,
2183 "port %d full speed --> companion\n", index + 1);
2184
2185 isp1760_hcd_set(hcd, PORT_OWNER);
2186
2187 isp1760_hcd_clear(hcd, PORT_CSC);
2188 } else {
2189 dev_info(hcd->self.controller, "port %d high speed\n",
2190 index + 1);
2191 }
2192
2193 return;
2194 }
2195
isp1760_hub_control(struct usb_hcd * hcd,u16 typeReq,u16 wValue,u16 wIndex,char * buf,u16 wLength)2196 static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
2197 u16 wValue, u16 wIndex, char *buf, u16 wLength)
2198 {
2199 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2200 u32 status;
2201 unsigned long flags;
2202 int retval = 0;
2203 int ports;
2204
2205 ports = isp1760_hcd_n_ports(hcd);
2206
2207 /*
2208 * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
2209 * HCS_INDICATOR may say we can change LEDs to off/amber/green.
2210 * (track current state ourselves) ... blink for diagnostics,
2211 * power, "this is the one", etc. EHCI spec supports this.
2212 */
2213
2214 spin_lock_irqsave(&priv->lock, flags);
2215 switch (typeReq) {
2216 case ClearHubFeature:
2217 switch (wValue) {
2218 case C_HUB_LOCAL_POWER:
2219 case C_HUB_OVER_CURRENT:
2220 /* no hub-wide feature/status flags */
2221 break;
2222 default:
2223 goto error;
2224 }
2225 break;
2226 case ClearPortFeature:
2227 if (!wIndex || wIndex > ports)
2228 goto error;
2229 wIndex--;
2230
2231 /*
2232 * Even if OWNER is set, so the port is owned by the
2233 * companion controller, hub_wq needs to be able to clear
2234 * the port-change status bits (especially
2235 * USB_PORT_STAT_C_CONNECTION).
2236 */
2237
2238 switch (wValue) {
2239 case USB_PORT_FEAT_ENABLE:
2240 isp1760_hcd_clear(hcd, PORT_PE);
2241 break;
2242 case USB_PORT_FEAT_C_ENABLE:
2243 /* XXX error? */
2244 break;
2245 case USB_PORT_FEAT_SUSPEND:
2246 if (isp1760_hcd_is_set(hcd, PORT_RESET))
2247 goto error;
2248
2249 if (isp1760_hcd_is_set(hcd, PORT_SUSPEND)) {
2250 if (!isp1760_hcd_is_set(hcd, PORT_PE))
2251 goto error;
2252 /* resume signaling for 20 msec */
2253 isp1760_hcd_clear(hcd, PORT_CSC);
2254 isp1760_hcd_set(hcd, PORT_RESUME);
2255
2256 priv->reset_done = jiffies +
2257 msecs_to_jiffies(USB_RESUME_TIMEOUT);
2258 }
2259 break;
2260 case USB_PORT_FEAT_C_SUSPEND:
2261 /* we auto-clear this feature */
2262 break;
2263 case USB_PORT_FEAT_POWER:
2264 if (isp1760_hcd_ppc_is_set(hcd))
2265 isp1760_hcd_clear(hcd, PORT_POWER);
2266 break;
2267 case USB_PORT_FEAT_C_CONNECTION:
2268 isp1760_hcd_set(hcd, PORT_CSC);
2269 break;
2270 case USB_PORT_FEAT_C_OVER_CURRENT:
2271 /* XXX error ?*/
2272 break;
2273 case USB_PORT_FEAT_C_RESET:
2274 /* GetPortStatus clears reset */
2275 break;
2276 default:
2277 goto error;
2278 }
2279 isp1760_hcd_read(hcd, CMD_RUN);
2280 break;
2281 case GetHubDescriptor:
2282 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
2283 buf);
2284 break;
2285 case GetHubStatus:
2286 /* no hub-wide feature/status flags */
2287 memset(buf, 0, 4);
2288 break;
2289 case GetPortStatus:
2290 if (!wIndex || wIndex > ports)
2291 goto error;
2292 wIndex--;
2293 status = 0;
2294
2295 /* wPortChange bits */
2296 if (isp1760_hcd_is_set(hcd, PORT_CSC))
2297 status |= USB_PORT_STAT_C_CONNECTION << 16;
2298
2299 /* whoever resumes must GetPortStatus to complete it!! */
2300 if (isp1760_hcd_is_set(hcd, PORT_RESUME)) {
2301 dev_err(hcd->self.controller, "Port resume should be skipped.\n");
2302
2303 /* Remote Wakeup received? */
2304 if (!priv->reset_done) {
2305 /* resume signaling for 20 msec */
2306 priv->reset_done = jiffies
2307 + msecs_to_jiffies(20);
2308 /* check the port again */
2309 mod_timer(&hcd->rh_timer, priv->reset_done);
2310 }
2311
2312 /* resume completed? */
2313 else if (time_after_eq(jiffies,
2314 priv->reset_done)) {
2315 status |= USB_PORT_STAT_C_SUSPEND << 16;
2316 priv->reset_done = 0;
2317
2318 /* stop resume signaling */
2319 isp1760_hcd_clear(hcd, PORT_CSC);
2320
2321 retval = isp1760_hcd_clear_and_wait(hcd,
2322 PORT_RESUME, 2000);
2323 if (retval != 0) {
2324 dev_err(hcd->self.controller,
2325 "port %d resume error %d\n",
2326 wIndex + 1, retval);
2327 goto error;
2328 }
2329 }
2330 }
2331
2332 /* whoever resets must GetPortStatus to complete it!! */
2333 if (isp1760_hcd_is_set(hcd, PORT_RESET) &&
2334 time_after_eq(jiffies, priv->reset_done)) {
2335 status |= USB_PORT_STAT_C_RESET << 16;
2336 priv->reset_done = 0;
2337
2338 /* force reset to complete */
2339 /* REVISIT: some hardware needs 550+ usec to clear
2340 * this bit; seems too long to spin routinely...
2341 */
2342 retval = isp1760_hcd_clear_and_wait(hcd, PORT_RESET,
2343 750);
2344 if (retval != 0) {
2345 dev_err(hcd->self.controller, "port %d reset error %d\n",
2346 wIndex + 1, retval);
2347 goto error;
2348 }
2349
2350 /* see what we found out */
2351 check_reset_complete(hcd, wIndex);
2352 }
2353 /*
2354 * Even if OWNER is set, there's no harm letting hub_wq
2355 * see the wPortStatus values (they should all be 0 except
2356 * for PORT_POWER anyway).
2357 */
2358
2359 if (isp1760_hcd_is_set(hcd, PORT_OWNER))
2360 dev_err(hcd->self.controller, "PORT_OWNER is set\n");
2361
2362 if (isp1760_hcd_is_set(hcd, PORT_CONNECT)) {
2363 status |= USB_PORT_STAT_CONNECTION;
2364 /* status may be from integrated TT */
2365 status |= USB_PORT_STAT_HIGH_SPEED;
2366 }
2367 if (isp1760_hcd_is_set(hcd, PORT_PE))
2368 status |= USB_PORT_STAT_ENABLE;
2369 if (isp1760_hcd_is_set(hcd, PORT_SUSPEND) &&
2370 isp1760_hcd_is_set(hcd, PORT_RESUME))
2371 status |= USB_PORT_STAT_SUSPEND;
2372 if (isp1760_hcd_is_set(hcd, PORT_RESET))
2373 status |= USB_PORT_STAT_RESET;
2374 if (isp1760_hcd_is_set(hcd, PORT_POWER))
2375 status |= USB_PORT_STAT_POWER;
2376
2377 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
2378 break;
2379 case SetHubFeature:
2380 switch (wValue) {
2381 case C_HUB_LOCAL_POWER:
2382 case C_HUB_OVER_CURRENT:
2383 /* no hub-wide feature/status flags */
2384 break;
2385 default:
2386 goto error;
2387 }
2388 break;
2389 case SetPortFeature:
2390 wIndex &= 0xff;
2391 if (!wIndex || wIndex > ports)
2392 goto error;
2393 wIndex--;
2394
2395 if (isp1760_hcd_is_set(hcd, PORT_OWNER))
2396 break;
2397
2398 switch (wValue) {
2399 case USB_PORT_FEAT_ENABLE:
2400 isp1760_hcd_set(hcd, PORT_PE);
2401 break;
2402
2403 case USB_PORT_FEAT_SUSPEND:
2404 if (!isp1760_hcd_is_set(hcd, PORT_PE) ||
2405 isp1760_hcd_is_set(hcd, PORT_RESET))
2406 goto error;
2407
2408 isp1760_hcd_set(hcd, PORT_SUSPEND);
2409 break;
2410 case USB_PORT_FEAT_POWER:
2411 if (isp1760_hcd_ppc_is_set(hcd))
2412 isp1760_hcd_set(hcd, PORT_POWER);
2413 break;
2414 case USB_PORT_FEAT_RESET:
2415 if (isp1760_hcd_is_set(hcd, PORT_RESUME))
2416 goto error;
2417 /* line status bits may report this as low speed,
2418 * which can be fine if this root hub has a
2419 * transaction translator built in.
2420 */
2421 if ((isp1760_hcd_is_set(hcd, PORT_CONNECT) &&
2422 !isp1760_hcd_is_set(hcd, PORT_PE)) &&
2423 (isp1760_hcd_read(hcd, PORT_LSTATUS) == 1)) {
2424 isp1760_hcd_set(hcd, PORT_OWNER);
2425 } else {
2426 isp1760_hcd_set(hcd, PORT_RESET);
2427 isp1760_hcd_clear(hcd, PORT_PE);
2428
2429 /*
2430 * caller must wait, then call GetPortStatus
2431 * usb 2.0 spec says 50 ms resets on root
2432 */
2433 priv->reset_done = jiffies +
2434 msecs_to_jiffies(50);
2435 }
2436 break;
2437 default:
2438 goto error;
2439 }
2440 break;
2441
2442 default:
2443 error:
2444 /* "stall" on error */
2445 retval = -EPIPE;
2446 }
2447 spin_unlock_irqrestore(&priv->lock, flags);
2448 return retval;
2449 }
2450
isp1760_get_frame(struct usb_hcd * hcd)2451 static int isp1760_get_frame(struct usb_hcd *hcd)
2452 {
2453 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2454 u32 fr;
2455
2456 fr = isp1760_hcd_read(hcd, HC_FRINDEX);
2457 return (fr >> 3) % priv->periodic_size;
2458 }
2459
isp1760_stop(struct usb_hcd * hcd)2460 static void isp1760_stop(struct usb_hcd *hcd)
2461 {
2462 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2463
2464 del_timer(&errata2_timer);
2465
2466 isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
2467 NULL, 0);
2468 msleep(20);
2469
2470 spin_lock_irq(&priv->lock);
2471 ehci_reset(hcd);
2472 /* Disable IRQ */
2473 isp1760_hcd_clear(hcd, HW_GLOBAL_INTR_EN);
2474 spin_unlock_irq(&priv->lock);
2475
2476 isp1760_hcd_clear(hcd, FLAG_CF);
2477 }
2478
isp1760_shutdown(struct usb_hcd * hcd)2479 static void isp1760_shutdown(struct usb_hcd *hcd)
2480 {
2481 isp1760_stop(hcd);
2482
2483 isp1760_hcd_clear(hcd, HW_GLOBAL_INTR_EN);
2484
2485 isp1760_hcd_clear(hcd, CMD_RUN);
2486 }
2487
isp1760_clear_tt_buffer_complete(struct usb_hcd * hcd,struct usb_host_endpoint * ep)2488 static void isp1760_clear_tt_buffer_complete(struct usb_hcd *hcd,
2489 struct usb_host_endpoint *ep)
2490 {
2491 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2492 struct isp1760_qh *qh = ep->hcpriv;
2493 unsigned long spinflags;
2494
2495 if (!qh)
2496 return;
2497
2498 spin_lock_irqsave(&priv->lock, spinflags);
2499 qh->tt_buffer_dirty = 0;
2500 schedule_ptds(hcd);
2501 spin_unlock_irqrestore(&priv->lock, spinflags);
2502 }
2503
2504
2505 static const struct hc_driver isp1760_hc_driver = {
2506 .description = "isp1760-hcd",
2507 .product_desc = "NXP ISP1760 USB Host Controller",
2508 .hcd_priv_size = sizeof(struct isp1760_hcd *),
2509 .irq = isp1760_irq,
2510 .flags = HCD_MEMORY | HCD_USB2,
2511 .reset = isp1760_hc_setup,
2512 .start = isp1760_run,
2513 .stop = isp1760_stop,
2514 .shutdown = isp1760_shutdown,
2515 .urb_enqueue = isp1760_urb_enqueue,
2516 .urb_dequeue = isp1760_urb_dequeue,
2517 .endpoint_disable = isp1760_endpoint_disable,
2518 .get_frame_number = isp1760_get_frame,
2519 .hub_status_data = isp1760_hub_status_data,
2520 .hub_control = isp1760_hub_control,
2521 .clear_tt_buffer_complete = isp1760_clear_tt_buffer_complete,
2522 };
2523
isp1760_init_kmem_once(void)2524 int __init isp1760_init_kmem_once(void)
2525 {
2526 urb_listitem_cachep = kmem_cache_create("isp1760_urb_listitem",
2527 sizeof(struct urb_listitem), 0, SLAB_TEMPORARY |
2528 SLAB_MEM_SPREAD, NULL);
2529
2530 if (!urb_listitem_cachep)
2531 return -ENOMEM;
2532
2533 qtd_cachep = kmem_cache_create("isp1760_qtd",
2534 sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
2535 SLAB_MEM_SPREAD, NULL);
2536
2537 if (!qtd_cachep)
2538 goto destroy_urb_listitem;
2539
2540 qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh),
2541 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
2542
2543 if (!qh_cachep)
2544 goto destroy_qtd;
2545
2546 return 0;
2547
2548 destroy_qtd:
2549 kmem_cache_destroy(qtd_cachep);
2550
2551 destroy_urb_listitem:
2552 kmem_cache_destroy(urb_listitem_cachep);
2553
2554 return -ENOMEM;
2555 }
2556
isp1760_deinit_kmem_cache(void)2557 void isp1760_deinit_kmem_cache(void)
2558 {
2559 kmem_cache_destroy(qtd_cachep);
2560 kmem_cache_destroy(qh_cachep);
2561 kmem_cache_destroy(urb_listitem_cachep);
2562 }
2563
isp1760_hcd_register(struct isp1760_hcd * priv,struct resource * mem,int irq,unsigned long irqflags,struct device * dev)2564 int isp1760_hcd_register(struct isp1760_hcd *priv, struct resource *mem,
2565 int irq, unsigned long irqflags,
2566 struct device *dev)
2567 {
2568 const struct isp1760_memory_layout *mem_layout = priv->memory_layout;
2569 struct usb_hcd *hcd;
2570 int ret;
2571
2572 hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev));
2573 if (!hcd)
2574 return -ENOMEM;
2575
2576 *(struct isp1760_hcd **)hcd->hcd_priv = priv;
2577
2578 priv->hcd = hcd;
2579
2580 priv->atl_slots = kcalloc(mem_layout->slot_num,
2581 sizeof(struct isp1760_slotinfo), GFP_KERNEL);
2582 if (!priv->atl_slots) {
2583 ret = -ENOMEM;
2584 goto put_hcd;
2585 }
2586
2587 priv->int_slots = kcalloc(mem_layout->slot_num,
2588 sizeof(struct isp1760_slotinfo), GFP_KERNEL);
2589 if (!priv->int_slots) {
2590 ret = -ENOMEM;
2591 goto free_atl_slots;
2592 }
2593
2594 init_memory(priv);
2595
2596 hcd->irq = irq;
2597 hcd->rsrc_start = mem->start;
2598 hcd->rsrc_len = resource_size(mem);
2599
2600 /* This driver doesn't support wakeup requests */
2601 hcd->cant_recv_wakeups = 1;
2602
2603 ret = usb_add_hcd(hcd, irq, irqflags);
2604 if (ret)
2605 goto free_int_slots;
2606
2607 device_wakeup_enable(hcd->self.controller);
2608
2609 return 0;
2610
2611 free_int_slots:
2612 kfree(priv->int_slots);
2613 free_atl_slots:
2614 kfree(priv->atl_slots);
2615 put_hcd:
2616 usb_put_hcd(hcd);
2617 return ret;
2618 }
2619
isp1760_hcd_unregister(struct isp1760_hcd * priv)2620 void isp1760_hcd_unregister(struct isp1760_hcd *priv)
2621 {
2622 if (!priv->hcd)
2623 return;
2624
2625 usb_remove_hcd(priv->hcd);
2626 usb_put_hcd(priv->hcd);
2627 kfree(priv->atl_slots);
2628 kfree(priv->int_slots);
2629 }
2630