1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _LINUX_IRQ_H
3 #define _LINUX_IRQ_H
4
5 /*
6 * Please do not include this file in generic code. There is currently
7 * no requirement for any architecture to implement anything held
8 * within this file.
9 *
10 * Thanks. --rmk
11 */
12
13 #include <linux/cache.h>
14 #include <linux/spinlock.h>
15 #include <linux/cpumask.h>
16 #include <linux/irqhandler.h>
17 #include <linux/irqreturn.h>
18 #include <linux/irqnr.h>
19 #include <linux/topology.h>
20 #include <linux/io.h>
21 #include <linux/slab.h>
22
23 #include <asm/irq.h>
24 #include <asm/ptrace.h>
25 #include <asm/irq_regs.h>
26
27 struct seq_file;
28 struct module;
29 struct msi_msg;
30 struct irq_affinity_desc;
31 enum irqchip_irq_state;
32
33 /*
34 * IRQ line status.
35 *
36 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
37 *
38 * IRQ_TYPE_NONE - default, unspecified type
39 * IRQ_TYPE_EDGE_RISING - rising edge triggered
40 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
41 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
42 * IRQ_TYPE_LEVEL_HIGH - high level triggered
43 * IRQ_TYPE_LEVEL_LOW - low level triggered
44 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
45 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
46 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
47 * to setup the HW to a sane default (used
48 * by irqdomain map() callbacks to synchronize
49 * the HW state and SW flags for a newly
50 * allocated descriptor).
51 *
52 * IRQ_TYPE_PROBE - Special flag for probing in progress
53 *
54 * Bits which can be modified via irq_set/clear/modify_status_flags()
55 * IRQ_LEVEL - Interrupt is level type. Will be also
56 * updated in the code when the above trigger
57 * bits are modified via irq_set_irq_type()
58 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
59 * it from affinity setting
60 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
61 * IRQ_NOREQUEST - Interrupt cannot be requested via
62 * request_irq()
63 * IRQ_NOTHREAD - Interrupt cannot be threaded
64 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
65 * request/setup_irq()
66 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
67 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
68 * IRQ_NESTED_THREAD - Interrupt nests into another thread
69 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
70 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude
71 * it from the spurious interrupt detection
72 * mechanism and from core side polling.
73 * IRQ_DISABLE_UNLAZY - Disable lazy irq disable
74 * IRQ_HIDDEN - Don't show up in /proc/interrupts
75 * IRQ_NO_DEBUG - Exclude from note_interrupt() debugging
76 * IRQ_RAW - Skip tick management and irqtime accounting
77 */
78 enum {
79 IRQ_TYPE_NONE = 0x00000000,
80 IRQ_TYPE_EDGE_RISING = 0x00000001,
81 IRQ_TYPE_EDGE_FALLING = 0x00000002,
82 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
83 IRQ_TYPE_LEVEL_HIGH = 0x00000004,
84 IRQ_TYPE_LEVEL_LOW = 0x00000008,
85 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
86 IRQ_TYPE_SENSE_MASK = 0x0000000f,
87 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK,
88
89 IRQ_TYPE_PROBE = 0x00000010,
90
91 IRQ_LEVEL = (1 << 8),
92 IRQ_PER_CPU = (1 << 9),
93 IRQ_NOPROBE = (1 << 10),
94 IRQ_NOREQUEST = (1 << 11),
95 IRQ_NOAUTOEN = (1 << 12),
96 IRQ_NO_BALANCING = (1 << 13),
97 IRQ_MOVE_PCNTXT = (1 << 14),
98 IRQ_NESTED_THREAD = (1 << 15),
99 IRQ_NOTHREAD = (1 << 16),
100 IRQ_PER_CPU_DEVID = (1 << 17),
101 IRQ_IS_POLLED = (1 << 18),
102 IRQ_DISABLE_UNLAZY = (1 << 19),
103 IRQ_HIDDEN = (1 << 20),
104 IRQ_NO_DEBUG = (1 << 21),
105 IRQ_RAW = (1 << 22),
106 };
107
108 #define IRQF_MODIFY_MASK \
109 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
110 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
111 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
112 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY | IRQ_HIDDEN)
113
114 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
115
116 /*
117 * Return value for chip->irq_set_affinity()
118 *
119 * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity
120 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity
121 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
122 * support stacked irqchips, which indicates skipping
123 * all descendant irqchips.
124 */
125 enum {
126 IRQ_SET_MASK_OK = 0,
127 IRQ_SET_MASK_OK_NOCOPY,
128 IRQ_SET_MASK_OK_DONE,
129 };
130
131 struct msi_desc;
132 struct irq_domain;
133
134 /**
135 * struct irq_common_data - per irq data shared by all irqchips
136 * @state_use_accessors: status information for irq chip functions.
137 * Use accessor functions to deal with it
138 * @node: node index useful for balancing
139 * @handler_data: per-IRQ data for the irq_chip methods
140 * @affinity: IRQ affinity on SMP. If this is an IPI
141 * related irq, then this is the mask of the
142 * CPUs to which an IPI can be sent.
143 * @effective_affinity: The effective IRQ affinity on SMP as some irq
144 * chips do not allow multi CPU destinations.
145 * A subset of @affinity.
146 * @msi_desc: MSI descriptor
147 * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional.
148 */
149 struct irq_common_data {
150 unsigned int __private state_use_accessors;
151 #ifdef CONFIG_NUMA
152 unsigned int node;
153 #endif
154 void *handler_data;
155 struct msi_desc *msi_desc;
156 cpumask_var_t affinity;
157 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
158 cpumask_var_t effective_affinity;
159 #endif
160 #ifdef CONFIG_GENERIC_IRQ_IPI
161 unsigned int ipi_offset;
162 #endif
163 };
164
165 /**
166 * struct irq_data - per irq chip data passed down to chip functions
167 * @mask: precomputed bitmask for accessing the chip registers
168 * @irq: interrupt number
169 * @hwirq: hardware interrupt number, local to the interrupt domain
170 * @common: point to data shared by all irqchips
171 * @chip: low level interrupt hardware access
172 * @domain: Interrupt translation domain; responsible for mapping
173 * between hwirq number and linux irq number.
174 * @parent_data: pointer to parent struct irq_data to support hierarchy
175 * irq_domain
176 * @chip_data: platform-specific per-chip private data for the chip
177 * methods, to allow shared chip implementations
178 */
179 struct irq_data {
180 u32 mask;
181 unsigned int irq;
182 unsigned long hwirq;
183 struct irq_common_data *common;
184 struct irq_chip *chip;
185 struct irq_domain *domain;
186 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
187 struct irq_data *parent_data;
188 #endif
189 void *chip_data;
190 };
191
192 /*
193 * Bit masks for irq_common_data.state_use_accessors
194 *
195 * IRQD_TRIGGER_MASK - Mask for the trigger type bits
196 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
197 * IRQD_ACTIVATED - Interrupt has already been activated
198 * IRQD_NO_BALANCING - Balancing disabled for this IRQ
199 * IRQD_PER_CPU - Interrupt is per cpu
200 * IRQD_AFFINITY_SET - Interrupt affinity was set
201 * IRQD_LEVEL - Interrupt is level triggered
202 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
203 * from suspend
204 * IRQD_MOVE_PCNTXT - Interrupt can be moved in process
205 * context
206 * IRQD_IRQ_DISABLED - Disabled state of the interrupt
207 * IRQD_IRQ_MASKED - Masked state of the interrupt
208 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
209 * IRQD_WAKEUP_ARMED - Wakeup mode armed
210 * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU
211 * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel
212 * IRQD_IRQ_STARTED - Startup state of the interrupt
213 * IRQD_MANAGED_SHUTDOWN - Interrupt was shutdown due to empty affinity
214 * mask. Applies only to affinity managed irqs.
215 * IRQD_SINGLE_TARGET - IRQ allows only a single affinity target
216 * IRQD_DEFAULT_TRIGGER_SET - Expected trigger already been set
217 * IRQD_CAN_RESERVE - Can use reservation mode
218 * IRQD_MSI_NOMASK_QUIRK - Non-maskable MSI quirk for affinity change
219 * required
220 * IRQD_HANDLE_ENFORCE_IRQCTX - Enforce that handle_irq_*() is only invoked
221 * from actual interrupt context.
222 * IRQD_AFFINITY_ON_ACTIVATE - Affinity is set on activation. Don't call
223 * irq_chip::irq_set_affinity() when deactivated.
224 * IRQD_IRQ_ENABLED_ON_SUSPEND - Interrupt is enabled on suspend by irq pm if
225 * irqchip have flag IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND set.
226 */
227 enum {
228 IRQD_TRIGGER_MASK = 0xf,
229 IRQD_SETAFFINITY_PENDING = (1 << 8),
230 IRQD_ACTIVATED = (1 << 9),
231 IRQD_NO_BALANCING = (1 << 10),
232 IRQD_PER_CPU = (1 << 11),
233 IRQD_AFFINITY_SET = (1 << 12),
234 IRQD_LEVEL = (1 << 13),
235 IRQD_WAKEUP_STATE = (1 << 14),
236 IRQD_MOVE_PCNTXT = (1 << 15),
237 IRQD_IRQ_DISABLED = (1 << 16),
238 IRQD_IRQ_MASKED = (1 << 17),
239 IRQD_IRQ_INPROGRESS = (1 << 18),
240 IRQD_WAKEUP_ARMED = (1 << 19),
241 IRQD_FORWARDED_TO_VCPU = (1 << 20),
242 IRQD_AFFINITY_MANAGED = (1 << 21),
243 IRQD_IRQ_STARTED = (1 << 22),
244 IRQD_MANAGED_SHUTDOWN = (1 << 23),
245 IRQD_SINGLE_TARGET = (1 << 24),
246 IRQD_DEFAULT_TRIGGER_SET = (1 << 25),
247 IRQD_CAN_RESERVE = (1 << 26),
248 IRQD_MSI_NOMASK_QUIRK = (1 << 27),
249 IRQD_HANDLE_ENFORCE_IRQCTX = (1 << 28),
250 IRQD_AFFINITY_ON_ACTIVATE = (1 << 29),
251 IRQD_IRQ_ENABLED_ON_SUSPEND = (1 << 30),
252 };
253
254 #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors)
255
irqd_is_setaffinity_pending(struct irq_data * d)256 static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
257 {
258 return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING;
259 }
260
irqd_is_per_cpu(struct irq_data * d)261 static inline bool irqd_is_per_cpu(struct irq_data *d)
262 {
263 return __irqd_to_state(d) & IRQD_PER_CPU;
264 }
265
irqd_can_balance(struct irq_data * d)266 static inline bool irqd_can_balance(struct irq_data *d)
267 {
268 return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING));
269 }
270
irqd_affinity_was_set(struct irq_data * d)271 static inline bool irqd_affinity_was_set(struct irq_data *d)
272 {
273 return __irqd_to_state(d) & IRQD_AFFINITY_SET;
274 }
275
irqd_mark_affinity_was_set(struct irq_data * d)276 static inline void irqd_mark_affinity_was_set(struct irq_data *d)
277 {
278 __irqd_to_state(d) |= IRQD_AFFINITY_SET;
279 }
280
irqd_trigger_type_was_set(struct irq_data * d)281 static inline bool irqd_trigger_type_was_set(struct irq_data *d)
282 {
283 return __irqd_to_state(d) & IRQD_DEFAULT_TRIGGER_SET;
284 }
285
irqd_get_trigger_type(struct irq_data * d)286 static inline u32 irqd_get_trigger_type(struct irq_data *d)
287 {
288 return __irqd_to_state(d) & IRQD_TRIGGER_MASK;
289 }
290
291 /*
292 * Must only be called inside irq_chip.irq_set_type() functions or
293 * from the DT/ACPI setup code.
294 */
irqd_set_trigger_type(struct irq_data * d,u32 type)295 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
296 {
297 __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK;
298 __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK;
299 __irqd_to_state(d) |= IRQD_DEFAULT_TRIGGER_SET;
300 }
301
irqd_is_level_type(struct irq_data * d)302 static inline bool irqd_is_level_type(struct irq_data *d)
303 {
304 return __irqd_to_state(d) & IRQD_LEVEL;
305 }
306
307 /*
308 * Must only be called of irqchip.irq_set_affinity() or low level
309 * hierarchy domain allocation functions.
310 */
irqd_set_single_target(struct irq_data * d)311 static inline void irqd_set_single_target(struct irq_data *d)
312 {
313 __irqd_to_state(d) |= IRQD_SINGLE_TARGET;
314 }
315
irqd_is_single_target(struct irq_data * d)316 static inline bool irqd_is_single_target(struct irq_data *d)
317 {
318 return __irqd_to_state(d) & IRQD_SINGLE_TARGET;
319 }
320
irqd_set_handle_enforce_irqctx(struct irq_data * d)321 static inline void irqd_set_handle_enforce_irqctx(struct irq_data *d)
322 {
323 __irqd_to_state(d) |= IRQD_HANDLE_ENFORCE_IRQCTX;
324 }
325
irqd_is_handle_enforce_irqctx(struct irq_data * d)326 static inline bool irqd_is_handle_enforce_irqctx(struct irq_data *d)
327 {
328 return __irqd_to_state(d) & IRQD_HANDLE_ENFORCE_IRQCTX;
329 }
330
irqd_is_enabled_on_suspend(struct irq_data * d)331 static inline bool irqd_is_enabled_on_suspend(struct irq_data *d)
332 {
333 return __irqd_to_state(d) & IRQD_IRQ_ENABLED_ON_SUSPEND;
334 }
335
irqd_is_wakeup_set(struct irq_data * d)336 static inline bool irqd_is_wakeup_set(struct irq_data *d)
337 {
338 return __irqd_to_state(d) & IRQD_WAKEUP_STATE;
339 }
340
irqd_can_move_in_process_context(struct irq_data * d)341 static inline bool irqd_can_move_in_process_context(struct irq_data *d)
342 {
343 return __irqd_to_state(d) & IRQD_MOVE_PCNTXT;
344 }
345
irqd_irq_disabled(struct irq_data * d)346 static inline bool irqd_irq_disabled(struct irq_data *d)
347 {
348 return __irqd_to_state(d) & IRQD_IRQ_DISABLED;
349 }
350
irqd_irq_masked(struct irq_data * d)351 static inline bool irqd_irq_masked(struct irq_data *d)
352 {
353 return __irqd_to_state(d) & IRQD_IRQ_MASKED;
354 }
355
irqd_irq_inprogress(struct irq_data * d)356 static inline bool irqd_irq_inprogress(struct irq_data *d)
357 {
358 return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS;
359 }
360
irqd_is_wakeup_armed(struct irq_data * d)361 static inline bool irqd_is_wakeup_armed(struct irq_data *d)
362 {
363 return __irqd_to_state(d) & IRQD_WAKEUP_ARMED;
364 }
365
irqd_is_forwarded_to_vcpu(struct irq_data * d)366 static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d)
367 {
368 return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU;
369 }
370
irqd_set_forwarded_to_vcpu(struct irq_data * d)371 static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d)
372 {
373 __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU;
374 }
375
irqd_clr_forwarded_to_vcpu(struct irq_data * d)376 static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d)
377 {
378 __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU;
379 }
380
irqd_affinity_is_managed(struct irq_data * d)381 static inline bool irqd_affinity_is_managed(struct irq_data *d)
382 {
383 return __irqd_to_state(d) & IRQD_AFFINITY_MANAGED;
384 }
385
irqd_is_activated(struct irq_data * d)386 static inline bool irqd_is_activated(struct irq_data *d)
387 {
388 return __irqd_to_state(d) & IRQD_ACTIVATED;
389 }
390
irqd_set_activated(struct irq_data * d)391 static inline void irqd_set_activated(struct irq_data *d)
392 {
393 __irqd_to_state(d) |= IRQD_ACTIVATED;
394 }
395
irqd_clr_activated(struct irq_data * d)396 static inline void irqd_clr_activated(struct irq_data *d)
397 {
398 __irqd_to_state(d) &= ~IRQD_ACTIVATED;
399 }
400
irqd_is_started(struct irq_data * d)401 static inline bool irqd_is_started(struct irq_data *d)
402 {
403 return __irqd_to_state(d) & IRQD_IRQ_STARTED;
404 }
405
irqd_is_managed_and_shutdown(struct irq_data * d)406 static inline bool irqd_is_managed_and_shutdown(struct irq_data *d)
407 {
408 return __irqd_to_state(d) & IRQD_MANAGED_SHUTDOWN;
409 }
410
irqd_set_can_reserve(struct irq_data * d)411 static inline void irqd_set_can_reserve(struct irq_data *d)
412 {
413 __irqd_to_state(d) |= IRQD_CAN_RESERVE;
414 }
415
irqd_clr_can_reserve(struct irq_data * d)416 static inline void irqd_clr_can_reserve(struct irq_data *d)
417 {
418 __irqd_to_state(d) &= ~IRQD_CAN_RESERVE;
419 }
420
irqd_can_reserve(struct irq_data * d)421 static inline bool irqd_can_reserve(struct irq_data *d)
422 {
423 return __irqd_to_state(d) & IRQD_CAN_RESERVE;
424 }
425
irqd_set_msi_nomask_quirk(struct irq_data * d)426 static inline void irqd_set_msi_nomask_quirk(struct irq_data *d)
427 {
428 __irqd_to_state(d) |= IRQD_MSI_NOMASK_QUIRK;
429 }
430
irqd_clr_msi_nomask_quirk(struct irq_data * d)431 static inline void irqd_clr_msi_nomask_quirk(struct irq_data *d)
432 {
433 __irqd_to_state(d) &= ~IRQD_MSI_NOMASK_QUIRK;
434 }
435
irqd_msi_nomask_quirk(struct irq_data * d)436 static inline bool irqd_msi_nomask_quirk(struct irq_data *d)
437 {
438 return __irqd_to_state(d) & IRQD_MSI_NOMASK_QUIRK;
439 }
440
irqd_set_affinity_on_activate(struct irq_data * d)441 static inline void irqd_set_affinity_on_activate(struct irq_data *d)
442 {
443 __irqd_to_state(d) |= IRQD_AFFINITY_ON_ACTIVATE;
444 }
445
irqd_affinity_on_activate(struct irq_data * d)446 static inline bool irqd_affinity_on_activate(struct irq_data *d)
447 {
448 return __irqd_to_state(d) & IRQD_AFFINITY_ON_ACTIVATE;
449 }
450
451 #undef __irqd_to_state
452
irqd_to_hwirq(struct irq_data * d)453 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
454 {
455 return d->hwirq;
456 }
457
458 /**
459 * struct irq_chip - hardware interrupt chip descriptor
460 *
461 * @parent_device: pointer to parent device for irqchip
462 * @name: name for /proc/interrupts
463 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
464 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
465 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
466 * @irq_disable: disable the interrupt
467 * @irq_ack: start of a new interrupt
468 * @irq_mask: mask an interrupt source
469 * @irq_mask_ack: ack and mask an interrupt source
470 * @irq_unmask: unmask an interrupt source
471 * @irq_eoi: end of interrupt
472 * @irq_set_affinity: Set the CPU affinity on SMP machines. If the force
473 * argument is true, it tells the driver to
474 * unconditionally apply the affinity setting. Sanity
475 * checks against the supplied affinity mask are not
476 * required. This is used for CPU hotplug where the
477 * target CPU is not yet set in the cpu_online_mask.
478 * @irq_retrigger: resend an IRQ to the CPU
479 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
480 * @irq_set_wake: enable/disable power-management wake-on of an IRQ
481 * @irq_bus_lock: function to lock access to slow bus (i2c) chips
482 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
483 * @irq_cpu_online: configure an interrupt source for a secondary CPU
484 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
485 * @irq_suspend: function called from core code on suspend once per
486 * chip, when one or more interrupts are installed
487 * @irq_resume: function called from core code on resume once per chip,
488 * when one ore more interrupts are installed
489 * @irq_pm_shutdown: function called from core code on shutdown once per chip
490 * @irq_calc_mask: Optional function to set irq_data.mask for special cases
491 * @irq_print_chip: optional to print special chip info in show_interrupts
492 * @irq_request_resources: optional to request resources before calling
493 * any other callback related to this irq
494 * @irq_release_resources: optional to release resources acquired with
495 * irq_request_resources
496 * @irq_compose_msi_msg: optional to compose message content for MSI
497 * @irq_write_msi_msg: optional to write message content for MSI
498 * @irq_get_irqchip_state: return the internal state of an interrupt
499 * @irq_set_irqchip_state: set the internal state of a interrupt
500 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine
501 * @ipi_send_single: send a single IPI to destination cpus
502 * @ipi_send_mask: send an IPI to destination cpus in cpumask
503 * @irq_nmi_setup: function called from core code before enabling an NMI
504 * @irq_nmi_teardown: function called from core code after disabling an NMI
505 * @flags: chip specific flags
506 */
507 struct irq_chip {
508 struct device *parent_device;
509 const char *name;
510 unsigned int (*irq_startup)(struct irq_data *data);
511 void (*irq_shutdown)(struct irq_data *data);
512 void (*irq_enable)(struct irq_data *data);
513 void (*irq_disable)(struct irq_data *data);
514
515 void (*irq_ack)(struct irq_data *data);
516 void (*irq_mask)(struct irq_data *data);
517 void (*irq_mask_ack)(struct irq_data *data);
518 void (*irq_unmask)(struct irq_data *data);
519 void (*irq_eoi)(struct irq_data *data);
520
521 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
522 int (*irq_retrigger)(struct irq_data *data);
523 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
524 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
525
526 void (*irq_bus_lock)(struct irq_data *data);
527 void (*irq_bus_sync_unlock)(struct irq_data *data);
528
529 void (*irq_cpu_online)(struct irq_data *data);
530 void (*irq_cpu_offline)(struct irq_data *data);
531
532 void (*irq_suspend)(struct irq_data *data);
533 void (*irq_resume)(struct irq_data *data);
534 void (*irq_pm_shutdown)(struct irq_data *data);
535
536 void (*irq_calc_mask)(struct irq_data *data);
537
538 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
539 int (*irq_request_resources)(struct irq_data *data);
540 void (*irq_release_resources)(struct irq_data *data);
541
542 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg);
543 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg);
544
545 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state);
546 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state);
547
548 int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info);
549
550 void (*ipi_send_single)(struct irq_data *data, unsigned int cpu);
551 void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest);
552
553 int (*irq_nmi_setup)(struct irq_data *data);
554 void (*irq_nmi_teardown)(struct irq_data *data);
555
556 unsigned long flags;
557 };
558
559 /*
560 * irq_chip specific flags
561 *
562 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
563 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
564 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
565 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
566 * when irq enabled
567 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
568 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask
569 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode
570 * IRQCHIP_SUPPORTS_LEVEL_MSI: Chip can provide two doorbells for Level MSIs
571 * IRQCHIP_SUPPORTS_NMI: Chip can deliver NMIs, only for root irqchips
572 * IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND: Invokes __enable_irq()/__disable_irq() for wake irqs
573 * in the suspend path if they are in disabled state
574 * IRQCHIP_AFFINITY_PRE_STARTUP: Default affinity update before startup
575 */
576 enum {
577 IRQCHIP_SET_TYPE_MASKED = (1 << 0),
578 IRQCHIP_EOI_IF_HANDLED = (1 << 1),
579 IRQCHIP_MASK_ON_SUSPEND = (1 << 2),
580 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3),
581 IRQCHIP_SKIP_SET_WAKE = (1 << 4),
582 IRQCHIP_ONESHOT_SAFE = (1 << 5),
583 IRQCHIP_EOI_THREADED = (1 << 6),
584 IRQCHIP_SUPPORTS_LEVEL_MSI = (1 << 7),
585 IRQCHIP_SUPPORTS_NMI = (1 << 8),
586 IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND = (1 << 9),
587 IRQCHIP_AFFINITY_PRE_STARTUP = (1 << 10),
588 };
589
590 #include <linux/irqdesc.h>
591
592 /*
593 * Pick up the arch-dependent methods:
594 */
595 #include <asm/hw_irq.h>
596
597 #ifndef NR_IRQS_LEGACY
598 # define NR_IRQS_LEGACY 0
599 #endif
600
601 #ifndef ARCH_IRQ_INIT_FLAGS
602 # define ARCH_IRQ_INIT_FLAGS 0
603 #endif
604
605 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
606
607 struct irqaction;
608 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
609 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act);
610
611 extern void irq_cpu_online(void);
612 extern void irq_cpu_offline(void);
613 extern int irq_set_affinity_locked(struct irq_data *data,
614 const struct cpumask *cpumask, bool force);
615 extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info);
616
617 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_IRQ_MIGRATION)
618 extern void irq_migrate_all_off_this_cpu(void);
619 extern int irq_affinity_online_cpu(unsigned int cpu);
620 #else
621 # define irq_affinity_online_cpu NULL
622 #endif
623
624 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
625 void __irq_move_irq(struct irq_data *data);
irq_move_irq(struct irq_data * data)626 static inline void irq_move_irq(struct irq_data *data)
627 {
628 if (unlikely(irqd_is_setaffinity_pending(data)))
629 __irq_move_irq(data);
630 }
631 void irq_move_masked_irq(struct irq_data *data);
632 void irq_force_complete_move(struct irq_desc *desc);
633 #else
irq_move_irq(struct irq_data * data)634 static inline void irq_move_irq(struct irq_data *data) { }
irq_move_masked_irq(struct irq_data * data)635 static inline void irq_move_masked_irq(struct irq_data *data) { }
irq_force_complete_move(struct irq_desc * desc)636 static inline void irq_force_complete_move(struct irq_desc *desc) { }
637 #endif
638
639 extern int no_irq_affinity;
640
641 #ifdef CONFIG_HARDIRQS_SW_RESEND
642 int irq_set_parent(int irq, int parent_irq);
643 #else
irq_set_parent(int irq,int parent_irq)644 static inline int irq_set_parent(int irq, int parent_irq)
645 {
646 return 0;
647 }
648 #endif
649
650 /*
651 * Built-in IRQ handlers for various IRQ types,
652 * callable via desc->handle_irq()
653 */
654 extern void handle_level_irq(struct irq_desc *desc);
655 extern void handle_fasteoi_irq(struct irq_desc *desc);
656 extern void handle_edge_irq(struct irq_desc *desc);
657 extern void handle_edge_eoi_irq(struct irq_desc *desc);
658 extern void handle_simple_irq(struct irq_desc *desc);
659 extern void handle_untracked_irq(struct irq_desc *desc);
660 extern void handle_percpu_irq(struct irq_desc *desc);
661 extern void handle_percpu_devid_irq(struct irq_desc *desc);
662 extern void handle_bad_irq(struct irq_desc *desc);
663 extern void handle_nested_irq(unsigned int irq);
664
665 extern void handle_fasteoi_nmi(struct irq_desc *desc);
666 extern void handle_percpu_devid_fasteoi_nmi(struct irq_desc *desc);
667
668 extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg);
669 extern int irq_chip_pm_get(struct irq_data *data);
670 extern int irq_chip_pm_put(struct irq_data *data);
671 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
672 extern void handle_fasteoi_ack_irq(struct irq_desc *desc);
673 extern void handle_fasteoi_mask_irq(struct irq_desc *desc);
674 extern int irq_chip_set_parent_state(struct irq_data *data,
675 enum irqchip_irq_state which,
676 bool val);
677 extern int irq_chip_get_parent_state(struct irq_data *data,
678 enum irqchip_irq_state which,
679 bool *state);
680 extern void irq_chip_enable_parent(struct irq_data *data);
681 extern void irq_chip_disable_parent(struct irq_data *data);
682 extern void irq_chip_ack_parent(struct irq_data *data);
683 extern int irq_chip_retrigger_hierarchy(struct irq_data *data);
684 extern void irq_chip_mask_parent(struct irq_data *data);
685 extern void irq_chip_mask_ack_parent(struct irq_data *data);
686 extern void irq_chip_unmask_parent(struct irq_data *data);
687 extern void irq_chip_eoi_parent(struct irq_data *data);
688 extern int irq_chip_set_affinity_parent(struct irq_data *data,
689 const struct cpumask *dest,
690 bool force);
691 extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
692 extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data,
693 void *vcpu_info);
694 extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type);
695 extern int irq_chip_request_resources_parent(struct irq_data *data);
696 extern void irq_chip_release_resources_parent(struct irq_data *data);
697 #endif
698
699 /* Handling of unhandled and spurious interrupts: */
700 extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret);
701
702
703 /* Enable/disable irq debugging output: */
704 extern int noirqdebug_setup(char *str);
705
706 /* Checks whether the interrupt can be requested by request_irq(): */
707 extern int can_request_irq(unsigned int irq, unsigned long irqflags);
708
709 /* Dummy irq-chip implementations: */
710 extern struct irq_chip no_irq_chip;
711 extern struct irq_chip dummy_irq_chip;
712
713 extern void
714 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
715 irq_flow_handler_t handle, const char *name);
716
irq_set_chip_and_handler(unsigned int irq,struct irq_chip * chip,irq_flow_handler_t handle)717 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
718 irq_flow_handler_t handle)
719 {
720 irq_set_chip_and_handler_name(irq, chip, handle, NULL);
721 }
722
723 extern int irq_set_percpu_devid(unsigned int irq);
724 extern int irq_set_percpu_devid_partition(unsigned int irq,
725 const struct cpumask *affinity);
726 extern int irq_get_percpu_devid_partition(unsigned int irq,
727 struct cpumask *affinity);
728
729 extern void
730 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
731 const char *name);
732
733 static inline void
irq_set_handler(unsigned int irq,irq_flow_handler_t handle)734 irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
735 {
736 __irq_set_handler(irq, handle, 0, NULL);
737 }
738
739 /*
740 * Set a highlevel chained flow handler for a given IRQ.
741 * (a chained handler is automatically enabled and set to
742 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
743 */
744 static inline void
irq_set_chained_handler(unsigned int irq,irq_flow_handler_t handle)745 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
746 {
747 __irq_set_handler(irq, handle, 1, NULL);
748 }
749
750 /*
751 * Set a highlevel chained flow handler and its data for a given IRQ.
752 * (a chained handler is automatically enabled and set to
753 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
754 */
755 void
756 irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
757 void *data);
758
759 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
760
irq_set_status_flags(unsigned int irq,unsigned long set)761 static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
762 {
763 irq_modify_status(irq, 0, set);
764 }
765
irq_clear_status_flags(unsigned int irq,unsigned long clr)766 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
767 {
768 irq_modify_status(irq, clr, 0);
769 }
770
irq_set_noprobe(unsigned int irq)771 static inline void irq_set_noprobe(unsigned int irq)
772 {
773 irq_modify_status(irq, 0, IRQ_NOPROBE);
774 }
775
irq_set_probe(unsigned int irq)776 static inline void irq_set_probe(unsigned int irq)
777 {
778 irq_modify_status(irq, IRQ_NOPROBE, 0);
779 }
780
irq_set_nothread(unsigned int irq)781 static inline void irq_set_nothread(unsigned int irq)
782 {
783 irq_modify_status(irq, 0, IRQ_NOTHREAD);
784 }
785
irq_set_thread(unsigned int irq)786 static inline void irq_set_thread(unsigned int irq)
787 {
788 irq_modify_status(irq, IRQ_NOTHREAD, 0);
789 }
790
irq_set_nested_thread(unsigned int irq,bool nest)791 static inline void irq_set_nested_thread(unsigned int irq, bool nest)
792 {
793 if (nest)
794 irq_set_status_flags(irq, IRQ_NESTED_THREAD);
795 else
796 irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
797 }
798
irq_set_percpu_devid_flags(unsigned int irq)799 static inline void irq_set_percpu_devid_flags(unsigned int irq)
800 {
801 irq_set_status_flags(irq,
802 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
803 IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
804 }
805
806 /* Set/get chip/data for an IRQ: */
807 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip);
808 extern int irq_set_handler_data(unsigned int irq, void *data);
809 extern int irq_set_chip_data(unsigned int irq, void *data);
810 extern int irq_set_irq_type(unsigned int irq, unsigned int type);
811 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
812 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
813 struct msi_desc *entry);
814 extern struct irq_data *irq_get_irq_data(unsigned int irq);
815
irq_get_chip(unsigned int irq)816 static inline struct irq_chip *irq_get_chip(unsigned int irq)
817 {
818 struct irq_data *d = irq_get_irq_data(irq);
819 return d ? d->chip : NULL;
820 }
821
irq_data_get_irq_chip(struct irq_data * d)822 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
823 {
824 return d->chip;
825 }
826
irq_get_chip_data(unsigned int irq)827 static inline void *irq_get_chip_data(unsigned int irq)
828 {
829 struct irq_data *d = irq_get_irq_data(irq);
830 return d ? d->chip_data : NULL;
831 }
832
irq_data_get_irq_chip_data(struct irq_data * d)833 static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
834 {
835 return d->chip_data;
836 }
837
irq_get_handler_data(unsigned int irq)838 static inline void *irq_get_handler_data(unsigned int irq)
839 {
840 struct irq_data *d = irq_get_irq_data(irq);
841 return d ? d->common->handler_data : NULL;
842 }
843
irq_data_get_irq_handler_data(struct irq_data * d)844 static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
845 {
846 return d->common->handler_data;
847 }
848
irq_get_msi_desc(unsigned int irq)849 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
850 {
851 struct irq_data *d = irq_get_irq_data(irq);
852 return d ? d->common->msi_desc : NULL;
853 }
854
irq_data_get_msi_desc(struct irq_data * d)855 static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d)
856 {
857 return d->common->msi_desc;
858 }
859
irq_get_trigger_type(unsigned int irq)860 static inline u32 irq_get_trigger_type(unsigned int irq)
861 {
862 struct irq_data *d = irq_get_irq_data(irq);
863 return d ? irqd_get_trigger_type(d) : 0;
864 }
865
irq_common_data_get_node(struct irq_common_data * d)866 static inline int irq_common_data_get_node(struct irq_common_data *d)
867 {
868 #ifdef CONFIG_NUMA
869 return d->node;
870 #else
871 return 0;
872 #endif
873 }
874
irq_data_get_node(struct irq_data * d)875 static inline int irq_data_get_node(struct irq_data *d)
876 {
877 return irq_common_data_get_node(d->common);
878 }
879
irq_data_get_affinity_mask(struct irq_data * d)880 static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d)
881 {
882 return d->common->affinity;
883 }
884
irq_data_update_affinity(struct irq_data * d,const struct cpumask * m)885 static inline void irq_data_update_affinity(struct irq_data *d,
886 const struct cpumask *m)
887 {
888 cpumask_copy(d->common->affinity, m);
889 }
890
irq_get_affinity_mask(int irq)891 static inline struct cpumask *irq_get_affinity_mask(int irq)
892 {
893 struct irq_data *d = irq_get_irq_data(irq);
894
895 return d ? irq_data_get_affinity_mask(d) : NULL;
896 }
897
898 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
899 static inline
irq_data_get_effective_affinity_mask(struct irq_data * d)900 struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
901 {
902 return d->common->effective_affinity;
903 }
irq_data_update_effective_affinity(struct irq_data * d,const struct cpumask * m)904 static inline void irq_data_update_effective_affinity(struct irq_data *d,
905 const struct cpumask *m)
906 {
907 cpumask_copy(d->common->effective_affinity, m);
908 }
909 #else
irq_data_update_effective_affinity(struct irq_data * d,const struct cpumask * m)910 static inline void irq_data_update_effective_affinity(struct irq_data *d,
911 const struct cpumask *m)
912 {
913 }
914 static inline
irq_data_get_effective_affinity_mask(struct irq_data * d)915 struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
916 {
917 return irq_data_get_affinity_mask(d);
918 }
919 #endif
920
irq_get_effective_affinity_mask(unsigned int irq)921 static inline struct cpumask *irq_get_effective_affinity_mask(unsigned int irq)
922 {
923 struct irq_data *d = irq_get_irq_data(irq);
924
925 return d ? irq_data_get_effective_affinity_mask(d) : NULL;
926 }
927
928 unsigned int arch_dynirq_lower_bound(unsigned int from);
929
930 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
931 struct module *owner,
932 const struct irq_affinity_desc *affinity);
933
934 int __devm_irq_alloc_descs(struct device *dev, int irq, unsigned int from,
935 unsigned int cnt, int node, struct module *owner,
936 const struct irq_affinity_desc *affinity);
937
938 /* use macros to avoid needing export.h for THIS_MODULE */
939 #define irq_alloc_descs(irq, from, cnt, node) \
940 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL)
941
942 #define irq_alloc_desc(node) \
943 irq_alloc_descs(-1, 1, 1, node)
944
945 #define irq_alloc_desc_at(at, node) \
946 irq_alloc_descs(at, at, 1, node)
947
948 #define irq_alloc_desc_from(from, node) \
949 irq_alloc_descs(-1, from, 1, node)
950
951 #define irq_alloc_descs_from(from, cnt, node) \
952 irq_alloc_descs(-1, from, cnt, node)
953
954 #define devm_irq_alloc_descs(dev, irq, from, cnt, node) \
955 __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL)
956
957 #define devm_irq_alloc_desc(dev, node) \
958 devm_irq_alloc_descs(dev, -1, 1, 1, node)
959
960 #define devm_irq_alloc_desc_at(dev, at, node) \
961 devm_irq_alloc_descs(dev, at, at, 1, node)
962
963 #define devm_irq_alloc_desc_from(dev, from, node) \
964 devm_irq_alloc_descs(dev, -1, from, 1, node)
965
966 #define devm_irq_alloc_descs_from(dev, from, cnt, node) \
967 devm_irq_alloc_descs(dev, -1, from, cnt, node)
968
969 void irq_free_descs(unsigned int irq, unsigned int cnt);
irq_free_desc(unsigned int irq)970 static inline void irq_free_desc(unsigned int irq)
971 {
972 irq_free_descs(irq, 1);
973 }
974
975 #ifdef CONFIG_GENERIC_IRQ_LEGACY
976 void irq_init_desc(unsigned int irq);
977 #endif
978
979 /**
980 * struct irq_chip_regs - register offsets for struct irq_gci
981 * @enable: Enable register offset to reg_base
982 * @disable: Disable register offset to reg_base
983 * @mask: Mask register offset to reg_base
984 * @ack: Ack register offset to reg_base
985 * @eoi: Eoi register offset to reg_base
986 * @type: Type configuration register offset to reg_base
987 * @polarity: Polarity configuration register offset to reg_base
988 */
989 struct irq_chip_regs {
990 unsigned long enable;
991 unsigned long disable;
992 unsigned long mask;
993 unsigned long ack;
994 unsigned long eoi;
995 unsigned long type;
996 unsigned long polarity;
997 };
998
999 /**
1000 * struct irq_chip_type - Generic interrupt chip instance for a flow type
1001 * @chip: The real interrupt chip which provides the callbacks
1002 * @regs: Register offsets for this chip
1003 * @handler: Flow handler associated with this chip
1004 * @type: Chip can handle these flow types
1005 * @mask_cache_priv: Cached mask register private to the chip type
1006 * @mask_cache: Pointer to cached mask register
1007 *
1008 * A irq_generic_chip can have several instances of irq_chip_type when
1009 * it requires different functions and register offsets for different
1010 * flow types.
1011 */
1012 struct irq_chip_type {
1013 struct irq_chip chip;
1014 struct irq_chip_regs regs;
1015 irq_flow_handler_t handler;
1016 u32 type;
1017 u32 mask_cache_priv;
1018 u32 *mask_cache;
1019 };
1020
1021 /**
1022 * struct irq_chip_generic - Generic irq chip data structure
1023 * @lock: Lock to protect register and cache data access
1024 * @reg_base: Register base address (virtual)
1025 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL)
1026 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL)
1027 * @suspend: Function called from core code on suspend once per
1028 * chip; can be useful instead of irq_chip::suspend to
1029 * handle chip details even when no interrupts are in use
1030 * @resume: Function called from core code on resume once per chip;
1031 * can be useful instead of irq_chip::suspend to handle
1032 * chip details even when no interrupts are in use
1033 * @irq_base: Interrupt base nr for this chip
1034 * @irq_cnt: Number of interrupts handled by this chip
1035 * @mask_cache: Cached mask register shared between all chip types
1036 * @type_cache: Cached type register
1037 * @polarity_cache: Cached polarity register
1038 * @wake_enabled: Interrupt can wakeup from suspend
1039 * @wake_active: Interrupt is marked as an wakeup from suspend source
1040 * @num_ct: Number of available irq_chip_type instances (usually 1)
1041 * @private: Private data for non generic chip callbacks
1042 * @installed: bitfield to denote installed interrupts
1043 * @unused: bitfield to denote unused interrupts
1044 * @domain: irq domain pointer
1045 * @list: List head for keeping track of instances
1046 * @chip_types: Array of interrupt irq_chip_types
1047 *
1048 * Note, that irq_chip_generic can have multiple irq_chip_type
1049 * implementations which can be associated to a particular irq line of
1050 * an irq_chip_generic instance. That allows to share and protect
1051 * state in an irq_chip_generic instance when we need to implement
1052 * different flow mechanisms (level/edge) for it.
1053 */
1054 struct irq_chip_generic {
1055 raw_spinlock_t lock;
1056 void __iomem *reg_base;
1057 u32 (*reg_readl)(void __iomem *addr);
1058 void (*reg_writel)(u32 val, void __iomem *addr);
1059 void (*suspend)(struct irq_chip_generic *gc);
1060 void (*resume)(struct irq_chip_generic *gc);
1061 unsigned int irq_base;
1062 unsigned int irq_cnt;
1063 u32 mask_cache;
1064 u32 type_cache;
1065 u32 polarity_cache;
1066 u32 wake_enabled;
1067 u32 wake_active;
1068 unsigned int num_ct;
1069 void *private;
1070 unsigned long installed;
1071 unsigned long unused;
1072 struct irq_domain *domain;
1073 struct list_head list;
1074 struct irq_chip_type chip_types[];
1075 };
1076
1077 /**
1078 * enum irq_gc_flags - Initialization flags for generic irq chips
1079 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
1080 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
1081 * irq chips which need to call irq_set_wake() on
1082 * the parent irq. Usually GPIO implementations
1083 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
1084 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
1085 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE)
1086 */
1087 enum irq_gc_flags {
1088 IRQ_GC_INIT_MASK_CACHE = 1 << 0,
1089 IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
1090 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
1091 IRQ_GC_NO_MASK = 1 << 3,
1092 IRQ_GC_BE_IO = 1 << 4,
1093 };
1094
1095 /*
1096 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
1097 * @irqs_per_chip: Number of interrupts per chip
1098 * @num_chips: Number of chips
1099 * @irq_flags_to_set: IRQ* flags to set on irq setup
1100 * @irq_flags_to_clear: IRQ* flags to clear on irq setup
1101 * @gc_flags: Generic chip specific setup flags
1102 * @gc: Array of pointers to generic interrupt chips
1103 */
1104 struct irq_domain_chip_generic {
1105 unsigned int irqs_per_chip;
1106 unsigned int num_chips;
1107 unsigned int irq_flags_to_clear;
1108 unsigned int irq_flags_to_set;
1109 enum irq_gc_flags gc_flags;
1110 struct irq_chip_generic *gc[];
1111 };
1112
1113 /* Generic chip callback functions */
1114 void irq_gc_noop(struct irq_data *d);
1115 void irq_gc_mask_disable_reg(struct irq_data *d);
1116 void irq_gc_mask_set_bit(struct irq_data *d);
1117 void irq_gc_mask_clr_bit(struct irq_data *d);
1118 void irq_gc_unmask_enable_reg(struct irq_data *d);
1119 void irq_gc_ack_set_bit(struct irq_data *d);
1120 void irq_gc_ack_clr_bit(struct irq_data *d);
1121 void irq_gc_mask_disable_and_ack_set(struct irq_data *d);
1122 void irq_gc_eoi(struct irq_data *d);
1123 int irq_gc_set_wake(struct irq_data *d, unsigned int on);
1124
1125 /* Setup functions for irq_chip_generic */
1126 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
1127 irq_hw_number_t hw_irq);
1128 struct irq_chip_generic *
1129 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
1130 void __iomem *reg_base, irq_flow_handler_t handler);
1131 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
1132 enum irq_gc_flags flags, unsigned int clr,
1133 unsigned int set);
1134 int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
1135 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
1136 unsigned int clr, unsigned int set);
1137
1138 struct irq_chip_generic *
1139 devm_irq_alloc_generic_chip(struct device *dev, const char *name, int num_ct,
1140 unsigned int irq_base, void __iomem *reg_base,
1141 irq_flow_handler_t handler);
1142 int devm_irq_setup_generic_chip(struct device *dev, struct irq_chip_generic *gc,
1143 u32 msk, enum irq_gc_flags flags,
1144 unsigned int clr, unsigned int set);
1145
1146 struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq);
1147
1148 int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
1149 int num_ct, const char *name,
1150 irq_flow_handler_t handler,
1151 unsigned int clr, unsigned int set,
1152 enum irq_gc_flags flags);
1153
1154 #define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \
1155 handler, clr, set, flags) \
1156 ({ \
1157 MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \
1158 __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\
1159 handler, clr, set, flags); \
1160 })
1161
irq_free_generic_chip(struct irq_chip_generic * gc)1162 static inline void irq_free_generic_chip(struct irq_chip_generic *gc)
1163 {
1164 kfree(gc);
1165 }
1166
irq_destroy_generic_chip(struct irq_chip_generic * gc,u32 msk,unsigned int clr,unsigned int set)1167 static inline void irq_destroy_generic_chip(struct irq_chip_generic *gc,
1168 u32 msk, unsigned int clr,
1169 unsigned int set)
1170 {
1171 irq_remove_generic_chip(gc, msk, clr, set);
1172 irq_free_generic_chip(gc);
1173 }
1174
irq_data_get_chip_type(struct irq_data * d)1175 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
1176 {
1177 return container_of(d->chip, struct irq_chip_type, chip);
1178 }
1179
1180 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
1181
1182 #ifdef CONFIG_SMP
irq_gc_lock(struct irq_chip_generic * gc)1183 static inline void irq_gc_lock(struct irq_chip_generic *gc)
1184 {
1185 raw_spin_lock(&gc->lock);
1186 }
1187
irq_gc_unlock(struct irq_chip_generic * gc)1188 static inline void irq_gc_unlock(struct irq_chip_generic *gc)
1189 {
1190 raw_spin_unlock(&gc->lock);
1191 }
1192 #else
irq_gc_lock(struct irq_chip_generic * gc)1193 static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
irq_gc_unlock(struct irq_chip_generic * gc)1194 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
1195 #endif
1196
1197 /*
1198 * The irqsave variants are for usage in non interrupt code. Do not use
1199 * them in irq_chip callbacks. Use irq_gc_lock() instead.
1200 */
1201 #define irq_gc_lock_irqsave(gc, flags) \
1202 raw_spin_lock_irqsave(&(gc)->lock, flags)
1203
1204 #define irq_gc_unlock_irqrestore(gc, flags) \
1205 raw_spin_unlock_irqrestore(&(gc)->lock, flags)
1206
irq_reg_writel(struct irq_chip_generic * gc,u32 val,int reg_offset)1207 static inline void irq_reg_writel(struct irq_chip_generic *gc,
1208 u32 val, int reg_offset)
1209 {
1210 if (gc->reg_writel)
1211 gc->reg_writel(val, gc->reg_base + reg_offset);
1212 else
1213 writel(val, gc->reg_base + reg_offset);
1214 }
1215
irq_reg_readl(struct irq_chip_generic * gc,int reg_offset)1216 static inline u32 irq_reg_readl(struct irq_chip_generic *gc,
1217 int reg_offset)
1218 {
1219 if (gc->reg_readl)
1220 return gc->reg_readl(gc->reg_base + reg_offset);
1221 else
1222 return readl(gc->reg_base + reg_offset);
1223 }
1224
1225 struct irq_matrix;
1226 struct irq_matrix *irq_alloc_matrix(unsigned int matrix_bits,
1227 unsigned int alloc_start,
1228 unsigned int alloc_end);
1229 void irq_matrix_online(struct irq_matrix *m);
1230 void irq_matrix_offline(struct irq_matrix *m);
1231 void irq_matrix_assign_system(struct irq_matrix *m, unsigned int bit, bool replace);
1232 int irq_matrix_reserve_managed(struct irq_matrix *m, const struct cpumask *msk);
1233 void irq_matrix_remove_managed(struct irq_matrix *m, const struct cpumask *msk);
1234 int irq_matrix_alloc_managed(struct irq_matrix *m, const struct cpumask *msk,
1235 unsigned int *mapped_cpu);
1236 void irq_matrix_reserve(struct irq_matrix *m);
1237 void irq_matrix_remove_reserved(struct irq_matrix *m);
1238 int irq_matrix_alloc(struct irq_matrix *m, const struct cpumask *msk,
1239 bool reserved, unsigned int *mapped_cpu);
1240 void irq_matrix_free(struct irq_matrix *m, unsigned int cpu,
1241 unsigned int bit, bool managed);
1242 void irq_matrix_assign(struct irq_matrix *m, unsigned int bit);
1243 unsigned int irq_matrix_available(struct irq_matrix *m, bool cpudown);
1244 unsigned int irq_matrix_allocated(struct irq_matrix *m);
1245 unsigned int irq_matrix_reserved(struct irq_matrix *m);
1246 void irq_matrix_debug_show(struct seq_file *sf, struct irq_matrix *m, int ind);
1247
1248 /* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */
1249 #define INVALID_HWIRQ (~0UL)
1250 irq_hw_number_t ipi_get_hwirq(unsigned int irq, unsigned int cpu);
1251 int __ipi_send_single(struct irq_desc *desc, unsigned int cpu);
1252 int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest);
1253 int ipi_send_single(unsigned int virq, unsigned int cpu);
1254 int ipi_send_mask(unsigned int virq, const struct cpumask *dest);
1255
1256 #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER
1257 /*
1258 * Registers a generic IRQ handling function as the top-level IRQ handler in
1259 * the system, which is generally the first C code called from an assembly
1260 * architecture-specific interrupt handler.
1261 *
1262 * Returns 0 on success, or -EBUSY if an IRQ handler has already been
1263 * registered.
1264 */
1265 int __init set_handle_irq(void (*handle_irq)(struct pt_regs *));
1266
1267 /*
1268 * Allows interrupt handlers to find the irqchip that's been registered as the
1269 * top-level IRQ handler.
1270 */
1271 extern void (*handle_arch_irq)(struct pt_regs *) __ro_after_init;
1272 #else
1273 #ifndef set_handle_irq
1274 #define set_handle_irq(handle_irq) \
1275 do { \
1276 (void)handle_irq; \
1277 WARN_ON(1); \
1278 } while (0)
1279 #endif
1280 #endif
1281
1282 #endif /* _LINUX_IRQ_H */
1283