1 // SPDX-License-Identifier: GPL-2.0-only
2
3 // motu-protocol-v1.c - a part of driver for MOTU FireWire series
4 //
5 // Copyright (c) 2021 Takashi Sakamoto <o-takashi@sakamocchi.jp>
6 //
7 // Licensed under the terms of the GNU General Public License, version 2.
8
9 #include "motu.h"
10
11 #include <linux/delay.h>
12
13 // Status register for MOTU 828 (0x'ffff'f000'0b00).
14 //
15 // 0xffff0000: ISOC_COMM_CONTROL_MASK in motu-stream.c.
16 // 0x00008000: mode of optical input interface.
17 // 0x00008000: for S/PDIF signal.
18 // 0x00000000: disabled or for ADAT signal.
19 // 0x00004000: mode of optical output interface.
20 // 0x00004000: for S/PDIF signal.
21 // 0x00000000: disabled or for ADAT signal.
22 // 0x00003f00: monitor input mode.
23 // 0x00000800: analog-1/2
24 // 0x00001a00: analog-3/4
25 // 0x00002c00: analog-5/6
26 // 0x00003e00: analog-7/8
27 // 0x00000000: analog-1
28 // 0x00000900: analog-2
29 // 0x00001200: analog-3
30 // 0x00001b00: analog-4
31 // 0x00002400: analog-5
32 // 0x00002d00: analog-6
33 // 0x00003600: analog-7
34 // 0x00003f00: analog-8
35 // 0x00000080: enable stream input.
36 // 0x00000040: disable monitor input.
37 // 0x00000008: enable main out.
38 // 0x00000004: rate of sampling clock.
39 // 0x00000004: 48.0 kHz
40 // 0x00000000: 44.1 kHz
41 // 0x00000023: source of sampling clock.
42 // 0x00000003: source packet header (SPH)
43 // 0x00000002: S/PDIF on optical/coaxial interface.
44 // 0x00000021: ADAT on optical interface
45 // 0x00000001: ADAT on Dsub 9pin
46 // 0x00000000: internal
47
48 #define CLK_828_STATUS_OFFSET 0x0b00
49 #define CLK_828_STATUS_MASK 0x0000ffff
50 #define CLK_828_STATUS_FLAG_OPT_IN_IFACE_IS_SPDIF 0x00008000
51 #define CLK_828_STATUS_FLAG_OPT_OUT_IFACE_IS_SPDIF 0x00004000
52 #define CLK_828_STATUS_FLAG_FETCH_PCM_FRAMES 0x00000080
53 #define CLK_828_STATUS_FLAG_ENABLE_OUTPUT 0x00000008
54 #define CLK_828_STATUS_FLAG_RATE_48000 0x00000004
55 #define CLK_828_STATUS_MASK_SRC 0x00000023
56 #define CLK_828_STATUS_FLAG_SRC_ADAT_ON_OPT 0x00000021
57 #define CLK_828_STATUS_FLAG_SRC_SPH 0x00000003
58 #define CLK_828_STATUS_FLAG_SRC_SPDIF 0x00000002
59 #define CLK_828_STATUS_FLAG_SRC_ADAT_ON_DSUB 0x00000001
60 #define CLK_828_STATUS_FLAG_SRC_INTERNAL 0x00000000
61
62 // Status register for MOTU 896 (0x'ffff'f000'0b14).
63 //
64 // 0xf0000000: enable physical and stream input to DAC.
65 // 0x80000000: disable
66 // 0x40000000: disable
67 // 0x20000000: enable (prior to the other bits)
68 // 0x10000000: disable
69 // 0x00000000: disable
70 // 0x08000000: speed of word clock signal output on BNC interface.
71 // 0x00000000: force to low rate (44.1/48.0 kHz).
72 // 0x08000000: follow to system clock.
73 // 0x04000000: something relevant to clock.
74 // 0x03000000: enable output.
75 // 0x02000000: enabled irreversibly once standing unless the device voluntarily disables it.
76 // 0x01000000: enabled irreversibly once standing unless the device voluntarily disables it.
77 // 0x00ffff00: monitor input mode.
78 // 0x00000000: disabled
79 // 0x00004800: analog-1/2
80 // 0x00005a00: analog-3/4
81 // 0x00006c00: analog-5/6
82 // 0x00007e00: analog-7/8
83 // 0x00104800: AES/EBU-1/2
84 // 0x00004000: analog-1
85 // 0x00004900: analog-2
86 // 0x00005200: analog-3
87 // 0x00005b00: analog-4
88 // 0x00006400: analog-5
89 // 0x00006d00: analog-6
90 // 0x00007600: analog-7
91 // 0x00007f00: analog-8
92 // 0x00104000: AES/EBU-1
93 // 0x00104900: AES/EBU-2
94 // 0x00000060: sample rate conversion for AES/EBU input/output.
95 // 0x00000000: None
96 // 0x00000020: input signal is converted to system rate
97 // 0x00000040: output is slave to input, ignoring system rate
98 // 0x00000060: output is double rate than system rate
99 // 0x00000018: nominal rate of sampling clock.
100 // 0x00000000: 44.1 kHz
101 // 0x00000008: 48.0 kHz
102 // 0x00000010: 88.2 kHz
103 // 0x00000018: 96.0 kHz
104 // 0x00000007: source of sampling clock.
105 // 0x00000000: internal
106 // 0x00000001: ADAT on optical interface
107 // 0x00000002: AES/EBU on XLR
108 // 0x00000003: source packet header (SPH)
109 // 0x00000004: word clock on BNC
110 // 0x00000005: ADAT on Dsub 9pin
111
112 #define CLK_896_STATUS_OFFSET 0x0b14
113 #define CLK_896_STATUS_FLAG_FETCH_ENABLE 0x20000000
114 #define CLK_896_STATUS_FLAG_OUTPUT_ON 0x03000000
115 #define CLK_896_STATUS_MASK_SRC 0x00000007
116 #define CLK_896_STATUS_FLAG_SRC_INTERNAL 0x00000000
117 #define CLK_896_STATUS_FLAG_SRC_ADAT_ON_OPT 0x00000001
118 #define CLK_896_STATUS_FLAG_SRC_AESEBU 0x00000002
119 #define CLK_896_STATUS_FLAG_SRC_SPH 0x00000003
120 #define CLK_896_STATUS_FLAG_SRC_WORD 0x00000004
121 #define CLK_896_STATUS_FLAG_SRC_ADAT_ON_DSUB 0x00000005
122 #define CLK_896_STATUS_MASK_RATE 0x00000018
123 #define CLK_896_STATUS_FLAG_RATE_44100 0x00000000
124 #define CLK_896_STATUS_FLAG_RATE_48000 0x00000008
125 #define CLK_896_STATUS_FLAG_RATE_88200 0x00000010
126 #define CLK_896_STATUS_FLAG_RATE_96000 0x00000018
127
parse_clock_rate_828(u32 data,unsigned int * rate)128 static void parse_clock_rate_828(u32 data, unsigned int *rate)
129 {
130 if (data & CLK_828_STATUS_FLAG_RATE_48000)
131 *rate = 48000;
132 else
133 *rate = 44100;
134 }
135
get_clock_rate_828(struct snd_motu * motu,unsigned int * rate)136 static int get_clock_rate_828(struct snd_motu *motu, unsigned int *rate)
137 {
138 __be32 reg;
139 int err;
140
141 err = snd_motu_transaction_read(motu, CLK_828_STATUS_OFFSET, ®, sizeof(reg));
142 if (err < 0)
143 return err;
144 parse_clock_rate_828(be32_to_cpu(reg), rate);
145
146 return 0;
147 }
148
parse_clock_rate_896(u32 data,unsigned int * rate)149 static int parse_clock_rate_896(u32 data, unsigned int *rate)
150 {
151 switch (data & CLK_896_STATUS_MASK_RATE) {
152 case CLK_896_STATUS_FLAG_RATE_44100:
153 *rate = 44100;
154 break;
155 case CLK_896_STATUS_FLAG_RATE_48000:
156 *rate = 48000;
157 break;
158 case CLK_896_STATUS_FLAG_RATE_88200:
159 *rate = 88200;
160 break;
161 case CLK_896_STATUS_FLAG_RATE_96000:
162 *rate = 96000;
163 break;
164 default:
165 return -ENXIO;
166 }
167
168 return 0;
169 }
170
get_clock_rate_896(struct snd_motu * motu,unsigned int * rate)171 static int get_clock_rate_896(struct snd_motu *motu, unsigned int *rate)
172 {
173 __be32 reg;
174 int err;
175
176 err = snd_motu_transaction_read(motu, CLK_896_STATUS_OFFSET, ®, sizeof(reg));
177 if (err < 0)
178 return err;
179 return parse_clock_rate_896(be32_to_cpu(reg), rate);
180 }
181
snd_motu_protocol_v1_get_clock_rate(struct snd_motu * motu,unsigned int * rate)182 int snd_motu_protocol_v1_get_clock_rate(struct snd_motu *motu, unsigned int *rate)
183 {
184 if (motu->spec == &snd_motu_spec_828)
185 return get_clock_rate_828(motu, rate);
186 else if (motu->spec == &snd_motu_spec_896)
187 return get_clock_rate_896(motu, rate);
188 else
189 return -ENXIO;
190 }
191
set_clock_rate_828(struct snd_motu * motu,unsigned int rate)192 static int set_clock_rate_828(struct snd_motu *motu, unsigned int rate)
193 {
194 __be32 reg;
195 u32 data;
196 int err;
197
198 err = snd_motu_transaction_read(motu, CLK_828_STATUS_OFFSET, ®, sizeof(reg));
199 if (err < 0)
200 return err;
201 data = be32_to_cpu(reg) & CLK_828_STATUS_MASK;
202
203 data &= ~CLK_828_STATUS_FLAG_RATE_48000;
204 if (rate == 48000)
205 data |= CLK_828_STATUS_FLAG_RATE_48000;
206
207 reg = cpu_to_be32(data);
208 return snd_motu_transaction_write(motu, CLK_828_STATUS_OFFSET, ®, sizeof(reg));
209 }
210
set_clock_rate_896(struct snd_motu * motu,unsigned int rate)211 static int set_clock_rate_896(struct snd_motu *motu, unsigned int rate)
212 {
213 unsigned int flag;
214 __be32 reg;
215 u32 data;
216 int err;
217
218 err = snd_motu_transaction_read(motu, CLK_896_STATUS_OFFSET, ®, sizeof(reg));
219 if (err < 0)
220 return err;
221 data = be32_to_cpu(reg);
222
223 switch (rate) {
224 case 44100:
225 flag = CLK_896_STATUS_FLAG_RATE_44100;
226 break;
227 case 48000:
228 flag = CLK_896_STATUS_FLAG_RATE_48000;
229 break;
230 case 88200:
231 flag = CLK_896_STATUS_FLAG_RATE_88200;
232 break;
233 case 96000:
234 flag = CLK_896_STATUS_FLAG_RATE_96000;
235 break;
236 default:
237 return -EINVAL;
238 }
239
240 data &= ~CLK_896_STATUS_MASK_RATE;
241 data |= flag;
242
243 reg = cpu_to_be32(data);
244 return snd_motu_transaction_write(motu, CLK_896_STATUS_OFFSET, ®, sizeof(reg));
245 }
246
snd_motu_protocol_v1_set_clock_rate(struct snd_motu * motu,unsigned int rate)247 int snd_motu_protocol_v1_set_clock_rate(struct snd_motu *motu, unsigned int rate)
248 {
249 if (motu->spec == &snd_motu_spec_828)
250 return set_clock_rate_828(motu, rate);
251 else if (motu->spec == &snd_motu_spec_896)
252 return set_clock_rate_896(motu, rate);
253 else
254 return -ENXIO;
255 }
256
get_clock_source_828(struct snd_motu * motu,enum snd_motu_clock_source * src)257 static int get_clock_source_828(struct snd_motu *motu, enum snd_motu_clock_source *src)
258 {
259 __be32 reg;
260 u32 data;
261 int err;
262
263 err = snd_motu_transaction_read(motu, CLK_828_STATUS_OFFSET, ®, sizeof(reg));
264 if (err < 0)
265 return err;
266 data = be32_to_cpu(reg) & CLK_828_STATUS_MASK;
267
268 switch (data & CLK_828_STATUS_MASK_SRC) {
269 case CLK_828_STATUS_FLAG_SRC_ADAT_ON_OPT:
270 *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_OPT;
271 break;
272 case CLK_828_STATUS_FLAG_SRC_SPH:
273 *src = SND_MOTU_CLOCK_SOURCE_SPH;
274 break;
275 case CLK_828_STATUS_FLAG_SRC_SPDIF:
276 {
277 if (data & CLK_828_STATUS_FLAG_OPT_IN_IFACE_IS_SPDIF)
278 *src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_COAX;
279 else
280 *src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_OPT;
281 break;
282 }
283 case CLK_828_STATUS_FLAG_SRC_ADAT_ON_DSUB:
284 *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_DSUB;
285 break;
286 case CLK_828_STATUS_FLAG_SRC_INTERNAL:
287 *src = SND_MOTU_CLOCK_SOURCE_INTERNAL;
288 break;
289 default:
290 return -ENXIO;
291 }
292
293 return 0;
294 }
295
get_clock_source_896(struct snd_motu * motu,enum snd_motu_clock_source * src)296 static int get_clock_source_896(struct snd_motu *motu, enum snd_motu_clock_source *src)
297 {
298 __be32 reg;
299 u32 data;
300 int err;
301
302 err = snd_motu_transaction_read(motu, CLK_896_STATUS_OFFSET, ®, sizeof(reg));
303 if (err < 0)
304 return err;
305 data = be32_to_cpu(reg);
306
307 switch (data & CLK_896_STATUS_MASK_SRC) {
308 case CLK_896_STATUS_FLAG_SRC_INTERNAL:
309 *src = SND_MOTU_CLOCK_SOURCE_INTERNAL;
310 break;
311 case CLK_896_STATUS_FLAG_SRC_ADAT_ON_OPT:
312 *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_OPT;
313 break;
314 case CLK_896_STATUS_FLAG_SRC_AESEBU:
315 *src = SND_MOTU_CLOCK_SOURCE_AESEBU_ON_XLR;
316 break;
317 case CLK_896_STATUS_FLAG_SRC_SPH:
318 *src = SND_MOTU_CLOCK_SOURCE_SPH;
319 break;
320 case CLK_896_STATUS_FLAG_SRC_WORD:
321 *src = SND_MOTU_CLOCK_SOURCE_WORD_ON_BNC;
322 break;
323 case CLK_896_STATUS_FLAG_SRC_ADAT_ON_DSUB:
324 *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_DSUB;
325 break;
326 default:
327 return -ENXIO;
328 }
329
330 return 0;
331 }
332
snd_motu_protocol_v1_get_clock_source(struct snd_motu * motu,enum snd_motu_clock_source * src)333 int snd_motu_protocol_v1_get_clock_source(struct snd_motu *motu, enum snd_motu_clock_source *src)
334 {
335 if (motu->spec == &snd_motu_spec_828)
336 return get_clock_source_828(motu, src);
337 else if (motu->spec == &snd_motu_spec_896)
338 return get_clock_source_896(motu, src);
339 else
340 return -ENXIO;
341 }
342
switch_fetching_mode_828(struct snd_motu * motu,bool enable)343 static int switch_fetching_mode_828(struct snd_motu *motu, bool enable)
344 {
345 __be32 reg;
346 u32 data;
347 int err;
348
349 err = snd_motu_transaction_read(motu, CLK_828_STATUS_OFFSET, ®, sizeof(reg));
350 if (err < 0)
351 return err;
352 data = be32_to_cpu(reg) & CLK_828_STATUS_MASK;
353
354 data &= ~(CLK_828_STATUS_FLAG_FETCH_PCM_FRAMES | CLK_828_STATUS_FLAG_ENABLE_OUTPUT);
355 if (enable) {
356 // This transaction should be initiated after the device receives batch of packets
357 // since the device voluntarily mutes outputs. As a workaround, yield processor over
358 // 100 msec.
359 msleep(100);
360 data |= CLK_828_STATUS_FLAG_FETCH_PCM_FRAMES | CLK_828_STATUS_FLAG_ENABLE_OUTPUT;
361 }
362
363 reg = cpu_to_be32(data);
364 return snd_motu_transaction_write(motu, CLK_828_STATUS_OFFSET, ®, sizeof(reg));
365 }
366
switch_fetching_mode_896(struct snd_motu * motu,bool enable)367 static int switch_fetching_mode_896(struct snd_motu *motu, bool enable)
368 {
369 __be32 reg;
370 u32 data;
371 int err;
372
373 err = snd_motu_transaction_read(motu, CLK_896_STATUS_OFFSET, ®, sizeof(reg));
374 if (err < 0)
375 return err;
376 data = be32_to_cpu(reg);
377
378 data &= ~CLK_896_STATUS_FLAG_FETCH_ENABLE;
379 if (enable)
380 data |= CLK_896_STATUS_FLAG_FETCH_ENABLE | CLK_896_STATUS_FLAG_OUTPUT_ON;
381
382 reg = cpu_to_be32(data);
383 return snd_motu_transaction_write(motu, CLK_896_STATUS_OFFSET, ®, sizeof(reg));
384 }
385
snd_motu_protocol_v1_switch_fetching_mode(struct snd_motu * motu,bool enable)386 int snd_motu_protocol_v1_switch_fetching_mode(struct snd_motu *motu, bool enable)
387 {
388 if (motu->spec == &snd_motu_spec_828)
389 return switch_fetching_mode_828(motu, enable);
390 else if (motu->spec == &snd_motu_spec_896)
391 return switch_fetching_mode_896(motu, enable);
392 else
393 return -ENXIO;
394 }
395
detect_packet_formats_828(struct snd_motu * motu)396 static int detect_packet_formats_828(struct snd_motu *motu)
397 {
398 __be32 reg;
399 u32 data;
400 int err;
401
402 motu->tx_packet_formats.pcm_byte_offset = 4;
403 motu->tx_packet_formats.msg_chunks = 2;
404
405 motu->rx_packet_formats.pcm_byte_offset = 4;
406 motu->rx_packet_formats.msg_chunks = 0;
407
408 err = snd_motu_transaction_read(motu, CLK_828_STATUS_OFFSET, ®, sizeof(reg));
409 if (err < 0)
410 return err;
411 data = be32_to_cpu(reg) & CLK_828_STATUS_MASK;
412
413 // The number of chunks is just reduced when SPDIF is activated.
414 if (!(data & CLK_828_STATUS_FLAG_OPT_IN_IFACE_IS_SPDIF))
415 motu->tx_packet_formats.pcm_chunks[0] += 8;
416
417 if (!(data & CLK_828_STATUS_FLAG_OPT_OUT_IFACE_IS_SPDIF))
418 motu->rx_packet_formats.pcm_chunks[0] += 8;
419
420 return 0;
421 }
422
detect_packet_formats_896(struct snd_motu * motu)423 static int detect_packet_formats_896(struct snd_motu *motu)
424 {
425 // 24bit PCM frames follow to source packet header without message chunk.
426 motu->tx_packet_formats.pcm_byte_offset = 4;
427 motu->rx_packet_formats.pcm_byte_offset = 4;
428
429 // No message chunk in data block.
430 motu->tx_packet_formats.msg_chunks = 0;
431 motu->rx_packet_formats.msg_chunks = 0;
432
433 // Always enable optical interface for ADAT signal since the device have no registers
434 // to refer to current configuration.
435 motu->tx_packet_formats.pcm_chunks[0] += 8;
436 motu->tx_packet_formats.pcm_chunks[1] += 8;
437
438 motu->rx_packet_formats.pcm_chunks[0] += 8;
439 motu->rx_packet_formats.pcm_chunks[1] += 8;
440
441 return 0;
442 }
443
snd_motu_protocol_v1_cache_packet_formats(struct snd_motu * motu)444 int snd_motu_protocol_v1_cache_packet_formats(struct snd_motu *motu)
445 {
446 memcpy(motu->tx_packet_formats.pcm_chunks, motu->spec->tx_fixed_pcm_chunks,
447 sizeof(motu->tx_packet_formats.pcm_chunks));
448 memcpy(motu->rx_packet_formats.pcm_chunks, motu->spec->rx_fixed_pcm_chunks,
449 sizeof(motu->rx_packet_formats.pcm_chunks));
450
451 if (motu->spec == &snd_motu_spec_828)
452 return detect_packet_formats_828(motu);
453 else if (motu->spec == &snd_motu_spec_896)
454 return detect_packet_formats_896(motu);
455 else
456 return 0;
457 }
458
459 const struct snd_motu_spec snd_motu_spec_828 = {
460 .name = "828",
461 .protocol_version = SND_MOTU_PROTOCOL_V1,
462 .tx_fixed_pcm_chunks = {10, 0, 0},
463 .rx_fixed_pcm_chunks = {10, 0, 0},
464 };
465
466 const struct snd_motu_spec snd_motu_spec_896 = {
467 .name = "896",
468 .tx_fixed_pcm_chunks = {10, 10, 0},
469 .rx_fixed_pcm_chunks = {10, 10, 0},
470 };
471