1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * cs42l42.c -- CS42L42 ALSA SoC audio driver
4 *
5 * Copyright 2016 Cirrus Logic, Inc.
6 *
7 * Author: James Schulman <james.schulman@cirrus.com>
8 * Author: Brian Austin <brian.austin@cirrus.com>
9 * Author: Michael White <michael.white@cirrus.com>
10 */
11
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/version.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/i2c.h>
19 #include <linux/gpio.h>
20 #include <linux/regmap.h>
21 #include <linux/slab.h>
22 #include <linux/acpi.h>
23 #include <linux/platform_device.h>
24 #include <linux/property.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/gpio/consumer.h>
27 #include <linux/of_device.h>
28 #include <linux/pm_runtime.h>
29 #include <sound/core.h>
30 #include <sound/pcm.h>
31 #include <sound/pcm_params.h>
32 #include <sound/soc.h>
33 #include <sound/soc-dapm.h>
34 #include <sound/initval.h>
35 #include <sound/tlv.h>
36 #include <dt-bindings/sound/cs42l42.h>
37
38 #include "cs42l42.h"
39 #include "cirrus_legacy.h"
40
41 static const struct reg_default cs42l42_reg_defaults[] = {
42 { CS42L42_FRZ_CTL, 0x00 },
43 { CS42L42_SRC_CTL, 0x10 },
44 { CS42L42_MCLK_STATUS, 0x02 },
45 { CS42L42_MCLK_CTL, 0x02 },
46 { CS42L42_SFTRAMP_RATE, 0xA4 },
47 { CS42L42_I2C_DEBOUNCE, 0x88 },
48 { CS42L42_I2C_STRETCH, 0x03 },
49 { CS42L42_I2C_TIMEOUT, 0xB7 },
50 { CS42L42_PWR_CTL1, 0xFF },
51 { CS42L42_PWR_CTL2, 0x84 },
52 { CS42L42_PWR_CTL3, 0x20 },
53 { CS42L42_RSENSE_CTL1, 0x40 },
54 { CS42L42_RSENSE_CTL2, 0x00 },
55 { CS42L42_OSC_SWITCH, 0x00 },
56 { CS42L42_OSC_SWITCH_STATUS, 0x05 },
57 { CS42L42_RSENSE_CTL3, 0x1B },
58 { CS42L42_TSENSE_CTL, 0x1B },
59 { CS42L42_TSRS_INT_DISABLE, 0x00 },
60 { CS42L42_TRSENSE_STATUS, 0x00 },
61 { CS42L42_HSDET_CTL1, 0x77 },
62 { CS42L42_HSDET_CTL2, 0x00 },
63 { CS42L42_HS_SWITCH_CTL, 0xF3 },
64 { CS42L42_HS_DET_STATUS, 0x00 },
65 { CS42L42_HS_CLAMP_DISABLE, 0x00 },
66 { CS42L42_MCLK_SRC_SEL, 0x00 },
67 { CS42L42_SPDIF_CLK_CFG, 0x00 },
68 { CS42L42_FSYNC_PW_LOWER, 0x00 },
69 { CS42L42_FSYNC_PW_UPPER, 0x00 },
70 { CS42L42_FSYNC_P_LOWER, 0xF9 },
71 { CS42L42_FSYNC_P_UPPER, 0x00 },
72 { CS42L42_ASP_CLK_CFG, 0x00 },
73 { CS42L42_ASP_FRM_CFG, 0x10 },
74 { CS42L42_FS_RATE_EN, 0x00 },
75 { CS42L42_IN_ASRC_CLK, 0x00 },
76 { CS42L42_OUT_ASRC_CLK, 0x00 },
77 { CS42L42_PLL_DIV_CFG1, 0x00 },
78 { CS42L42_ADC_OVFL_STATUS, 0x00 },
79 { CS42L42_MIXER_STATUS, 0x00 },
80 { CS42L42_SRC_STATUS, 0x00 },
81 { CS42L42_ASP_RX_STATUS, 0x00 },
82 { CS42L42_ASP_TX_STATUS, 0x00 },
83 { CS42L42_CODEC_STATUS, 0x00 },
84 { CS42L42_DET_INT_STATUS1, 0x00 },
85 { CS42L42_DET_INT_STATUS2, 0x00 },
86 { CS42L42_SRCPL_INT_STATUS, 0x00 },
87 { CS42L42_VPMON_STATUS, 0x00 },
88 { CS42L42_PLL_LOCK_STATUS, 0x00 },
89 { CS42L42_TSRS_PLUG_STATUS, 0x00 },
90 { CS42L42_ADC_OVFL_INT_MASK, 0x01 },
91 { CS42L42_MIXER_INT_MASK, 0x0F },
92 { CS42L42_SRC_INT_MASK, 0x0F },
93 { CS42L42_ASP_RX_INT_MASK, 0x1F },
94 { CS42L42_ASP_TX_INT_MASK, 0x0F },
95 { CS42L42_CODEC_INT_MASK, 0x03 },
96 { CS42L42_SRCPL_INT_MASK, 0x7F },
97 { CS42L42_VPMON_INT_MASK, 0x01 },
98 { CS42L42_PLL_LOCK_INT_MASK, 0x01 },
99 { CS42L42_TSRS_PLUG_INT_MASK, 0x0F },
100 { CS42L42_PLL_CTL1, 0x00 },
101 { CS42L42_PLL_DIV_FRAC0, 0x00 },
102 { CS42L42_PLL_DIV_FRAC1, 0x00 },
103 { CS42L42_PLL_DIV_FRAC2, 0x00 },
104 { CS42L42_PLL_DIV_INT, 0x40 },
105 { CS42L42_PLL_CTL3, 0x10 },
106 { CS42L42_PLL_CAL_RATIO, 0x80 },
107 { CS42L42_PLL_CTL4, 0x03 },
108 { CS42L42_LOAD_DET_RCSTAT, 0x00 },
109 { CS42L42_LOAD_DET_DONE, 0x00 },
110 { CS42L42_LOAD_DET_EN, 0x00 },
111 { CS42L42_HSBIAS_SC_AUTOCTL, 0x03 },
112 { CS42L42_WAKE_CTL, 0xC0 },
113 { CS42L42_ADC_DISABLE_MUTE, 0x00 },
114 { CS42L42_TIPSENSE_CTL, 0x02 },
115 { CS42L42_MISC_DET_CTL, 0x03 },
116 { CS42L42_MIC_DET_CTL1, 0x1F },
117 { CS42L42_MIC_DET_CTL2, 0x2F },
118 { CS42L42_DET_STATUS1, 0x00 },
119 { CS42L42_DET_STATUS2, 0x00 },
120 { CS42L42_DET_INT1_MASK, 0xE0 },
121 { CS42L42_DET_INT2_MASK, 0xFF },
122 { CS42L42_HS_BIAS_CTL, 0xC2 },
123 { CS42L42_ADC_CTL, 0x00 },
124 { CS42L42_ADC_VOLUME, 0x00 },
125 { CS42L42_ADC_WNF_HPF_CTL, 0x71 },
126 { CS42L42_DAC_CTL1, 0x00 },
127 { CS42L42_DAC_CTL2, 0x02 },
128 { CS42L42_HP_CTL, 0x0D },
129 { CS42L42_CLASSH_CTL, 0x07 },
130 { CS42L42_MIXER_CHA_VOL, 0x3F },
131 { CS42L42_MIXER_ADC_VOL, 0x3F },
132 { CS42L42_MIXER_CHB_VOL, 0x3F },
133 { CS42L42_EQ_COEF_IN0, 0x00 },
134 { CS42L42_EQ_COEF_IN1, 0x00 },
135 { CS42L42_EQ_COEF_IN2, 0x00 },
136 { CS42L42_EQ_COEF_IN3, 0x00 },
137 { CS42L42_EQ_COEF_RW, 0x00 },
138 { CS42L42_EQ_COEF_OUT0, 0x00 },
139 { CS42L42_EQ_COEF_OUT1, 0x00 },
140 { CS42L42_EQ_COEF_OUT2, 0x00 },
141 { CS42L42_EQ_COEF_OUT3, 0x00 },
142 { CS42L42_EQ_INIT_STAT, 0x00 },
143 { CS42L42_EQ_START_FILT, 0x00 },
144 { CS42L42_EQ_MUTE_CTL, 0x00 },
145 { CS42L42_SP_RX_CH_SEL, 0x04 },
146 { CS42L42_SP_RX_ISOC_CTL, 0x04 },
147 { CS42L42_SP_RX_FS, 0x8C },
148 { CS42l42_SPDIF_CH_SEL, 0x0E },
149 { CS42L42_SP_TX_ISOC_CTL, 0x04 },
150 { CS42L42_SP_TX_FS, 0xCC },
151 { CS42L42_SPDIF_SW_CTL1, 0x3F },
152 { CS42L42_SRC_SDIN_FS, 0x40 },
153 { CS42L42_SRC_SDOUT_FS, 0x40 },
154 { CS42L42_SPDIF_CTL1, 0x01 },
155 { CS42L42_SPDIF_CTL2, 0x00 },
156 { CS42L42_SPDIF_CTL3, 0x00 },
157 { CS42L42_SPDIF_CTL4, 0x42 },
158 { CS42L42_ASP_TX_SZ_EN, 0x00 },
159 { CS42L42_ASP_TX_CH_EN, 0x00 },
160 { CS42L42_ASP_TX_CH_AP_RES, 0x0F },
161 { CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 },
162 { CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 },
163 { CS42L42_ASP_TX_HIZ_DLY_CFG, 0x00 },
164 { CS42L42_ASP_TX_CH2_BIT_MSB, 0x00 },
165 { CS42L42_ASP_TX_CH2_BIT_LSB, 0x00 },
166 { CS42L42_ASP_RX_DAI0_EN, 0x00 },
167 { CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x03 },
168 { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 },
169 { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 },
170 { CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x03 },
171 { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 },
172 { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x00 },
173 { CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x03 },
174 { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 },
175 { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x00 },
176 { CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x03 },
177 { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 },
178 { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0x00 },
179 { CS42L42_ASP_RX_DAI1_CH1_AP_RES, 0x03 },
180 { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB, 0x00 },
181 { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB, 0x00 },
182 { CS42L42_ASP_RX_DAI1_CH2_AP_RES, 0x03 },
183 { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB, 0x00 },
184 { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB, 0x00 },
185 { CS42L42_SUB_REVID, 0x03 },
186 };
187
cs42l42_readable_register(struct device * dev,unsigned int reg)188 static bool cs42l42_readable_register(struct device *dev, unsigned int reg)
189 {
190 switch (reg) {
191 case CS42L42_PAGE_REGISTER:
192 case CS42L42_DEVID_AB:
193 case CS42L42_DEVID_CD:
194 case CS42L42_DEVID_E:
195 case CS42L42_FABID:
196 case CS42L42_REVID:
197 case CS42L42_FRZ_CTL:
198 case CS42L42_SRC_CTL:
199 case CS42L42_MCLK_STATUS:
200 case CS42L42_MCLK_CTL:
201 case CS42L42_SFTRAMP_RATE:
202 case CS42L42_I2C_DEBOUNCE:
203 case CS42L42_I2C_STRETCH:
204 case CS42L42_I2C_TIMEOUT:
205 case CS42L42_PWR_CTL1:
206 case CS42L42_PWR_CTL2:
207 case CS42L42_PWR_CTL3:
208 case CS42L42_RSENSE_CTL1:
209 case CS42L42_RSENSE_CTL2:
210 case CS42L42_OSC_SWITCH:
211 case CS42L42_OSC_SWITCH_STATUS:
212 case CS42L42_RSENSE_CTL3:
213 case CS42L42_TSENSE_CTL:
214 case CS42L42_TSRS_INT_DISABLE:
215 case CS42L42_TRSENSE_STATUS:
216 case CS42L42_HSDET_CTL1:
217 case CS42L42_HSDET_CTL2:
218 case CS42L42_HS_SWITCH_CTL:
219 case CS42L42_HS_DET_STATUS:
220 case CS42L42_HS_CLAMP_DISABLE:
221 case CS42L42_MCLK_SRC_SEL:
222 case CS42L42_SPDIF_CLK_CFG:
223 case CS42L42_FSYNC_PW_LOWER:
224 case CS42L42_FSYNC_PW_UPPER:
225 case CS42L42_FSYNC_P_LOWER:
226 case CS42L42_FSYNC_P_UPPER:
227 case CS42L42_ASP_CLK_CFG:
228 case CS42L42_ASP_FRM_CFG:
229 case CS42L42_FS_RATE_EN:
230 case CS42L42_IN_ASRC_CLK:
231 case CS42L42_OUT_ASRC_CLK:
232 case CS42L42_PLL_DIV_CFG1:
233 case CS42L42_ADC_OVFL_STATUS:
234 case CS42L42_MIXER_STATUS:
235 case CS42L42_SRC_STATUS:
236 case CS42L42_ASP_RX_STATUS:
237 case CS42L42_ASP_TX_STATUS:
238 case CS42L42_CODEC_STATUS:
239 case CS42L42_DET_INT_STATUS1:
240 case CS42L42_DET_INT_STATUS2:
241 case CS42L42_SRCPL_INT_STATUS:
242 case CS42L42_VPMON_STATUS:
243 case CS42L42_PLL_LOCK_STATUS:
244 case CS42L42_TSRS_PLUG_STATUS:
245 case CS42L42_ADC_OVFL_INT_MASK:
246 case CS42L42_MIXER_INT_MASK:
247 case CS42L42_SRC_INT_MASK:
248 case CS42L42_ASP_RX_INT_MASK:
249 case CS42L42_ASP_TX_INT_MASK:
250 case CS42L42_CODEC_INT_MASK:
251 case CS42L42_SRCPL_INT_MASK:
252 case CS42L42_VPMON_INT_MASK:
253 case CS42L42_PLL_LOCK_INT_MASK:
254 case CS42L42_TSRS_PLUG_INT_MASK:
255 case CS42L42_PLL_CTL1:
256 case CS42L42_PLL_DIV_FRAC0:
257 case CS42L42_PLL_DIV_FRAC1:
258 case CS42L42_PLL_DIV_FRAC2:
259 case CS42L42_PLL_DIV_INT:
260 case CS42L42_PLL_CTL3:
261 case CS42L42_PLL_CAL_RATIO:
262 case CS42L42_PLL_CTL4:
263 case CS42L42_LOAD_DET_RCSTAT:
264 case CS42L42_LOAD_DET_DONE:
265 case CS42L42_LOAD_DET_EN:
266 case CS42L42_HSBIAS_SC_AUTOCTL:
267 case CS42L42_WAKE_CTL:
268 case CS42L42_ADC_DISABLE_MUTE:
269 case CS42L42_TIPSENSE_CTL:
270 case CS42L42_MISC_DET_CTL:
271 case CS42L42_MIC_DET_CTL1:
272 case CS42L42_MIC_DET_CTL2:
273 case CS42L42_DET_STATUS1:
274 case CS42L42_DET_STATUS2:
275 case CS42L42_DET_INT1_MASK:
276 case CS42L42_DET_INT2_MASK:
277 case CS42L42_HS_BIAS_CTL:
278 case CS42L42_ADC_CTL:
279 case CS42L42_ADC_VOLUME:
280 case CS42L42_ADC_WNF_HPF_CTL:
281 case CS42L42_DAC_CTL1:
282 case CS42L42_DAC_CTL2:
283 case CS42L42_HP_CTL:
284 case CS42L42_CLASSH_CTL:
285 case CS42L42_MIXER_CHA_VOL:
286 case CS42L42_MIXER_ADC_VOL:
287 case CS42L42_MIXER_CHB_VOL:
288 case CS42L42_EQ_COEF_IN0:
289 case CS42L42_EQ_COEF_IN1:
290 case CS42L42_EQ_COEF_IN2:
291 case CS42L42_EQ_COEF_IN3:
292 case CS42L42_EQ_COEF_RW:
293 case CS42L42_EQ_COEF_OUT0:
294 case CS42L42_EQ_COEF_OUT1:
295 case CS42L42_EQ_COEF_OUT2:
296 case CS42L42_EQ_COEF_OUT3:
297 case CS42L42_EQ_INIT_STAT:
298 case CS42L42_EQ_START_FILT:
299 case CS42L42_EQ_MUTE_CTL:
300 case CS42L42_SP_RX_CH_SEL:
301 case CS42L42_SP_RX_ISOC_CTL:
302 case CS42L42_SP_RX_FS:
303 case CS42l42_SPDIF_CH_SEL:
304 case CS42L42_SP_TX_ISOC_CTL:
305 case CS42L42_SP_TX_FS:
306 case CS42L42_SPDIF_SW_CTL1:
307 case CS42L42_SRC_SDIN_FS:
308 case CS42L42_SRC_SDOUT_FS:
309 case CS42L42_SPDIF_CTL1:
310 case CS42L42_SPDIF_CTL2:
311 case CS42L42_SPDIF_CTL3:
312 case CS42L42_SPDIF_CTL4:
313 case CS42L42_ASP_TX_SZ_EN:
314 case CS42L42_ASP_TX_CH_EN:
315 case CS42L42_ASP_TX_CH_AP_RES:
316 case CS42L42_ASP_TX_CH1_BIT_MSB:
317 case CS42L42_ASP_TX_CH1_BIT_LSB:
318 case CS42L42_ASP_TX_HIZ_DLY_CFG:
319 case CS42L42_ASP_TX_CH2_BIT_MSB:
320 case CS42L42_ASP_TX_CH2_BIT_LSB:
321 case CS42L42_ASP_RX_DAI0_EN:
322 case CS42L42_ASP_RX_DAI0_CH1_AP_RES:
323 case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB:
324 case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB:
325 case CS42L42_ASP_RX_DAI0_CH2_AP_RES:
326 case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB:
327 case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB:
328 case CS42L42_ASP_RX_DAI0_CH3_AP_RES:
329 case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB:
330 case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB:
331 case CS42L42_ASP_RX_DAI0_CH4_AP_RES:
332 case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB:
333 case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB:
334 case CS42L42_ASP_RX_DAI1_CH1_AP_RES:
335 case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB:
336 case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB:
337 case CS42L42_ASP_RX_DAI1_CH2_AP_RES:
338 case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB:
339 case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB:
340 case CS42L42_SUB_REVID:
341 return true;
342 default:
343 return false;
344 }
345 }
346
cs42l42_volatile_register(struct device * dev,unsigned int reg)347 static bool cs42l42_volatile_register(struct device *dev, unsigned int reg)
348 {
349 switch (reg) {
350 case CS42L42_DEVID_AB:
351 case CS42L42_DEVID_CD:
352 case CS42L42_DEVID_E:
353 case CS42L42_MCLK_STATUS:
354 case CS42L42_TRSENSE_STATUS:
355 case CS42L42_HS_DET_STATUS:
356 case CS42L42_ADC_OVFL_STATUS:
357 case CS42L42_MIXER_STATUS:
358 case CS42L42_SRC_STATUS:
359 case CS42L42_ASP_RX_STATUS:
360 case CS42L42_ASP_TX_STATUS:
361 case CS42L42_CODEC_STATUS:
362 case CS42L42_DET_INT_STATUS1:
363 case CS42L42_DET_INT_STATUS2:
364 case CS42L42_SRCPL_INT_STATUS:
365 case CS42L42_VPMON_STATUS:
366 case CS42L42_PLL_LOCK_STATUS:
367 case CS42L42_TSRS_PLUG_STATUS:
368 case CS42L42_LOAD_DET_RCSTAT:
369 case CS42L42_LOAD_DET_DONE:
370 case CS42L42_DET_STATUS1:
371 case CS42L42_DET_STATUS2:
372 return true;
373 default:
374 return false;
375 }
376 }
377
378 static const struct regmap_range_cfg cs42l42_page_range = {
379 .name = "Pages",
380 .range_min = 0,
381 .range_max = CS42L42_MAX_REGISTER,
382 .selector_reg = CS42L42_PAGE_REGISTER,
383 .selector_mask = 0xff,
384 .selector_shift = 0,
385 .window_start = 0,
386 .window_len = 256,
387 };
388
389 static const struct regmap_config cs42l42_regmap = {
390 .reg_bits = 8,
391 .val_bits = 8,
392
393 .readable_reg = cs42l42_readable_register,
394 .volatile_reg = cs42l42_volatile_register,
395
396 .ranges = &cs42l42_page_range,
397 .num_ranges = 1,
398
399 .max_register = CS42L42_MAX_REGISTER,
400 .reg_defaults = cs42l42_reg_defaults,
401 .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults),
402 .cache_type = REGCACHE_RBTREE,
403
404 .use_single_read = true,
405 .use_single_write = true,
406 };
407
408 static DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 100, true);
409 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true);
410
411 static const char * const cs42l42_hpf_freq_text[] = {
412 "1.86Hz", "120Hz", "235Hz", "466Hz"
413 };
414
415 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
416 CS42L42_ADC_HPF_CF_SHIFT,
417 cs42l42_hpf_freq_text);
418
419 static const char * const cs42l42_wnf3_freq_text[] = {
420 "160Hz", "180Hz", "200Hz", "220Hz",
421 "240Hz", "260Hz", "280Hz", "300Hz"
422 };
423
424 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
425 CS42L42_ADC_WNF_CF_SHIFT,
426 cs42l42_wnf3_freq_text);
427
428 static const struct snd_kcontrol_new cs42l42_snd_controls[] = {
429 /* ADC Volume and Filter Controls */
430 SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL,
431 CS42L42_ADC_NOTCH_DIS_SHIFT, true, true),
432 SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL,
433 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false),
434 SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL,
435 CS42L42_ADC_INV_SHIFT, true, false),
436 SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL,
437 CS42L42_ADC_DIG_BOOST_SHIFT, true, false),
438 SOC_SINGLE_S8_TLV("ADC Volume", CS42L42_ADC_VOLUME, -97, 12, adc_tlv),
439 SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL,
440 CS42L42_ADC_WNF_EN_SHIFT, true, false),
441 SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL,
442 CS42L42_ADC_HPF_EN_SHIFT, true, false),
443 SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum),
444 SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum),
445
446 /* DAC Volume and Filter Controls */
447 SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1,
448 CS42L42_DACA_INV_SHIFT, true, false),
449 SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1,
450 CS42L42_DACB_INV_SHIFT, true, false),
451 SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2,
452 CS42L42_DAC_HPF_EN_SHIFT, true, false),
453 SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL,
454 CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT,
455 0x3f, 1, mixer_tlv)
456 };
457
458 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = {
459 /* Playback Path */
460 SND_SOC_DAPM_OUTPUT("HP"),
461 SND_SOC_DAPM_DAC("DAC", NULL, CS42L42_PWR_CTL1, CS42L42_HP_PDN_SHIFT, 1),
462 SND_SOC_DAPM_MIXER("MIXER", CS42L42_PWR_CTL1, CS42L42_MIXER_PDN_SHIFT, 1, NULL, 0),
463 SND_SOC_DAPM_AIF_IN("SDIN1", NULL, 0, SND_SOC_NOPM, 0, 0),
464 SND_SOC_DAPM_AIF_IN("SDIN2", NULL, 1, SND_SOC_NOPM, 0, 0),
465
466 /* Playback Requirements */
467 SND_SOC_DAPM_SUPPLY("ASP DAI0", CS42L42_PWR_CTL1, CS42L42_ASP_DAI_PDN_SHIFT, 1, NULL, 0),
468
469 /* Capture Path */
470 SND_SOC_DAPM_INPUT("HS"),
471 SND_SOC_DAPM_ADC("ADC", NULL, CS42L42_PWR_CTL1, CS42L42_ADC_PDN_SHIFT, 1),
472 SND_SOC_DAPM_AIF_OUT("SDOUT1", NULL, 0, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH1_SHIFT, 0),
473 SND_SOC_DAPM_AIF_OUT("SDOUT2", NULL, 1, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH2_SHIFT, 0),
474
475 /* Capture Requirements */
476 SND_SOC_DAPM_SUPPLY("ASP DAO0", CS42L42_PWR_CTL1, CS42L42_ASP_DAO_PDN_SHIFT, 1, NULL, 0),
477 SND_SOC_DAPM_SUPPLY("ASP TX EN", CS42L42_ASP_TX_SZ_EN, CS42L42_ASP_TX_EN_SHIFT, 0, NULL, 0),
478
479 /* Playback/Capture Requirements */
480 SND_SOC_DAPM_SUPPLY("SCLK", CS42L42_ASP_CLK_CFG, CS42L42_ASP_SCLK_EN_SHIFT, 0, NULL, 0),
481 };
482
483 static const struct snd_soc_dapm_route cs42l42_audio_map[] = {
484 /* Playback Path */
485 {"HP", NULL, "DAC"},
486 {"DAC", NULL, "MIXER"},
487 {"MIXER", NULL, "SDIN1"},
488 {"MIXER", NULL, "SDIN2"},
489 {"SDIN1", NULL, "Playback"},
490 {"SDIN2", NULL, "Playback"},
491
492 /* Playback Requirements */
493 {"SDIN1", NULL, "ASP DAI0"},
494 {"SDIN2", NULL, "ASP DAI0"},
495 {"SDIN1", NULL, "SCLK"},
496 {"SDIN2", NULL, "SCLK"},
497
498 /* Capture Path */
499 {"ADC", NULL, "HS"},
500 { "SDOUT1", NULL, "ADC" },
501 { "SDOUT2", NULL, "ADC" },
502 { "Capture", NULL, "SDOUT1" },
503 { "Capture", NULL, "SDOUT2" },
504
505 /* Capture Requirements */
506 { "SDOUT1", NULL, "ASP DAO0" },
507 { "SDOUT2", NULL, "ASP DAO0" },
508 { "SDOUT1", NULL, "SCLK" },
509 { "SDOUT2", NULL, "SCLK" },
510 { "SDOUT1", NULL, "ASP TX EN" },
511 { "SDOUT2", NULL, "ASP TX EN" },
512 };
513
cs42l42_set_jack(struct snd_soc_component * component,struct snd_soc_jack * jk,void * d)514 static int cs42l42_set_jack(struct snd_soc_component *component, struct snd_soc_jack *jk, void *d)
515 {
516 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
517
518 cs42l42->jack = jk;
519
520 regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK,
521 CS42L42_RS_PLUG_MASK | CS42L42_RS_UNPLUG_MASK |
522 CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK,
523 (1 << CS42L42_RS_PLUG_SHIFT) | (1 << CS42L42_RS_UNPLUG_SHIFT) |
524 (0 << CS42L42_TS_PLUG_SHIFT) | (0 << CS42L42_TS_UNPLUG_SHIFT));
525
526 return 0;
527 }
528
cs42l42_component_probe(struct snd_soc_component * component)529 static int cs42l42_component_probe(struct snd_soc_component *component)
530 {
531 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
532
533 cs42l42->component = component;
534
535 return 0;
536 }
537
538 static const struct snd_soc_component_driver soc_component_dev_cs42l42 = {
539 .probe = cs42l42_component_probe,
540 .set_jack = cs42l42_set_jack,
541 .dapm_widgets = cs42l42_dapm_widgets,
542 .num_dapm_widgets = ARRAY_SIZE(cs42l42_dapm_widgets),
543 .dapm_routes = cs42l42_audio_map,
544 .num_dapm_routes = ARRAY_SIZE(cs42l42_audio_map),
545 .controls = cs42l42_snd_controls,
546 .num_controls = ARRAY_SIZE(cs42l42_snd_controls),
547 .idle_bias_on = 1,
548 .endianness = 1,
549 .non_legacy_dai_naming = 1,
550 };
551
552 /* Switch to SCLK. Atomic delay after the write to allow the switch to complete. */
553 static const struct reg_sequence cs42l42_to_sclk_seq[] = {
554 {
555 .reg = CS42L42_OSC_SWITCH,
556 .def = CS42L42_SCLK_PRESENT_MASK,
557 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US,
558 },
559 };
560
561 /* Switch to OSC. Atomic delay after the write to allow the switch to complete. */
562 static const struct reg_sequence cs42l42_to_osc_seq[] = {
563 {
564 .reg = CS42L42_OSC_SWITCH,
565 .def = 0,
566 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US,
567 },
568 };
569
570 struct cs42l42_pll_params {
571 u32 sclk;
572 u8 mclk_div;
573 u8 mclk_src_sel;
574 u8 sclk_prediv;
575 u8 pll_div_int;
576 u32 pll_div_frac;
577 u8 pll_mode;
578 u8 pll_divout;
579 u32 mclk_int;
580 u8 pll_cal_ratio;
581 u8 n;
582 };
583
584 /*
585 * Common PLL Settings for given SCLK
586 * Table 4-5 from the Datasheet
587 */
588 static const struct cs42l42_pll_params pll_ratio_table[] = {
589 { 1411200, 0, 1, 0x00, 0x80, 0x000000, 0x03, 0x10, 11289600, 128, 2},
590 { 1536000, 0, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125, 2},
591 { 2304000, 0, 1, 0x00, 0x55, 0xC00000, 0x02, 0x10, 12288000, 85, 2},
592 { 2400000, 0, 1, 0x00, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2},
593 { 2822400, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
594 { 3000000, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
595 { 3072000, 0, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
596 { 4000000, 0, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96, 1},
597 { 4096000, 0, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94, 1},
598 { 5644800, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
599 { 6000000, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
600 { 6144000, 0, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
601 { 11289600, 0, 0, 0, 0, 0, 0, 0, 11289600, 0, 1},
602 { 12000000, 0, 0, 0, 0, 0, 0, 0, 12000000, 0, 1},
603 { 12288000, 0, 0, 0, 0, 0, 0, 0, 12288000, 0, 1},
604 { 22579200, 1, 0, 0, 0, 0, 0, 0, 22579200, 0, 1},
605 { 24000000, 1, 0, 0, 0, 0, 0, 0, 24000000, 0, 1},
606 { 24576000, 1, 0, 0, 0, 0, 0, 0, 24576000, 0, 1}
607 };
608
cs42l42_pll_config(struct snd_soc_component * component)609 static int cs42l42_pll_config(struct snd_soc_component *component)
610 {
611 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
612 int i;
613 u32 clk;
614 u32 fsync;
615
616 if (!cs42l42->sclk)
617 clk = cs42l42->bclk;
618 else
619 clk = cs42l42->sclk;
620
621 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
622 if (pll_ratio_table[i].sclk == clk) {
623 cs42l42->pll_config = i;
624
625 /* Configure the internal sample rate */
626 snd_soc_component_update_bits(component, CS42L42_MCLK_CTL,
627 CS42L42_INTERNAL_FS_MASK,
628 ((pll_ratio_table[i].mclk_int !=
629 12000000) &&
630 (pll_ratio_table[i].mclk_int !=
631 24000000)) <<
632 CS42L42_INTERNAL_FS_SHIFT);
633
634 snd_soc_component_update_bits(component, CS42L42_MCLK_SRC_SEL,
635 CS42L42_MCLKDIV_MASK,
636 (pll_ratio_table[i].mclk_div <<
637 CS42L42_MCLKDIV_SHIFT));
638 /* Set up the LRCLK */
639 fsync = clk / cs42l42->srate;
640 if (((fsync * cs42l42->srate) != clk)
641 || ((fsync % 2) != 0)) {
642 dev_err(component->dev,
643 "Unsupported sclk %d/sample rate %d\n",
644 clk,
645 cs42l42->srate);
646 return -EINVAL;
647 }
648 /* Set the LRCLK period */
649 snd_soc_component_update_bits(component,
650 CS42L42_FSYNC_P_LOWER,
651 CS42L42_FSYNC_PERIOD_MASK,
652 CS42L42_FRAC0_VAL(fsync - 1) <<
653 CS42L42_FSYNC_PERIOD_SHIFT);
654 snd_soc_component_update_bits(component,
655 CS42L42_FSYNC_P_UPPER,
656 CS42L42_FSYNC_PERIOD_MASK,
657 CS42L42_FRAC1_VAL(fsync - 1) <<
658 CS42L42_FSYNC_PERIOD_SHIFT);
659 /* Set the LRCLK to 50% duty cycle */
660 fsync = fsync / 2;
661 snd_soc_component_update_bits(component,
662 CS42L42_FSYNC_PW_LOWER,
663 CS42L42_FSYNC_PULSE_WIDTH_MASK,
664 CS42L42_FRAC0_VAL(fsync - 1) <<
665 CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
666 snd_soc_component_update_bits(component,
667 CS42L42_FSYNC_PW_UPPER,
668 CS42L42_FSYNC_PULSE_WIDTH_MASK,
669 CS42L42_FRAC1_VAL(fsync - 1) <<
670 CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
671 /* Set the sample rates (96k or lower) */
672 snd_soc_component_update_bits(component, CS42L42_FS_RATE_EN,
673 CS42L42_FS_EN_MASK,
674 (CS42L42_FS_EN_IASRC_96K |
675 CS42L42_FS_EN_OASRC_96K) <<
676 CS42L42_FS_EN_SHIFT);
677 /* Set the input/output internal MCLK clock ~12 MHz */
678 snd_soc_component_update_bits(component, CS42L42_IN_ASRC_CLK,
679 CS42L42_CLK_IASRC_SEL_MASK,
680 CS42L42_CLK_IASRC_SEL_12 <<
681 CS42L42_CLK_IASRC_SEL_SHIFT);
682 snd_soc_component_update_bits(component,
683 CS42L42_OUT_ASRC_CLK,
684 CS42L42_CLK_OASRC_SEL_MASK,
685 CS42L42_CLK_OASRC_SEL_12 <<
686 CS42L42_CLK_OASRC_SEL_SHIFT);
687 if (pll_ratio_table[i].mclk_src_sel == 0) {
688 /* Pass the clock straight through */
689 snd_soc_component_update_bits(component,
690 CS42L42_PLL_CTL1,
691 CS42L42_PLL_START_MASK, 0);
692 } else {
693 /* Configure PLL per table 4-5 */
694 snd_soc_component_update_bits(component,
695 CS42L42_PLL_DIV_CFG1,
696 CS42L42_SCLK_PREDIV_MASK,
697 pll_ratio_table[i].sclk_prediv
698 << CS42L42_SCLK_PREDIV_SHIFT);
699 snd_soc_component_update_bits(component,
700 CS42L42_PLL_DIV_INT,
701 CS42L42_PLL_DIV_INT_MASK,
702 pll_ratio_table[i].pll_div_int
703 << CS42L42_PLL_DIV_INT_SHIFT);
704 snd_soc_component_update_bits(component,
705 CS42L42_PLL_DIV_FRAC0,
706 CS42L42_PLL_DIV_FRAC_MASK,
707 CS42L42_FRAC0_VAL(
708 pll_ratio_table[i].pll_div_frac)
709 << CS42L42_PLL_DIV_FRAC_SHIFT);
710 snd_soc_component_update_bits(component,
711 CS42L42_PLL_DIV_FRAC1,
712 CS42L42_PLL_DIV_FRAC_MASK,
713 CS42L42_FRAC1_VAL(
714 pll_ratio_table[i].pll_div_frac)
715 << CS42L42_PLL_DIV_FRAC_SHIFT);
716 snd_soc_component_update_bits(component,
717 CS42L42_PLL_DIV_FRAC2,
718 CS42L42_PLL_DIV_FRAC_MASK,
719 CS42L42_FRAC2_VAL(
720 pll_ratio_table[i].pll_div_frac)
721 << CS42L42_PLL_DIV_FRAC_SHIFT);
722 snd_soc_component_update_bits(component,
723 CS42L42_PLL_CTL4,
724 CS42L42_PLL_MODE_MASK,
725 pll_ratio_table[i].pll_mode
726 << CS42L42_PLL_MODE_SHIFT);
727 snd_soc_component_update_bits(component,
728 CS42L42_PLL_CTL3,
729 CS42L42_PLL_DIVOUT_MASK,
730 (pll_ratio_table[i].pll_divout * pll_ratio_table[i].n)
731 << CS42L42_PLL_DIVOUT_SHIFT);
732 if (pll_ratio_table[i].n != 1)
733 cs42l42->pll_divout = pll_ratio_table[i].pll_divout;
734 else
735 cs42l42->pll_divout = 0;
736 snd_soc_component_update_bits(component,
737 CS42L42_PLL_CAL_RATIO,
738 CS42L42_PLL_CAL_RATIO_MASK,
739 pll_ratio_table[i].pll_cal_ratio
740 << CS42L42_PLL_CAL_RATIO_SHIFT);
741 }
742 return 0;
743 }
744 }
745
746 return -EINVAL;
747 }
748
cs42l42_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)749 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
750 {
751 struct snd_soc_component *component = codec_dai->component;
752 u32 asp_cfg_val = 0;
753
754 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
755 case SND_SOC_DAIFMT_CBS_CFM:
756 asp_cfg_val |= CS42L42_ASP_MASTER_MODE <<
757 CS42L42_ASP_MODE_SHIFT;
758 break;
759 case SND_SOC_DAIFMT_CBS_CFS:
760 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE <<
761 CS42L42_ASP_MODE_SHIFT;
762 break;
763 default:
764 return -EINVAL;
765 }
766
767 /* interface format */
768 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
769 case SND_SOC_DAIFMT_I2S:
770 /*
771 * 5050 mode, frame starts on falling edge of LRCLK,
772 * frame delayed by 1.0 SCLKs
773 */
774 snd_soc_component_update_bits(component,
775 CS42L42_ASP_FRM_CFG,
776 CS42L42_ASP_STP_MASK |
777 CS42L42_ASP_5050_MASK |
778 CS42L42_ASP_FSD_MASK,
779 CS42L42_ASP_5050_MASK |
780 (CS42L42_ASP_FSD_1_0 <<
781 CS42L42_ASP_FSD_SHIFT));
782 break;
783 default:
784 return -EINVAL;
785 }
786
787 /* Bitclock/frame inversion */
788 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
789 case SND_SOC_DAIFMT_NB_NF:
790 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
791 break;
792 case SND_SOC_DAIFMT_NB_IF:
793 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
794 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
795 break;
796 case SND_SOC_DAIFMT_IB_NF:
797 break;
798 case SND_SOC_DAIFMT_IB_IF:
799 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
800 break;
801 }
802
803 snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK |
804 CS42L42_ASP_SCPOL_MASK |
805 CS42L42_ASP_LCPOL_MASK,
806 asp_cfg_val);
807
808 return 0;
809 }
810
cs42l42_dai_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)811 static int cs42l42_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
812 {
813 struct snd_soc_component *component = dai->component;
814 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
815
816 /*
817 * Sample rates < 44.1 kHz would produce an out-of-range SCLK with
818 * a standard I2S frame. If the machine driver sets SCLK it must be
819 * legal.
820 */
821 if (cs42l42->sclk)
822 return 0;
823
824 /* Machine driver has not set a SCLK, limit bottom end to 44.1 kHz */
825 return snd_pcm_hw_constraint_minmax(substream->runtime,
826 SNDRV_PCM_HW_PARAM_RATE,
827 44100, 192000);
828 }
829
cs42l42_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)830 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
831 struct snd_pcm_hw_params *params,
832 struct snd_soc_dai *dai)
833 {
834 struct snd_soc_component *component = dai->component;
835 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
836 unsigned int channels = params_channels(params);
837 unsigned int width = (params_width(params) / 8) - 1;
838 unsigned int val = 0;
839
840 cs42l42->srate = params_rate(params);
841 cs42l42->bclk = snd_soc_params_to_bclk(params);
842
843 /* I2S frame always has 2 channels even for mono audio */
844 if (channels == 1)
845 cs42l42->bclk *= 2;
846
847 /*
848 * Assume 24-bit samples are in 32-bit slots, to prevent SCLK being
849 * more than assumed (which would result in overclocking).
850 */
851 if (params_width(params) == 24)
852 cs42l42->bclk = (cs42l42->bclk / 3) * 4;
853
854 switch(substream->stream) {
855 case SNDRV_PCM_STREAM_CAPTURE:
856 /* channel 2 on high LRCLK */
857 val = CS42L42_ASP_TX_CH2_AP_MASK |
858 (width << CS42L42_ASP_TX_CH2_RES_SHIFT) |
859 (width << CS42L42_ASP_TX_CH1_RES_SHIFT);
860
861 snd_soc_component_update_bits(component, CS42L42_ASP_TX_CH_AP_RES,
862 CS42L42_ASP_TX_CH1_AP_MASK | CS42L42_ASP_TX_CH2_AP_MASK |
863 CS42L42_ASP_TX_CH2_RES_MASK | CS42L42_ASP_TX_CH1_RES_MASK, val);
864 break;
865 case SNDRV_PCM_STREAM_PLAYBACK:
866 val |= width << CS42L42_ASP_RX_CH_RES_SHIFT;
867 /* channel 1 on low LRCLK */
868 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES,
869 CS42L42_ASP_RX_CH_AP_MASK |
870 CS42L42_ASP_RX_CH_RES_MASK, val);
871 /* Channel 2 on high LRCLK */
872 val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT;
873 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES,
874 CS42L42_ASP_RX_CH_AP_MASK |
875 CS42L42_ASP_RX_CH_RES_MASK, val);
876
877 /* Channel B comes from the last active channel */
878 snd_soc_component_update_bits(component, CS42L42_SP_RX_CH_SEL,
879 CS42L42_SP_RX_CHB_SEL_MASK,
880 (channels - 1) << CS42L42_SP_RX_CHB_SEL_SHIFT);
881
882 /* Both LRCLK slots must be enabled */
883 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN,
884 CS42L42_ASP_RX0_CH_EN_MASK,
885 BIT(CS42L42_ASP_RX0_CH1_SHIFT) |
886 BIT(CS42L42_ASP_RX0_CH2_SHIFT));
887 break;
888 default:
889 break;
890 }
891
892 return cs42l42_pll_config(component);
893 }
894
cs42l42_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)895 static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
896 int clk_id, unsigned int freq, int dir)
897 {
898 struct snd_soc_component *component = dai->component;
899 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
900 int i;
901
902 if (freq == 0) {
903 cs42l42->sclk = 0;
904 return 0;
905 }
906
907 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
908 if (pll_ratio_table[i].sclk == freq) {
909 cs42l42->sclk = freq;
910 return 0;
911 }
912 }
913
914 dev_err(component->dev, "SCLK %u not supported\n", freq);
915
916 return -EINVAL;
917 }
918
cs42l42_mute_stream(struct snd_soc_dai * dai,int mute,int stream)919 static int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
920 {
921 struct snd_soc_component *component = dai->component;
922 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
923 unsigned int regval;
924 int ret;
925
926 if (mute) {
927 /* Mute the headphone */
928 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
929 snd_soc_component_update_bits(component, CS42L42_HP_CTL,
930 CS42L42_HP_ANA_AMUTE_MASK |
931 CS42L42_HP_ANA_BMUTE_MASK,
932 CS42L42_HP_ANA_AMUTE_MASK |
933 CS42L42_HP_ANA_BMUTE_MASK);
934
935 cs42l42->stream_use &= ~(1 << stream);
936 if(!cs42l42->stream_use) {
937 /*
938 * Switch to the internal oscillator.
939 * SCLK must remain running until after this clock switch.
940 * Without a source of clock the I2C bus doesn't work.
941 */
942 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_osc_seq,
943 ARRAY_SIZE(cs42l42_to_osc_seq));
944
945 /* Must disconnect PLL before stopping it */
946 snd_soc_component_update_bits(component,
947 CS42L42_MCLK_SRC_SEL,
948 CS42L42_MCLK_SRC_SEL_MASK,
949 0);
950 usleep_range(100, 200);
951
952 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
953 CS42L42_PLL_START_MASK, 0);
954 }
955 } else {
956 if (!cs42l42->stream_use) {
957 /* SCLK must be running before codec unmute */
958 if (pll_ratio_table[cs42l42->pll_config].mclk_src_sel) {
959 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
960 CS42L42_PLL_START_MASK, 1);
961
962 if (cs42l42->pll_divout) {
963 usleep_range(CS42L42_PLL_DIVOUT_TIME_US,
964 CS42L42_PLL_DIVOUT_TIME_US * 2);
965 snd_soc_component_update_bits(component, CS42L42_PLL_CTL3,
966 CS42L42_PLL_DIVOUT_MASK,
967 cs42l42->pll_divout <<
968 CS42L42_PLL_DIVOUT_SHIFT);
969 }
970
971 ret = regmap_read_poll_timeout(cs42l42->regmap,
972 CS42L42_PLL_LOCK_STATUS,
973 regval,
974 (regval & 1),
975 CS42L42_PLL_LOCK_POLL_US,
976 CS42L42_PLL_LOCK_TIMEOUT_US);
977 if (ret < 0)
978 dev_warn(component->dev, "PLL failed to lock: %d\n", ret);
979
980 /* PLL must be running to drive glitchless switch logic */
981 snd_soc_component_update_bits(component,
982 CS42L42_MCLK_SRC_SEL,
983 CS42L42_MCLK_SRC_SEL_MASK,
984 CS42L42_MCLK_SRC_SEL_MASK);
985 }
986
987 /* Mark SCLK as present, turn off internal oscillator */
988 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_sclk_seq,
989 ARRAY_SIZE(cs42l42_to_sclk_seq));
990 }
991 cs42l42->stream_use |= 1 << stream;
992
993 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
994 /* Un-mute the headphone */
995 snd_soc_component_update_bits(component, CS42L42_HP_CTL,
996 CS42L42_HP_ANA_AMUTE_MASK |
997 CS42L42_HP_ANA_BMUTE_MASK,
998 0);
999 }
1000 }
1001
1002 return 0;
1003 }
1004
1005 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1006 SNDRV_PCM_FMTBIT_S24_LE |\
1007 SNDRV_PCM_FMTBIT_S32_LE )
1008
1009 static const struct snd_soc_dai_ops cs42l42_ops = {
1010 .startup = cs42l42_dai_startup,
1011 .hw_params = cs42l42_pcm_hw_params,
1012 .set_fmt = cs42l42_set_dai_fmt,
1013 .set_sysclk = cs42l42_set_sysclk,
1014 .mute_stream = cs42l42_mute_stream,
1015 };
1016
1017 static struct snd_soc_dai_driver cs42l42_dai = {
1018 .name = "cs42l42",
1019 .playback = {
1020 .stream_name = "Playback",
1021 .channels_min = 1,
1022 .channels_max = 2,
1023 .rates = SNDRV_PCM_RATE_8000_192000,
1024 .formats = CS42L42_FORMATS,
1025 },
1026 .capture = {
1027 .stream_name = "Capture",
1028 .channels_min = 1,
1029 .channels_max = 2,
1030 .rates = SNDRV_PCM_RATE_8000_192000,
1031 .formats = CS42L42_FORMATS,
1032 },
1033 .symmetric_rate = 1,
1034 .symmetric_sample_bits = 1,
1035 .ops = &cs42l42_ops,
1036 };
1037
cs42l42_process_hs_type_detect(struct cs42l42_private * cs42l42)1038 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42)
1039 {
1040 unsigned int hs_det_status;
1041 unsigned int int_status;
1042
1043 /* Mask the auto detect interrupt */
1044 regmap_update_bits(cs42l42->regmap,
1045 CS42L42_CODEC_INT_MASK,
1046 CS42L42_PDN_DONE_MASK |
1047 CS42L42_HSDET_AUTO_DONE_MASK,
1048 (1 << CS42L42_PDN_DONE_SHIFT) |
1049 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1050
1051 /* Set hs detect to automatic, disabled mode */
1052 regmap_update_bits(cs42l42->regmap,
1053 CS42L42_HSDET_CTL2,
1054 CS42L42_HSDET_CTRL_MASK |
1055 CS42L42_HSDET_SET_MASK |
1056 CS42L42_HSBIAS_REF_MASK |
1057 CS42L42_HSDET_AUTO_TIME_MASK,
1058 (2 << CS42L42_HSDET_CTRL_SHIFT) |
1059 (2 << CS42L42_HSDET_SET_SHIFT) |
1060 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1061 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1062
1063 /* Read and save the hs detection result */
1064 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
1065
1066 cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >>
1067 CS42L42_HSDET_TYPE_SHIFT;
1068
1069 /* Set up button detection */
1070 if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) ||
1071 (cs42l42->hs_type == CS42L42_PLUG_OMTP)) {
1072 /* Set auto HS bias settings to default */
1073 regmap_update_bits(cs42l42->regmap,
1074 CS42L42_HSBIAS_SC_AUTOCTL,
1075 CS42L42_HSBIAS_SENSE_EN_MASK |
1076 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1077 CS42L42_TIP_SENSE_EN_MASK |
1078 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1079 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1080 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1081 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1082 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1083
1084 /* Set up hs detect level sensitivity */
1085 regmap_update_bits(cs42l42->regmap,
1086 CS42L42_MIC_DET_CTL1,
1087 CS42L42_LATCH_TO_VP_MASK |
1088 CS42L42_EVENT_STAT_SEL_MASK |
1089 CS42L42_HS_DET_LEVEL_MASK,
1090 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1091 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1092 (cs42l42->bias_thresholds[0] <<
1093 CS42L42_HS_DET_LEVEL_SHIFT));
1094
1095 /* Set auto HS bias settings to default */
1096 regmap_update_bits(cs42l42->regmap,
1097 CS42L42_HSBIAS_SC_AUTOCTL,
1098 CS42L42_HSBIAS_SENSE_EN_MASK |
1099 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1100 CS42L42_TIP_SENSE_EN_MASK |
1101 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1102 (cs42l42->hs_bias_sense_en << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1103 (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1104 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1105 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1106
1107 /* Turn on level detect circuitry */
1108 regmap_update_bits(cs42l42->regmap,
1109 CS42L42_MISC_DET_CTL,
1110 CS42L42_DETECT_MODE_MASK |
1111 CS42L42_HSBIAS_CTL_MASK |
1112 CS42L42_PDN_MIC_LVL_DET_MASK,
1113 (0 << CS42L42_DETECT_MODE_SHIFT) |
1114 (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1115 (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1116
1117 msleep(cs42l42->btn_det_init_dbnce);
1118
1119 /* Clear any button interrupts before unmasking them */
1120 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1121 &int_status);
1122
1123 /* Unmask button detect interrupts */
1124 regmap_update_bits(cs42l42->regmap,
1125 CS42L42_DET_INT2_MASK,
1126 CS42L42_M_DETECT_TF_MASK |
1127 CS42L42_M_DETECT_FT_MASK |
1128 CS42L42_M_HSBIAS_HIZ_MASK |
1129 CS42L42_M_SHORT_RLS_MASK |
1130 CS42L42_M_SHORT_DET_MASK,
1131 (0 << CS42L42_M_DETECT_TF_SHIFT) |
1132 (0 << CS42L42_M_DETECT_FT_SHIFT) |
1133 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1134 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1135 (1 << CS42L42_M_SHORT_DET_SHIFT));
1136 } else {
1137 /* Make sure button detect and HS bias circuits are off */
1138 regmap_update_bits(cs42l42->regmap,
1139 CS42L42_MISC_DET_CTL,
1140 CS42L42_DETECT_MODE_MASK |
1141 CS42L42_HSBIAS_CTL_MASK |
1142 CS42L42_PDN_MIC_LVL_DET_MASK,
1143 (0 << CS42L42_DETECT_MODE_SHIFT) |
1144 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1145 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1146 }
1147
1148 regmap_update_bits(cs42l42->regmap,
1149 CS42L42_DAC_CTL2,
1150 CS42L42_HPOUT_PULLDOWN_MASK |
1151 CS42L42_HPOUT_LOAD_MASK |
1152 CS42L42_HPOUT_CLAMP_MASK |
1153 CS42L42_DAC_HPF_EN_MASK |
1154 CS42L42_DAC_MON_EN_MASK,
1155 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1156 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1157 (0 << CS42L42_HPOUT_CLAMP_SHIFT) |
1158 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1159 (0 << CS42L42_DAC_MON_EN_SHIFT));
1160
1161 /* Unmask tip sense interrupts */
1162 regmap_update_bits(cs42l42->regmap,
1163 CS42L42_TSRS_PLUG_INT_MASK,
1164 CS42L42_RS_PLUG_MASK |
1165 CS42L42_RS_UNPLUG_MASK |
1166 CS42L42_TS_PLUG_MASK |
1167 CS42L42_TS_UNPLUG_MASK,
1168 (1 << CS42L42_RS_PLUG_SHIFT) |
1169 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1170 (0 << CS42L42_TS_PLUG_SHIFT) |
1171 (0 << CS42L42_TS_UNPLUG_SHIFT));
1172 }
1173
cs42l42_init_hs_type_detect(struct cs42l42_private * cs42l42)1174 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42)
1175 {
1176 /* Mask tip sense interrupts */
1177 regmap_update_bits(cs42l42->regmap,
1178 CS42L42_TSRS_PLUG_INT_MASK,
1179 CS42L42_RS_PLUG_MASK |
1180 CS42L42_RS_UNPLUG_MASK |
1181 CS42L42_TS_PLUG_MASK |
1182 CS42L42_TS_UNPLUG_MASK,
1183 (1 << CS42L42_RS_PLUG_SHIFT) |
1184 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1185 (1 << CS42L42_TS_PLUG_SHIFT) |
1186 (1 << CS42L42_TS_UNPLUG_SHIFT));
1187
1188 /* Make sure button detect and HS bias circuits are off */
1189 regmap_update_bits(cs42l42->regmap,
1190 CS42L42_MISC_DET_CTL,
1191 CS42L42_DETECT_MODE_MASK |
1192 CS42L42_HSBIAS_CTL_MASK |
1193 CS42L42_PDN_MIC_LVL_DET_MASK,
1194 (0 << CS42L42_DETECT_MODE_SHIFT) |
1195 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1196 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1197
1198 /* Set auto HS bias settings to default */
1199 regmap_update_bits(cs42l42->regmap,
1200 CS42L42_HSBIAS_SC_AUTOCTL,
1201 CS42L42_HSBIAS_SENSE_EN_MASK |
1202 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1203 CS42L42_TIP_SENSE_EN_MASK |
1204 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1205 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1206 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1207 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1208 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1209
1210 /* Set hs detect to manual, disabled mode */
1211 regmap_update_bits(cs42l42->regmap,
1212 CS42L42_HSDET_CTL2,
1213 CS42L42_HSDET_CTRL_MASK |
1214 CS42L42_HSDET_SET_MASK |
1215 CS42L42_HSBIAS_REF_MASK |
1216 CS42L42_HSDET_AUTO_TIME_MASK,
1217 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1218 (2 << CS42L42_HSDET_SET_SHIFT) |
1219 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1220 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1221
1222 regmap_update_bits(cs42l42->regmap,
1223 CS42L42_DAC_CTL2,
1224 CS42L42_HPOUT_PULLDOWN_MASK |
1225 CS42L42_HPOUT_LOAD_MASK |
1226 CS42L42_HPOUT_CLAMP_MASK |
1227 CS42L42_DAC_HPF_EN_MASK |
1228 CS42L42_DAC_MON_EN_MASK,
1229 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1230 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1231 (1 << CS42L42_HPOUT_CLAMP_SHIFT) |
1232 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1233 (1 << CS42L42_DAC_MON_EN_SHIFT));
1234
1235 /* Power up HS bias to 2.7V */
1236 regmap_update_bits(cs42l42->regmap,
1237 CS42L42_MISC_DET_CTL,
1238 CS42L42_DETECT_MODE_MASK |
1239 CS42L42_HSBIAS_CTL_MASK |
1240 CS42L42_PDN_MIC_LVL_DET_MASK,
1241 (0 << CS42L42_DETECT_MODE_SHIFT) |
1242 (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1243 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1244
1245 /* Wait for HS bias to ramp up */
1246 msleep(cs42l42->hs_bias_ramp_time);
1247
1248 /* Unmask auto detect interrupt */
1249 regmap_update_bits(cs42l42->regmap,
1250 CS42L42_CODEC_INT_MASK,
1251 CS42L42_PDN_DONE_MASK |
1252 CS42L42_HSDET_AUTO_DONE_MASK,
1253 (1 << CS42L42_PDN_DONE_SHIFT) |
1254 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1255
1256 /* Set hs detect to automatic, enabled mode */
1257 regmap_update_bits(cs42l42->regmap,
1258 CS42L42_HSDET_CTL2,
1259 CS42L42_HSDET_CTRL_MASK |
1260 CS42L42_HSDET_SET_MASK |
1261 CS42L42_HSBIAS_REF_MASK |
1262 CS42L42_HSDET_AUTO_TIME_MASK,
1263 (3 << CS42L42_HSDET_CTRL_SHIFT) |
1264 (2 << CS42L42_HSDET_SET_SHIFT) |
1265 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1266 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1267 }
1268
cs42l42_cancel_hs_type_detect(struct cs42l42_private * cs42l42)1269 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42)
1270 {
1271 /* Mask button detect interrupts */
1272 regmap_update_bits(cs42l42->regmap,
1273 CS42L42_DET_INT2_MASK,
1274 CS42L42_M_DETECT_TF_MASK |
1275 CS42L42_M_DETECT_FT_MASK |
1276 CS42L42_M_HSBIAS_HIZ_MASK |
1277 CS42L42_M_SHORT_RLS_MASK |
1278 CS42L42_M_SHORT_DET_MASK,
1279 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1280 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1281 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1282 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1283 (1 << CS42L42_M_SHORT_DET_SHIFT));
1284
1285 /* Ground HS bias */
1286 regmap_update_bits(cs42l42->regmap,
1287 CS42L42_MISC_DET_CTL,
1288 CS42L42_DETECT_MODE_MASK |
1289 CS42L42_HSBIAS_CTL_MASK |
1290 CS42L42_PDN_MIC_LVL_DET_MASK,
1291 (0 << CS42L42_DETECT_MODE_SHIFT) |
1292 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1293 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1294
1295 /* Set auto HS bias settings to default */
1296 regmap_update_bits(cs42l42->regmap,
1297 CS42L42_HSBIAS_SC_AUTOCTL,
1298 CS42L42_HSBIAS_SENSE_EN_MASK |
1299 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1300 CS42L42_TIP_SENSE_EN_MASK |
1301 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1302 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1303 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1304 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1305 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1306
1307 /* Set hs detect to manual, disabled mode */
1308 regmap_update_bits(cs42l42->regmap,
1309 CS42L42_HSDET_CTL2,
1310 CS42L42_HSDET_CTRL_MASK |
1311 CS42L42_HSDET_SET_MASK |
1312 CS42L42_HSBIAS_REF_MASK |
1313 CS42L42_HSDET_AUTO_TIME_MASK,
1314 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1315 (2 << CS42L42_HSDET_SET_SHIFT) |
1316 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1317 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1318 }
1319
cs42l42_handle_button_press(struct cs42l42_private * cs42l42)1320 static int cs42l42_handle_button_press(struct cs42l42_private *cs42l42)
1321 {
1322 int bias_level;
1323 unsigned int detect_status;
1324
1325 /* Mask button detect interrupts */
1326 regmap_update_bits(cs42l42->regmap,
1327 CS42L42_DET_INT2_MASK,
1328 CS42L42_M_DETECT_TF_MASK |
1329 CS42L42_M_DETECT_FT_MASK |
1330 CS42L42_M_HSBIAS_HIZ_MASK |
1331 CS42L42_M_SHORT_RLS_MASK |
1332 CS42L42_M_SHORT_DET_MASK,
1333 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1334 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1335 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1336 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1337 (1 << CS42L42_M_SHORT_DET_SHIFT));
1338
1339 usleep_range(cs42l42->btn_det_event_dbnce * 1000,
1340 cs42l42->btn_det_event_dbnce * 2000);
1341
1342 /* Test all 4 level detect biases */
1343 bias_level = 1;
1344 do {
1345 /* Adjust button detect level sensitivity */
1346 regmap_update_bits(cs42l42->regmap,
1347 CS42L42_MIC_DET_CTL1,
1348 CS42L42_LATCH_TO_VP_MASK |
1349 CS42L42_EVENT_STAT_SEL_MASK |
1350 CS42L42_HS_DET_LEVEL_MASK,
1351 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1352 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1353 (cs42l42->bias_thresholds[bias_level] <<
1354 CS42L42_HS_DET_LEVEL_SHIFT));
1355
1356 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2,
1357 &detect_status);
1358 } while ((detect_status & CS42L42_HS_TRUE_MASK) &&
1359 (++bias_level < CS42L42_NUM_BIASES));
1360
1361 switch (bias_level) {
1362 case 1: /* Function C button press */
1363 bias_level = SND_JACK_BTN_2;
1364 dev_dbg(cs42l42->component->dev, "Function C button press\n");
1365 break;
1366 case 2: /* Function B button press */
1367 bias_level = SND_JACK_BTN_1;
1368 dev_dbg(cs42l42->component->dev, "Function B button press\n");
1369 break;
1370 case 3: /* Function D button press */
1371 bias_level = SND_JACK_BTN_3;
1372 dev_dbg(cs42l42->component->dev, "Function D button press\n");
1373 break;
1374 case 4: /* Function A button press */
1375 bias_level = SND_JACK_BTN_0;
1376 dev_dbg(cs42l42->component->dev, "Function A button press\n");
1377 break;
1378 default:
1379 bias_level = 0;
1380 break;
1381 }
1382
1383 /* Set button detect level sensitivity back to default */
1384 regmap_update_bits(cs42l42->regmap,
1385 CS42L42_MIC_DET_CTL1,
1386 CS42L42_LATCH_TO_VP_MASK |
1387 CS42L42_EVENT_STAT_SEL_MASK |
1388 CS42L42_HS_DET_LEVEL_MASK,
1389 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1390 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1391 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT));
1392
1393 /* Clear any button interrupts before unmasking them */
1394 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1395 &detect_status);
1396
1397 /* Unmask button detect interrupts */
1398 regmap_update_bits(cs42l42->regmap,
1399 CS42L42_DET_INT2_MASK,
1400 CS42L42_M_DETECT_TF_MASK |
1401 CS42L42_M_DETECT_FT_MASK |
1402 CS42L42_M_HSBIAS_HIZ_MASK |
1403 CS42L42_M_SHORT_RLS_MASK |
1404 CS42L42_M_SHORT_DET_MASK,
1405 (0 << CS42L42_M_DETECT_TF_SHIFT) |
1406 (0 << CS42L42_M_DETECT_FT_SHIFT) |
1407 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1408 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1409 (1 << CS42L42_M_SHORT_DET_SHIFT));
1410
1411 return bias_level;
1412 }
1413
1414 struct cs42l42_irq_params {
1415 u16 status_addr;
1416 u16 mask_addr;
1417 u8 mask;
1418 };
1419
1420 static const struct cs42l42_irq_params irq_params_table[] = {
1421 {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK,
1422 CS42L42_ADC_OVFL_VAL_MASK},
1423 {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK,
1424 CS42L42_MIXER_VAL_MASK},
1425 {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK,
1426 CS42L42_SRC_VAL_MASK},
1427 {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK,
1428 CS42L42_ASP_RX_VAL_MASK},
1429 {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK,
1430 CS42L42_ASP_TX_VAL_MASK},
1431 {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK,
1432 CS42L42_CODEC_VAL_MASK},
1433 {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK,
1434 CS42L42_DET_INT_VAL1_MASK},
1435 {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK,
1436 CS42L42_DET_INT_VAL2_MASK},
1437 {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK,
1438 CS42L42_SRCPL_VAL_MASK},
1439 {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK,
1440 CS42L42_VPMON_VAL_MASK},
1441 {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK,
1442 CS42L42_PLL_LOCK_VAL_MASK},
1443 {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK,
1444 CS42L42_TSRS_PLUG_VAL_MASK}
1445 };
1446
cs42l42_irq_thread(int irq,void * data)1447 static irqreturn_t cs42l42_irq_thread(int irq, void *data)
1448 {
1449 struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data;
1450 struct snd_soc_component *component = cs42l42->component;
1451 unsigned int stickies[12];
1452 unsigned int masks[12];
1453 unsigned int current_plug_status;
1454 unsigned int current_button_status;
1455 unsigned int i;
1456 int report = 0;
1457
1458
1459 /* Read sticky registers to clear interurpt */
1460 for (i = 0; i < ARRAY_SIZE(stickies); i++) {
1461 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr,
1462 &(stickies[i]));
1463 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr,
1464 &(masks[i]));
1465 stickies[i] = stickies[i] & (~masks[i]) &
1466 irq_params_table[i].mask;
1467 }
1468
1469 /* Read tip sense status before handling type detect */
1470 current_plug_status = (stickies[11] &
1471 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1472 CS42L42_TS_PLUG_SHIFT;
1473
1474 /* Read button sense status */
1475 current_button_status = stickies[7] &
1476 (CS42L42_M_DETECT_TF_MASK |
1477 CS42L42_M_DETECT_FT_MASK |
1478 CS42L42_M_HSBIAS_HIZ_MASK);
1479
1480 /* Check auto-detect status */
1481 if ((~masks[5]) & irq_params_table[5].mask) {
1482 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) {
1483 cs42l42_process_hs_type_detect(cs42l42);
1484 switch(cs42l42->hs_type){
1485 case CS42L42_PLUG_CTIA:
1486 case CS42L42_PLUG_OMTP:
1487 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADSET,
1488 SND_JACK_HEADSET);
1489 break;
1490 case CS42L42_PLUG_HEADPHONE:
1491 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADPHONE,
1492 SND_JACK_HEADPHONE);
1493 break;
1494 default:
1495 break;
1496 }
1497 dev_dbg(component->dev, "Auto detect done (%d)\n", cs42l42->hs_type);
1498 }
1499 }
1500
1501 /* Check tip sense status */
1502 if ((~masks[11]) & irq_params_table[11].mask) {
1503 switch (current_plug_status) {
1504 case CS42L42_TS_PLUG:
1505 if (cs42l42->plug_state != CS42L42_TS_PLUG) {
1506 cs42l42->plug_state = CS42L42_TS_PLUG;
1507 cs42l42_init_hs_type_detect(cs42l42);
1508 }
1509 break;
1510
1511 case CS42L42_TS_UNPLUG:
1512 if (cs42l42->plug_state != CS42L42_TS_UNPLUG) {
1513 cs42l42->plug_state = CS42L42_TS_UNPLUG;
1514 cs42l42_cancel_hs_type_detect(cs42l42);
1515
1516 switch(cs42l42->hs_type){
1517 case CS42L42_PLUG_CTIA:
1518 case CS42L42_PLUG_OMTP:
1519 snd_soc_jack_report(cs42l42->jack, 0, SND_JACK_HEADSET);
1520 break;
1521 case CS42L42_PLUG_HEADPHONE:
1522 snd_soc_jack_report(cs42l42->jack, 0, SND_JACK_HEADPHONE);
1523 break;
1524 default:
1525 break;
1526 }
1527 snd_soc_jack_report(cs42l42->jack, 0,
1528 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1529 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1530
1531 dev_dbg(component->dev, "Unplug event\n");
1532 }
1533 break;
1534
1535 default:
1536 if (cs42l42->plug_state != CS42L42_TS_TRANS)
1537 cs42l42->plug_state = CS42L42_TS_TRANS;
1538 }
1539 }
1540
1541 /* Check button detect status */
1542 if (cs42l42->plug_state == CS42L42_TS_PLUG && ((~masks[7]) & irq_params_table[7].mask)) {
1543 if (!(current_button_status &
1544 CS42L42_M_HSBIAS_HIZ_MASK)) {
1545
1546 if (current_button_status & CS42L42_M_DETECT_TF_MASK) {
1547 dev_dbg(component->dev, "Button released\n");
1548 report = 0;
1549 } else if (current_button_status & CS42L42_M_DETECT_FT_MASK) {
1550 report = cs42l42_handle_button_press(cs42l42);
1551
1552 }
1553 snd_soc_jack_report(cs42l42->jack, report, SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1554 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1555 }
1556 }
1557
1558 return IRQ_HANDLED;
1559 }
1560
cs42l42_set_interrupt_masks(struct cs42l42_private * cs42l42)1561 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42)
1562 {
1563 regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK,
1564 CS42L42_ADC_OVFL_MASK,
1565 (1 << CS42L42_ADC_OVFL_SHIFT));
1566
1567 regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK,
1568 CS42L42_MIX_CHB_OVFL_MASK |
1569 CS42L42_MIX_CHA_OVFL_MASK |
1570 CS42L42_EQ_OVFL_MASK |
1571 CS42L42_EQ_BIQUAD_OVFL_MASK,
1572 (1 << CS42L42_MIX_CHB_OVFL_SHIFT) |
1573 (1 << CS42L42_MIX_CHA_OVFL_SHIFT) |
1574 (1 << CS42L42_EQ_OVFL_SHIFT) |
1575 (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT));
1576
1577 regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK,
1578 CS42L42_SRC_ILK_MASK |
1579 CS42L42_SRC_OLK_MASK |
1580 CS42L42_SRC_IUNLK_MASK |
1581 CS42L42_SRC_OUNLK_MASK,
1582 (1 << CS42L42_SRC_ILK_SHIFT) |
1583 (1 << CS42L42_SRC_OLK_SHIFT) |
1584 (1 << CS42L42_SRC_IUNLK_SHIFT) |
1585 (1 << CS42L42_SRC_OUNLK_SHIFT));
1586
1587 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK,
1588 CS42L42_ASPRX_NOLRCK_MASK |
1589 CS42L42_ASPRX_EARLY_MASK |
1590 CS42L42_ASPRX_LATE_MASK |
1591 CS42L42_ASPRX_ERROR_MASK |
1592 CS42L42_ASPRX_OVLD_MASK,
1593 (1 << CS42L42_ASPRX_NOLRCK_SHIFT) |
1594 (1 << CS42L42_ASPRX_EARLY_SHIFT) |
1595 (1 << CS42L42_ASPRX_LATE_SHIFT) |
1596 (1 << CS42L42_ASPRX_ERROR_SHIFT) |
1597 (1 << CS42L42_ASPRX_OVLD_SHIFT));
1598
1599 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK,
1600 CS42L42_ASPTX_NOLRCK_MASK |
1601 CS42L42_ASPTX_EARLY_MASK |
1602 CS42L42_ASPTX_LATE_MASK |
1603 CS42L42_ASPTX_SMERROR_MASK,
1604 (1 << CS42L42_ASPTX_NOLRCK_SHIFT) |
1605 (1 << CS42L42_ASPTX_EARLY_SHIFT) |
1606 (1 << CS42L42_ASPTX_LATE_SHIFT) |
1607 (1 << CS42L42_ASPTX_SMERROR_SHIFT));
1608
1609 regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK,
1610 CS42L42_PDN_DONE_MASK |
1611 CS42L42_HSDET_AUTO_DONE_MASK,
1612 (1 << CS42L42_PDN_DONE_SHIFT) |
1613 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1614
1615 regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK,
1616 CS42L42_SRCPL_ADC_LK_MASK |
1617 CS42L42_SRCPL_DAC_LK_MASK |
1618 CS42L42_SRCPL_ADC_UNLK_MASK |
1619 CS42L42_SRCPL_DAC_UNLK_MASK,
1620 (1 << CS42L42_SRCPL_ADC_LK_SHIFT) |
1621 (1 << CS42L42_SRCPL_DAC_LK_SHIFT) |
1622 (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) |
1623 (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT));
1624
1625 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK,
1626 CS42L42_TIP_SENSE_UNPLUG_MASK |
1627 CS42L42_TIP_SENSE_PLUG_MASK |
1628 CS42L42_HSBIAS_SENSE_MASK,
1629 (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) |
1630 (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) |
1631 (1 << CS42L42_HSBIAS_SENSE_SHIFT));
1632
1633 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK,
1634 CS42L42_M_DETECT_TF_MASK |
1635 CS42L42_M_DETECT_FT_MASK |
1636 CS42L42_M_HSBIAS_HIZ_MASK |
1637 CS42L42_M_SHORT_RLS_MASK |
1638 CS42L42_M_SHORT_DET_MASK,
1639 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1640 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1641 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1642 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1643 (1 << CS42L42_M_SHORT_DET_SHIFT));
1644
1645 regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK,
1646 CS42L42_VPMON_MASK,
1647 (1 << CS42L42_VPMON_SHIFT));
1648
1649 regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK,
1650 CS42L42_PLL_LOCK_MASK,
1651 (1 << CS42L42_PLL_LOCK_SHIFT));
1652
1653 regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK,
1654 CS42L42_RS_PLUG_MASK |
1655 CS42L42_RS_UNPLUG_MASK |
1656 CS42L42_TS_PLUG_MASK |
1657 CS42L42_TS_UNPLUG_MASK,
1658 (1 << CS42L42_RS_PLUG_SHIFT) |
1659 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1660 (1 << CS42L42_TS_PLUG_SHIFT) |
1661 (1 << CS42L42_TS_UNPLUG_SHIFT));
1662 }
1663
cs42l42_setup_hs_type_detect(struct cs42l42_private * cs42l42)1664 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42)
1665 {
1666 unsigned int reg;
1667
1668 cs42l42->hs_type = CS42L42_PLUG_INVALID;
1669
1670 /* Latch analog controls to VP power domain */
1671 regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1,
1672 CS42L42_LATCH_TO_VP_MASK |
1673 CS42L42_EVENT_STAT_SEL_MASK |
1674 CS42L42_HS_DET_LEVEL_MASK,
1675 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1676 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1677 (cs42l42->bias_thresholds[0] <<
1678 CS42L42_HS_DET_LEVEL_SHIFT));
1679
1680 /* Remove ground noise-suppression clamps */
1681 regmap_update_bits(cs42l42->regmap,
1682 CS42L42_HS_CLAMP_DISABLE,
1683 CS42L42_HS_CLAMP_DISABLE_MASK,
1684 (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT));
1685
1686 /* Enable the tip sense circuit */
1687 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1688 CS42L42_TS_INV_MASK, CS42L42_TS_INV_MASK);
1689
1690 regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL,
1691 CS42L42_TIP_SENSE_CTRL_MASK |
1692 CS42L42_TIP_SENSE_INV_MASK |
1693 CS42L42_TIP_SENSE_DEBOUNCE_MASK,
1694 (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) |
1695 (!cs42l42->ts_inv << CS42L42_TIP_SENSE_INV_SHIFT) |
1696 (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT));
1697
1698 /* Save the initial status of the tip sense */
1699 regmap_read(cs42l42->regmap,
1700 CS42L42_TSRS_PLUG_STATUS,
1701 ®);
1702 cs42l42->plug_state = (((char) reg) &
1703 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1704 CS42L42_TS_PLUG_SHIFT;
1705 }
1706
1707 static const unsigned int threshold_defaults[] = {
1708 CS42L42_HS_DET_LEVEL_15,
1709 CS42L42_HS_DET_LEVEL_8,
1710 CS42L42_HS_DET_LEVEL_4,
1711 CS42L42_HS_DET_LEVEL_1
1712 };
1713
cs42l42_handle_device_data(struct device * dev,struct cs42l42_private * cs42l42)1714 static int cs42l42_handle_device_data(struct device *dev,
1715 struct cs42l42_private *cs42l42)
1716 {
1717 unsigned int val;
1718 u32 thresholds[CS42L42_NUM_BIASES];
1719 int ret;
1720 int i;
1721
1722 ret = device_property_read_u32(dev, "cirrus,ts-inv", &val);
1723 if (!ret) {
1724 switch (val) {
1725 case CS42L42_TS_INV_EN:
1726 case CS42L42_TS_INV_DIS:
1727 cs42l42->ts_inv = val;
1728 break;
1729 default:
1730 dev_err(dev,
1731 "Wrong cirrus,ts-inv DT value %d\n",
1732 val);
1733 cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1734 }
1735 } else {
1736 cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1737 }
1738
1739 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-rise", &val);
1740 if (!ret) {
1741 switch (val) {
1742 case CS42L42_TS_DBNCE_0:
1743 case CS42L42_TS_DBNCE_125:
1744 case CS42L42_TS_DBNCE_250:
1745 case CS42L42_TS_DBNCE_500:
1746 case CS42L42_TS_DBNCE_750:
1747 case CS42L42_TS_DBNCE_1000:
1748 case CS42L42_TS_DBNCE_1250:
1749 case CS42L42_TS_DBNCE_1500:
1750 cs42l42->ts_dbnc_rise = val;
1751 break;
1752 default:
1753 dev_err(dev,
1754 "Wrong cirrus,ts-dbnc-rise DT value %d\n",
1755 val);
1756 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1757 }
1758 } else {
1759 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1760 }
1761
1762 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1763 CS42L42_TS_RISE_DBNCE_TIME_MASK,
1764 (cs42l42->ts_dbnc_rise <<
1765 CS42L42_TS_RISE_DBNCE_TIME_SHIFT));
1766
1767 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-fall", &val);
1768 if (!ret) {
1769 switch (val) {
1770 case CS42L42_TS_DBNCE_0:
1771 case CS42L42_TS_DBNCE_125:
1772 case CS42L42_TS_DBNCE_250:
1773 case CS42L42_TS_DBNCE_500:
1774 case CS42L42_TS_DBNCE_750:
1775 case CS42L42_TS_DBNCE_1000:
1776 case CS42L42_TS_DBNCE_1250:
1777 case CS42L42_TS_DBNCE_1500:
1778 cs42l42->ts_dbnc_fall = val;
1779 break;
1780 default:
1781 dev_err(dev,
1782 "Wrong cirrus,ts-dbnc-fall DT value %d\n",
1783 val);
1784 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1785 }
1786 } else {
1787 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1788 }
1789
1790 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1791 CS42L42_TS_FALL_DBNCE_TIME_MASK,
1792 (cs42l42->ts_dbnc_fall <<
1793 CS42L42_TS_FALL_DBNCE_TIME_SHIFT));
1794
1795 ret = device_property_read_u32(dev, "cirrus,btn-det-init-dbnce", &val);
1796 if (!ret) {
1797 if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX)
1798 cs42l42->btn_det_init_dbnce = val;
1799 else {
1800 dev_err(dev,
1801 "Wrong cirrus,btn-det-init-dbnce DT value %d\n",
1802 val);
1803 cs42l42->btn_det_init_dbnce =
1804 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1805 }
1806 } else {
1807 cs42l42->btn_det_init_dbnce =
1808 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1809 }
1810
1811 ret = device_property_read_u32(dev, "cirrus,btn-det-event-dbnce", &val);
1812 if (!ret) {
1813 if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX)
1814 cs42l42->btn_det_event_dbnce = val;
1815 else {
1816 dev_err(dev,
1817 "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val);
1818 cs42l42->btn_det_event_dbnce =
1819 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1820 }
1821 } else {
1822 cs42l42->btn_det_event_dbnce =
1823 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1824 }
1825
1826 ret = device_property_read_u32_array(dev, "cirrus,bias-lvls",
1827 thresholds, ARRAY_SIZE(thresholds));
1828 if (!ret) {
1829 for (i = 0; i < CS42L42_NUM_BIASES; i++) {
1830 if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX)
1831 cs42l42->bias_thresholds[i] = thresholds[i];
1832 else {
1833 dev_err(dev,
1834 "Wrong cirrus,bias-lvls[%d] DT value %d\n", i,
1835 thresholds[i]);
1836 cs42l42->bias_thresholds[i] = threshold_defaults[i];
1837 }
1838 }
1839 } else {
1840 for (i = 0; i < CS42L42_NUM_BIASES; i++)
1841 cs42l42->bias_thresholds[i] = threshold_defaults[i];
1842 }
1843
1844 ret = device_property_read_u32(dev, "cirrus,hs-bias-ramp-rate", &val);
1845 if (!ret) {
1846 switch (val) {
1847 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL:
1848 cs42l42->hs_bias_ramp_rate = val;
1849 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0;
1850 break;
1851 case CS42L42_HSBIAS_RAMP_FAST:
1852 cs42l42->hs_bias_ramp_rate = val;
1853 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1;
1854 break;
1855 case CS42L42_HSBIAS_RAMP_SLOW:
1856 cs42l42->hs_bias_ramp_rate = val;
1857 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1858 break;
1859 case CS42L42_HSBIAS_RAMP_SLOWEST:
1860 cs42l42->hs_bias_ramp_rate = val;
1861 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3;
1862 break;
1863 default:
1864 dev_err(dev,
1865 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n",
1866 val);
1867 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
1868 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1869 }
1870 } else {
1871 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
1872 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1873 }
1874
1875 regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL,
1876 CS42L42_HSBIAS_RAMP_MASK,
1877 (cs42l42->hs_bias_ramp_rate <<
1878 CS42L42_HSBIAS_RAMP_SHIFT));
1879
1880 if (device_property_read_bool(dev, "cirrus,hs-bias-sense-disable"))
1881 cs42l42->hs_bias_sense_en = 0;
1882 else
1883 cs42l42->hs_bias_sense_en = 1;
1884
1885 return 0;
1886 }
1887
cs42l42_i2c_probe(struct i2c_client * i2c_client,const struct i2c_device_id * id)1888 static int cs42l42_i2c_probe(struct i2c_client *i2c_client,
1889 const struct i2c_device_id *id)
1890 {
1891 struct cs42l42_private *cs42l42;
1892 int ret, i, devid;
1893 unsigned int reg;
1894
1895 cs42l42 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l42_private),
1896 GFP_KERNEL);
1897 if (!cs42l42)
1898 return -ENOMEM;
1899
1900 i2c_set_clientdata(i2c_client, cs42l42);
1901
1902 cs42l42->regmap = devm_regmap_init_i2c(i2c_client, &cs42l42_regmap);
1903 if (IS_ERR(cs42l42->regmap)) {
1904 ret = PTR_ERR(cs42l42->regmap);
1905 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1906 return ret;
1907 }
1908
1909 for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++)
1910 cs42l42->supplies[i].supply = cs42l42_supply_names[i];
1911
1912 ret = devm_regulator_bulk_get(&i2c_client->dev,
1913 ARRAY_SIZE(cs42l42->supplies),
1914 cs42l42->supplies);
1915 if (ret != 0) {
1916 dev_err(&i2c_client->dev,
1917 "Failed to request supplies: %d\n", ret);
1918 return ret;
1919 }
1920
1921 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
1922 cs42l42->supplies);
1923 if (ret != 0) {
1924 dev_err(&i2c_client->dev,
1925 "Failed to enable supplies: %d\n", ret);
1926 return ret;
1927 }
1928
1929 /* Reset the Device */
1930 cs42l42->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
1931 "reset", GPIOD_OUT_LOW);
1932 if (IS_ERR(cs42l42->reset_gpio)) {
1933 ret = PTR_ERR(cs42l42->reset_gpio);
1934 goto err_disable;
1935 }
1936
1937 if (cs42l42->reset_gpio) {
1938 dev_dbg(&i2c_client->dev, "Found reset GPIO\n");
1939 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
1940 }
1941 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
1942
1943 /* Request IRQ */
1944 ret = devm_request_threaded_irq(&i2c_client->dev,
1945 i2c_client->irq,
1946 NULL, cs42l42_irq_thread,
1947 IRQF_ONESHOT | IRQF_TRIGGER_LOW,
1948 "cs42l42", cs42l42);
1949 if (ret == -EPROBE_DEFER)
1950 goto err_disable;
1951 else if (ret != 0)
1952 dev_err(&i2c_client->dev,
1953 "Failed to request IRQ: %d\n", ret);
1954
1955 /* initialize codec */
1956 devid = cirrus_read_device_id(cs42l42->regmap, CS42L42_DEVID_AB);
1957 if (devid < 0) {
1958 ret = devid;
1959 dev_err(&i2c_client->dev, "Failed to read device ID: %d\n", ret);
1960 goto err_disable;
1961 }
1962
1963 if (devid != CS42L42_CHIP_ID) {
1964 ret = -ENODEV;
1965 dev_err(&i2c_client->dev,
1966 "CS42L42 Device ID (%X). Expected %X\n",
1967 devid, CS42L42_CHIP_ID);
1968 goto err_disable;
1969 }
1970
1971 ret = regmap_read(cs42l42->regmap, CS42L42_REVID, ®);
1972 if (ret < 0) {
1973 dev_err(&i2c_client->dev, "Get Revision ID failed\n");
1974 goto err_disable;
1975 }
1976
1977 dev_info(&i2c_client->dev,
1978 "Cirrus Logic CS42L42, Revision: %02X\n", reg & 0xFF);
1979
1980 /* Power up the codec */
1981 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1,
1982 CS42L42_ASP_DAO_PDN_MASK |
1983 CS42L42_ASP_DAI_PDN_MASK |
1984 CS42L42_MIXER_PDN_MASK |
1985 CS42L42_EQ_PDN_MASK |
1986 CS42L42_HP_PDN_MASK |
1987 CS42L42_ADC_PDN_MASK |
1988 CS42L42_PDN_ALL_MASK,
1989 (1 << CS42L42_ASP_DAO_PDN_SHIFT) |
1990 (1 << CS42L42_ASP_DAI_PDN_SHIFT) |
1991 (1 << CS42L42_MIXER_PDN_SHIFT) |
1992 (1 << CS42L42_EQ_PDN_SHIFT) |
1993 (1 << CS42L42_HP_PDN_SHIFT) |
1994 (1 << CS42L42_ADC_PDN_SHIFT) |
1995 (0 << CS42L42_PDN_ALL_SHIFT));
1996
1997 ret = cs42l42_handle_device_data(&i2c_client->dev, cs42l42);
1998 if (ret != 0)
1999 goto err_disable;
2000
2001 /* Setup headset detection */
2002 cs42l42_setup_hs_type_detect(cs42l42);
2003
2004 /* Mask/Unmask Interrupts */
2005 cs42l42_set_interrupt_masks(cs42l42);
2006
2007 /* Register codec for machine driver */
2008 ret = devm_snd_soc_register_component(&i2c_client->dev,
2009 &soc_component_dev_cs42l42, &cs42l42_dai, 1);
2010 if (ret < 0)
2011 goto err_disable;
2012 return 0;
2013
2014 err_disable:
2015 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
2016 cs42l42->supplies);
2017 return ret;
2018 }
2019
cs42l42_i2c_remove(struct i2c_client * i2c_client)2020 static int cs42l42_i2c_remove(struct i2c_client *i2c_client)
2021 {
2022 struct cs42l42_private *cs42l42 = i2c_get_clientdata(i2c_client);
2023
2024 devm_free_irq(&i2c_client->dev, i2c_client->irq, cs42l42);
2025 pm_runtime_suspend(&i2c_client->dev);
2026 pm_runtime_disable(&i2c_client->dev);
2027
2028 return 0;
2029 }
2030
2031 #ifdef CONFIG_PM
cs42l42_runtime_suspend(struct device * dev)2032 static int cs42l42_runtime_suspend(struct device *dev)
2033 {
2034 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
2035
2036 regcache_cache_only(cs42l42->regmap, true);
2037 regcache_mark_dirty(cs42l42->regmap);
2038
2039 /* Hold down reset */
2040 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
2041
2042 /* remove power */
2043 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
2044 cs42l42->supplies);
2045
2046 return 0;
2047 }
2048
cs42l42_runtime_resume(struct device * dev)2049 static int cs42l42_runtime_resume(struct device *dev)
2050 {
2051 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
2052 int ret;
2053
2054 /* Enable power */
2055 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
2056 cs42l42->supplies);
2057 if (ret != 0) {
2058 dev_err(dev, "Failed to enable supplies: %d\n",
2059 ret);
2060 return ret;
2061 }
2062
2063 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
2064 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
2065
2066 regcache_cache_only(cs42l42->regmap, false);
2067 regcache_sync(cs42l42->regmap);
2068
2069 return 0;
2070 }
2071 #endif
2072
2073 static const struct dev_pm_ops cs42l42_runtime_pm = {
2074 SET_RUNTIME_PM_OPS(cs42l42_runtime_suspend, cs42l42_runtime_resume,
2075 NULL)
2076 };
2077
2078 #ifdef CONFIG_OF
2079 static const struct of_device_id cs42l42_of_match[] = {
2080 { .compatible = "cirrus,cs42l42", },
2081 {}
2082 };
2083 MODULE_DEVICE_TABLE(of, cs42l42_of_match);
2084 #endif
2085
2086 #ifdef CONFIG_ACPI
2087 static const struct acpi_device_id cs42l42_acpi_match[] = {
2088 {"10134242", 0,},
2089 {}
2090 };
2091 MODULE_DEVICE_TABLE(acpi, cs42l42_acpi_match);
2092 #endif
2093
2094 static const struct i2c_device_id cs42l42_id[] = {
2095 {"cs42l42", 0},
2096 {}
2097 };
2098
2099 MODULE_DEVICE_TABLE(i2c, cs42l42_id);
2100
2101 static struct i2c_driver cs42l42_i2c_driver = {
2102 .driver = {
2103 .name = "cs42l42",
2104 .pm = &cs42l42_runtime_pm,
2105 .of_match_table = of_match_ptr(cs42l42_of_match),
2106 .acpi_match_table = ACPI_PTR(cs42l42_acpi_match),
2107 },
2108 .id_table = cs42l42_id,
2109 .probe = cs42l42_i2c_probe,
2110 .remove = cs42l42_i2c_remove,
2111 };
2112
2113 module_i2c_driver(cs42l42_i2c_driver);
2114
2115 MODULE_DESCRIPTION("ASoC CS42L42 driver");
2116 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
2117 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
2118 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>");
2119 MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>");
2120 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
2121 MODULE_AUTHOR("Vitaly Rodionov <vitalyr@opensource.cirrus.com>");
2122 MODULE_LICENSE("GPL");
2123