1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * linux/sound/soc/codecs/tlv320aic32x4.c
4 *
5 * Copyright 2011 Vista Silicon S.L.
6 *
7 * Author: Javier Martin <javier.martin@vista-silicon.com>
8 *
9 * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
10 */
11
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
16 #include <linux/pm.h>
17 #include <linux/gpio.h>
18 #include <linux/of_gpio.h>
19 #include <linux/cdev.h>
20 #include <linux/slab.h>
21 #include <linux/clk.h>
22 #include <linux/of_clk.h>
23 #include <linux/regulator/consumer.h>
24
25 #include <sound/tlv320aic32x4.h>
26 #include <sound/core.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/soc-dapm.h>
31 #include <sound/initval.h>
32 #include <sound/tlv.h>
33
34 #include "tlv320aic32x4.h"
35
36 struct aic32x4_priv {
37 struct regmap *regmap;
38 u32 power_cfg;
39 u32 micpga_routing;
40 bool swapdacs;
41 int rstn_gpio;
42 const char *mclk_name;
43
44 struct regulator *supply_ldo;
45 struct regulator *supply_iov;
46 struct regulator *supply_dv;
47 struct regulator *supply_av;
48
49 struct aic32x4_setup_data *setup;
50 struct device *dev;
51 enum aic32x4_type type;
52
53 unsigned int fmt;
54 };
55
aic32x4_reset_adc(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)56 static int aic32x4_reset_adc(struct snd_soc_dapm_widget *w,
57 struct snd_kcontrol *kcontrol, int event)
58 {
59 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
60 u32 adc_reg;
61
62 /*
63 * Workaround: the datasheet does not mention a required programming
64 * sequence but experiments show the ADC needs to be reset after each
65 * capture to avoid audible artifacts.
66 */
67 switch (event) {
68 case SND_SOC_DAPM_POST_PMD:
69 adc_reg = snd_soc_component_read(component, AIC32X4_ADCSETUP);
70 snd_soc_component_write(component, AIC32X4_ADCSETUP, adc_reg |
71 AIC32X4_LADC_EN | AIC32X4_RADC_EN);
72 snd_soc_component_write(component, AIC32X4_ADCSETUP, adc_reg);
73 break;
74 }
75 return 0;
76 };
77
mic_bias_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)78 static int mic_bias_event(struct snd_soc_dapm_widget *w,
79 struct snd_kcontrol *kcontrol, int event)
80 {
81 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
82
83 switch (event) {
84 case SND_SOC_DAPM_POST_PMU:
85 /* Change Mic Bias Registor */
86 snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
87 AIC32x4_MICBIAS_MASK,
88 AIC32X4_MICBIAS_LDOIN |
89 AIC32X4_MICBIAS_2075V);
90 printk(KERN_DEBUG "%s: Mic Bias will be turned ON\n", __func__);
91 break;
92 case SND_SOC_DAPM_PRE_PMD:
93 snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
94 AIC32x4_MICBIAS_MASK, 0);
95 printk(KERN_DEBUG "%s: Mic Bias will be turned OFF\n",
96 __func__);
97 break;
98 }
99
100 return 0;
101 }
102
103
aic32x4_get_mfp1_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)104 static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol,
105 struct snd_ctl_elem_value *ucontrol)
106 {
107 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
108 u8 val;
109
110 val = snd_soc_component_read(component, AIC32X4_DINCTL);
111
112 ucontrol->value.integer.value[0] = (val & 0x01);
113
114 return 0;
115 };
116
aic32x4_set_mfp2_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)117 static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol,
118 struct snd_ctl_elem_value *ucontrol)
119 {
120 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
121 u8 val;
122 u8 gpio_check;
123
124 val = snd_soc_component_read(component, AIC32X4_DOUTCTL);
125 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
126 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
127 printk(KERN_ERR "%s: MFP2 is not configure as a GPIO output\n",
128 __func__);
129 return -EINVAL;
130 }
131
132 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP2_GPIO_OUT_HIGH))
133 return 0;
134
135 if (ucontrol->value.integer.value[0])
136 val |= ucontrol->value.integer.value[0];
137 else
138 val &= ~AIC32X4_MFP2_GPIO_OUT_HIGH;
139
140 snd_soc_component_write(component, AIC32X4_DOUTCTL, val);
141
142 return 0;
143 };
144
aic32x4_get_mfp3_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)145 static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol,
146 struct snd_ctl_elem_value *ucontrol)
147 {
148 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
149 u8 val;
150
151 val = snd_soc_component_read(component, AIC32X4_SCLKCTL);
152
153 ucontrol->value.integer.value[0] = (val & 0x01);
154
155 return 0;
156 };
157
aic32x4_set_mfp4_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)158 static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol,
159 struct snd_ctl_elem_value *ucontrol)
160 {
161 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
162 u8 val;
163 u8 gpio_check;
164
165 val = snd_soc_component_read(component, AIC32X4_MISOCTL);
166 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
167 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
168 printk(KERN_ERR "%s: MFP4 is not configure as a GPIO output\n",
169 __func__);
170 return -EINVAL;
171 }
172
173 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP5_GPIO_OUT_HIGH))
174 return 0;
175
176 if (ucontrol->value.integer.value[0])
177 val |= ucontrol->value.integer.value[0];
178 else
179 val &= ~AIC32X4_MFP5_GPIO_OUT_HIGH;
180
181 snd_soc_component_write(component, AIC32X4_MISOCTL, val);
182
183 return 0;
184 };
185
aic32x4_get_mfp5_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)186 static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol,
187 struct snd_ctl_elem_value *ucontrol)
188 {
189 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
190 u8 val;
191
192 val = snd_soc_component_read(component, AIC32X4_GPIOCTL);
193 ucontrol->value.integer.value[0] = ((val & 0x2) >> 1);
194
195 return 0;
196 };
197
aic32x4_set_mfp5_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)198 static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol,
199 struct snd_ctl_elem_value *ucontrol)
200 {
201 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
202 u8 val;
203 u8 gpio_check;
204
205 val = snd_soc_component_read(component, AIC32X4_GPIOCTL);
206 gpio_check = (val & AIC32X4_MFP5_GPIO_OUTPUT);
207 if (gpio_check != AIC32X4_MFP5_GPIO_OUTPUT) {
208 printk(KERN_ERR "%s: MFP5 is not configure as a GPIO output\n",
209 __func__);
210 return -EINVAL;
211 }
212
213 if (ucontrol->value.integer.value[0] == (val & 0x1))
214 return 0;
215
216 if (ucontrol->value.integer.value[0])
217 val |= ucontrol->value.integer.value[0];
218 else
219 val &= 0xfe;
220
221 snd_soc_component_write(component, AIC32X4_GPIOCTL, val);
222
223 return 0;
224 };
225
226 static const struct snd_kcontrol_new aic32x4_mfp1[] = {
227 SOC_SINGLE_BOOL_EXT("MFP1 GPIO", 0, aic32x4_get_mfp1_gpio, NULL),
228 };
229
230 static const struct snd_kcontrol_new aic32x4_mfp2[] = {
231 SOC_SINGLE_BOOL_EXT("MFP2 GPIO", 0, NULL, aic32x4_set_mfp2_gpio),
232 };
233
234 static const struct snd_kcontrol_new aic32x4_mfp3[] = {
235 SOC_SINGLE_BOOL_EXT("MFP3 GPIO", 0, aic32x4_get_mfp3_gpio, NULL),
236 };
237
238 static const struct snd_kcontrol_new aic32x4_mfp4[] = {
239 SOC_SINGLE_BOOL_EXT("MFP4 GPIO", 0, NULL, aic32x4_set_mfp4_gpio),
240 };
241
242 static const struct snd_kcontrol_new aic32x4_mfp5[] = {
243 SOC_SINGLE_BOOL_EXT("MFP5 GPIO", 0, aic32x4_get_mfp5_gpio,
244 aic32x4_set_mfp5_gpio),
245 };
246
247 /* 0dB min, 0.5dB steps */
248 static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0);
249 /* -63.5dB min, 0.5dB steps */
250 static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0);
251 /* -6dB min, 1dB steps */
252 static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0);
253 /* -12dB min, 0.5dB steps */
254 static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0);
255 /* -6dB min, 1dB steps */
256 static DECLARE_TLV_DB_SCALE(tlv_tas_driver_gain, -5850, 50, 0);
257 static DECLARE_TLV_DB_SCALE(tlv_amp_vol, 0, 600, 1);
258
259 static const char * const lo_cm_text[] = {
260 "Full Chip", "1.65V",
261 };
262
263 static SOC_ENUM_SINGLE_DECL(lo_cm_enum, AIC32X4_CMMODE, 3, lo_cm_text);
264
265 static const char * const ptm_text[] = {
266 "P3", "P2", "P1",
267 };
268
269 static SOC_ENUM_SINGLE_DECL(l_ptm_enum, AIC32X4_LPLAYBACK, 2, ptm_text);
270 static SOC_ENUM_SINGLE_DECL(r_ptm_enum, AIC32X4_RPLAYBACK, 2, ptm_text);
271
272 static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
273 SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
274 AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm),
275 SOC_ENUM("DAC Left Playback PowerTune Switch", l_ptm_enum),
276 SOC_ENUM("DAC Right Playback PowerTune Switch", r_ptm_enum),
277 SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
278 AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0,
279 tlv_driver_gain),
280 SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN,
281 AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0,
282 tlv_driver_gain),
283 SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN,
284 AIC32X4_HPRGAIN, 6, 0x01, 1),
285 SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN,
286 AIC32X4_LORGAIN, 6, 0x01, 1),
287 SOC_ENUM("LO Playback Common Mode Switch", lo_cm_enum),
288 SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL,
289 AIC32X4_RMICPGAVOL, 7, 0x01, 1),
290
291 SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0),
292 SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0),
293
294 SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL,
295 AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol),
296 SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL,
297 AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5),
298
299 SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
300
301 SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0),
302 SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0),
303 SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1,
304 4, 0x07, 0),
305 SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1,
306 0, 0x03, 0),
307 SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2,
308 6, 0x03, 0),
309 SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2,
310 1, 0x1F, 0),
311 SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3,
312 0, 0x7F, 0),
313 SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4,
314 3, 0x1F, 0),
315 SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5,
316 3, 0x1F, 0),
317 SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6,
318 0, 0x1F, 0),
319 SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7,
320 0, 0x0F, 0),
321 };
322
323 static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
324 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
325 SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
326 };
327
328 static const struct snd_kcontrol_new hpr_output_mixer_controls[] = {
329 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0),
330 SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0),
331 };
332
333 static const struct snd_kcontrol_new lol_output_mixer_controls[] = {
334 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0),
335 };
336
337 static const struct snd_kcontrol_new lor_output_mixer_controls[] = {
338 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0),
339 };
340
341 static const char * const resistor_text[] = {
342 "Off", "10 kOhm", "20 kOhm", "40 kOhm",
343 };
344
345 /* Left mixer pins */
346 static SOC_ENUM_SINGLE_DECL(in1l_lpga_p_enum, AIC32X4_LMICPGAPIN, 6, resistor_text);
347 static SOC_ENUM_SINGLE_DECL(in2l_lpga_p_enum, AIC32X4_LMICPGAPIN, 4, resistor_text);
348 static SOC_ENUM_SINGLE_DECL(in3l_lpga_p_enum, AIC32X4_LMICPGAPIN, 2, resistor_text);
349 static SOC_ENUM_SINGLE_DECL(in1r_lpga_p_enum, AIC32X4_LMICPGAPIN, 0, resistor_text);
350
351 static SOC_ENUM_SINGLE_DECL(cml_lpga_n_enum, AIC32X4_LMICPGANIN, 6, resistor_text);
352 static SOC_ENUM_SINGLE_DECL(in2r_lpga_n_enum, AIC32X4_LMICPGANIN, 4, resistor_text);
353 static SOC_ENUM_SINGLE_DECL(in3r_lpga_n_enum, AIC32X4_LMICPGANIN, 2, resistor_text);
354
355 static const struct snd_kcontrol_new in1l_to_lmixer_controls[] = {
356 SOC_DAPM_ENUM("IN1_L L+ Switch", in1l_lpga_p_enum),
357 };
358 static const struct snd_kcontrol_new in2l_to_lmixer_controls[] = {
359 SOC_DAPM_ENUM("IN2_L L+ Switch", in2l_lpga_p_enum),
360 };
361 static const struct snd_kcontrol_new in3l_to_lmixer_controls[] = {
362 SOC_DAPM_ENUM("IN3_L L+ Switch", in3l_lpga_p_enum),
363 };
364 static const struct snd_kcontrol_new in1r_to_lmixer_controls[] = {
365 SOC_DAPM_ENUM("IN1_R L+ Switch", in1r_lpga_p_enum),
366 };
367 static const struct snd_kcontrol_new cml_to_lmixer_controls[] = {
368 SOC_DAPM_ENUM("CM_L L- Switch", cml_lpga_n_enum),
369 };
370 static const struct snd_kcontrol_new in2r_to_lmixer_controls[] = {
371 SOC_DAPM_ENUM("IN2_R L- Switch", in2r_lpga_n_enum),
372 };
373 static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = {
374 SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum),
375 };
376
377 /* Right mixer pins */
378 static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text);
379 static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text);
380 static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text);
381 static SOC_ENUM_SINGLE_DECL(in2l_rpga_p_enum, AIC32X4_RMICPGAPIN, 0, resistor_text);
382 static SOC_ENUM_SINGLE_DECL(cmr_rpga_n_enum, AIC32X4_RMICPGANIN, 6, resistor_text);
383 static SOC_ENUM_SINGLE_DECL(in1l_rpga_n_enum, AIC32X4_RMICPGANIN, 4, resistor_text);
384 static SOC_ENUM_SINGLE_DECL(in3l_rpga_n_enum, AIC32X4_RMICPGANIN, 2, resistor_text);
385
386 static const struct snd_kcontrol_new in1r_to_rmixer_controls[] = {
387 SOC_DAPM_ENUM("IN1_R R+ Switch", in1r_rpga_p_enum),
388 };
389 static const struct snd_kcontrol_new in2r_to_rmixer_controls[] = {
390 SOC_DAPM_ENUM("IN2_R R+ Switch", in2r_rpga_p_enum),
391 };
392 static const struct snd_kcontrol_new in3r_to_rmixer_controls[] = {
393 SOC_DAPM_ENUM("IN3_R R+ Switch", in3r_rpga_p_enum),
394 };
395 static const struct snd_kcontrol_new in2l_to_rmixer_controls[] = {
396 SOC_DAPM_ENUM("IN2_L R+ Switch", in2l_rpga_p_enum),
397 };
398 static const struct snd_kcontrol_new cmr_to_rmixer_controls[] = {
399 SOC_DAPM_ENUM("CM_R R- Switch", cmr_rpga_n_enum),
400 };
401 static const struct snd_kcontrol_new in1l_to_rmixer_controls[] = {
402 SOC_DAPM_ENUM("IN1_L R- Switch", in1l_rpga_n_enum),
403 };
404 static const struct snd_kcontrol_new in3l_to_rmixer_controls[] = {
405 SOC_DAPM_ENUM("IN3_L R- Switch", in3l_rpga_n_enum),
406 };
407
408 static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
409 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0),
410 SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0,
411 &hpl_output_mixer_controls[0],
412 ARRAY_SIZE(hpl_output_mixer_controls)),
413 SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
414
415 SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0,
416 &lol_output_mixer_controls[0],
417 ARRAY_SIZE(lol_output_mixer_controls)),
418 SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0),
419
420 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0),
421 SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0,
422 &hpr_output_mixer_controls[0],
423 ARRAY_SIZE(hpr_output_mixer_controls)),
424 SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0),
425 SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0,
426 &lor_output_mixer_controls[0],
427 ARRAY_SIZE(lor_output_mixer_controls)),
428 SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0),
429
430 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0),
431 SND_SOC_DAPM_MUX("IN1_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
432 in1r_to_rmixer_controls),
433 SND_SOC_DAPM_MUX("IN2_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
434 in2r_to_rmixer_controls),
435 SND_SOC_DAPM_MUX("IN3_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
436 in3r_to_rmixer_controls),
437 SND_SOC_DAPM_MUX("IN2_L to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
438 in2l_to_rmixer_controls),
439 SND_SOC_DAPM_MUX("CM_R to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
440 cmr_to_rmixer_controls),
441 SND_SOC_DAPM_MUX("IN1_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
442 in1l_to_rmixer_controls),
443 SND_SOC_DAPM_MUX("IN3_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
444 in3l_to_rmixer_controls),
445
446 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0),
447 SND_SOC_DAPM_MUX("IN1_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
448 in1l_to_lmixer_controls),
449 SND_SOC_DAPM_MUX("IN2_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
450 in2l_to_lmixer_controls),
451 SND_SOC_DAPM_MUX("IN3_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
452 in3l_to_lmixer_controls),
453 SND_SOC_DAPM_MUX("IN1_R to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
454 in1r_to_lmixer_controls),
455 SND_SOC_DAPM_MUX("CM_L to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
456 cml_to_lmixer_controls),
457 SND_SOC_DAPM_MUX("IN2_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
458 in2r_to_lmixer_controls),
459 SND_SOC_DAPM_MUX("IN3_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
460 in3r_to_lmixer_controls),
461
462 SND_SOC_DAPM_SUPPLY("Mic Bias", AIC32X4_MICBIAS, 6, 0, mic_bias_event,
463 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
464
465 SND_SOC_DAPM_POST("ADC Reset", aic32x4_reset_adc),
466
467 SND_SOC_DAPM_OUTPUT("HPL"),
468 SND_SOC_DAPM_OUTPUT("HPR"),
469 SND_SOC_DAPM_OUTPUT("LOL"),
470 SND_SOC_DAPM_OUTPUT("LOR"),
471 SND_SOC_DAPM_INPUT("IN1_L"),
472 SND_SOC_DAPM_INPUT("IN1_R"),
473 SND_SOC_DAPM_INPUT("IN2_L"),
474 SND_SOC_DAPM_INPUT("IN2_R"),
475 SND_SOC_DAPM_INPUT("IN3_L"),
476 SND_SOC_DAPM_INPUT("IN3_R"),
477 SND_SOC_DAPM_INPUT("CM_L"),
478 SND_SOC_DAPM_INPUT("CM_R"),
479 };
480
481 static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
482 /* Left Output */
483 {"HPL Output Mixer", "L_DAC Switch", "Left DAC"},
484 {"HPL Output Mixer", "IN1_L Switch", "IN1_L"},
485
486 {"HPL Power", NULL, "HPL Output Mixer"},
487 {"HPL", NULL, "HPL Power"},
488
489 {"LOL Output Mixer", "L_DAC Switch", "Left DAC"},
490
491 {"LOL Power", NULL, "LOL Output Mixer"},
492 {"LOL", NULL, "LOL Power"},
493
494 /* Right Output */
495 {"HPR Output Mixer", "R_DAC Switch", "Right DAC"},
496 {"HPR Output Mixer", "IN1_R Switch", "IN1_R"},
497
498 {"HPR Power", NULL, "HPR Output Mixer"},
499 {"HPR", NULL, "HPR Power"},
500
501 {"LOR Output Mixer", "R_DAC Switch", "Right DAC"},
502
503 {"LOR Power", NULL, "LOR Output Mixer"},
504 {"LOR", NULL, "LOR Power"},
505
506 /* Right Input */
507 {"Right ADC", NULL, "IN1_R to Right Mixer Positive Resistor"},
508 {"IN1_R to Right Mixer Positive Resistor", "10 kOhm", "IN1_R"},
509 {"IN1_R to Right Mixer Positive Resistor", "20 kOhm", "IN1_R"},
510 {"IN1_R to Right Mixer Positive Resistor", "40 kOhm", "IN1_R"},
511
512 {"Right ADC", NULL, "IN2_R to Right Mixer Positive Resistor"},
513 {"IN2_R to Right Mixer Positive Resistor", "10 kOhm", "IN2_R"},
514 {"IN2_R to Right Mixer Positive Resistor", "20 kOhm", "IN2_R"},
515 {"IN2_R to Right Mixer Positive Resistor", "40 kOhm", "IN2_R"},
516
517 {"Right ADC", NULL, "IN3_R to Right Mixer Positive Resistor"},
518 {"IN3_R to Right Mixer Positive Resistor", "10 kOhm", "IN3_R"},
519 {"IN3_R to Right Mixer Positive Resistor", "20 kOhm", "IN3_R"},
520 {"IN3_R to Right Mixer Positive Resistor", "40 kOhm", "IN3_R"},
521
522 {"Right ADC", NULL, "IN2_L to Right Mixer Positive Resistor"},
523 {"IN2_L to Right Mixer Positive Resistor", "10 kOhm", "IN2_L"},
524 {"IN2_L to Right Mixer Positive Resistor", "20 kOhm", "IN2_L"},
525 {"IN2_L to Right Mixer Positive Resistor", "40 kOhm", "IN2_L"},
526
527 {"Right ADC", NULL, "CM_R to Right Mixer Negative Resistor"},
528 {"CM_R to Right Mixer Negative Resistor", "10 kOhm", "CM_R"},
529 {"CM_R to Right Mixer Negative Resistor", "20 kOhm", "CM_R"},
530 {"CM_R to Right Mixer Negative Resistor", "40 kOhm", "CM_R"},
531
532 {"Right ADC", NULL, "IN1_L to Right Mixer Negative Resistor"},
533 {"IN1_L to Right Mixer Negative Resistor", "10 kOhm", "IN1_L"},
534 {"IN1_L to Right Mixer Negative Resistor", "20 kOhm", "IN1_L"},
535 {"IN1_L to Right Mixer Negative Resistor", "40 kOhm", "IN1_L"},
536
537 {"Right ADC", NULL, "IN3_L to Right Mixer Negative Resistor"},
538 {"IN3_L to Right Mixer Negative Resistor", "10 kOhm", "IN3_L"},
539 {"IN3_L to Right Mixer Negative Resistor", "20 kOhm", "IN3_L"},
540 {"IN3_L to Right Mixer Negative Resistor", "40 kOhm", "IN3_L"},
541
542 /* Left Input */
543 {"Left ADC", NULL, "IN1_L to Left Mixer Positive Resistor"},
544 {"IN1_L to Left Mixer Positive Resistor", "10 kOhm", "IN1_L"},
545 {"IN1_L to Left Mixer Positive Resistor", "20 kOhm", "IN1_L"},
546 {"IN1_L to Left Mixer Positive Resistor", "40 kOhm", "IN1_L"},
547
548 {"Left ADC", NULL, "IN2_L to Left Mixer Positive Resistor"},
549 {"IN2_L to Left Mixer Positive Resistor", "10 kOhm", "IN2_L"},
550 {"IN2_L to Left Mixer Positive Resistor", "20 kOhm", "IN2_L"},
551 {"IN2_L to Left Mixer Positive Resistor", "40 kOhm", "IN2_L"},
552
553 {"Left ADC", NULL, "IN3_L to Left Mixer Positive Resistor"},
554 {"IN3_L to Left Mixer Positive Resistor", "10 kOhm", "IN3_L"},
555 {"IN3_L to Left Mixer Positive Resistor", "20 kOhm", "IN3_L"},
556 {"IN3_L to Left Mixer Positive Resistor", "40 kOhm", "IN3_L"},
557
558 {"Left ADC", NULL, "IN1_R to Left Mixer Positive Resistor"},
559 {"IN1_R to Left Mixer Positive Resistor", "10 kOhm", "IN1_R"},
560 {"IN1_R to Left Mixer Positive Resistor", "20 kOhm", "IN1_R"},
561 {"IN1_R to Left Mixer Positive Resistor", "40 kOhm", "IN1_R"},
562
563 {"Left ADC", NULL, "CM_L to Left Mixer Negative Resistor"},
564 {"CM_L to Left Mixer Negative Resistor", "10 kOhm", "CM_L"},
565 {"CM_L to Left Mixer Negative Resistor", "20 kOhm", "CM_L"},
566 {"CM_L to Left Mixer Negative Resistor", "40 kOhm", "CM_L"},
567
568 {"Left ADC", NULL, "IN2_R to Left Mixer Negative Resistor"},
569 {"IN2_R to Left Mixer Negative Resistor", "10 kOhm", "IN2_R"},
570 {"IN2_R to Left Mixer Negative Resistor", "20 kOhm", "IN2_R"},
571 {"IN2_R to Left Mixer Negative Resistor", "40 kOhm", "IN2_R"},
572
573 {"Left ADC", NULL, "IN3_R to Left Mixer Negative Resistor"},
574 {"IN3_R to Left Mixer Negative Resistor", "10 kOhm", "IN3_R"},
575 {"IN3_R to Left Mixer Negative Resistor", "20 kOhm", "IN3_R"},
576 {"IN3_R to Left Mixer Negative Resistor", "40 kOhm", "IN3_R"},
577 };
578
579 static const struct regmap_range_cfg aic32x4_regmap_pages[] = {
580 {
581 .selector_reg = 0,
582 .selector_mask = 0xff,
583 .window_start = 0,
584 .window_len = 128,
585 .range_min = 0,
586 .range_max = AIC32X4_REFPOWERUP,
587 },
588 };
589
590 const struct regmap_config aic32x4_regmap_config = {
591 .max_register = AIC32X4_REFPOWERUP,
592 .ranges = aic32x4_regmap_pages,
593 .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages),
594 };
595 EXPORT_SYMBOL(aic32x4_regmap_config);
596
aic32x4_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)597 static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
598 int clk_id, unsigned int freq, int dir)
599 {
600 struct snd_soc_component *component = codec_dai->component;
601 struct clk *mclk;
602 struct clk *pll;
603
604 pll = devm_clk_get(component->dev, "pll");
605 if (IS_ERR(pll))
606 return PTR_ERR(pll);
607
608 mclk = clk_get_parent(pll);
609
610 return clk_set_rate(mclk, freq);
611 }
612
aic32x4_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)613 static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
614 {
615 struct snd_soc_component *component = codec_dai->component;
616 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
617 u8 iface_reg_1 = 0;
618 u8 iface_reg_2 = 0;
619 u8 iface_reg_3 = 0;
620
621 /* set master/slave audio interface */
622 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
623 case SND_SOC_DAIFMT_CBM_CFM:
624 iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER;
625 break;
626 case SND_SOC_DAIFMT_CBS_CFS:
627 break;
628 default:
629 printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n");
630 return -EINVAL;
631 }
632
633 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
634 case SND_SOC_DAIFMT_I2S:
635 break;
636 case SND_SOC_DAIFMT_DSP_A:
637 iface_reg_1 |= (AIC32X4_DSP_MODE <<
638 AIC32X4_IFACE1_DATATYPE_SHIFT);
639 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
640 iface_reg_2 = 0x01; /* add offset 1 */
641 break;
642 case SND_SOC_DAIFMT_DSP_B:
643 iface_reg_1 |= (AIC32X4_DSP_MODE <<
644 AIC32X4_IFACE1_DATATYPE_SHIFT);
645 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
646 break;
647 case SND_SOC_DAIFMT_RIGHT_J:
648 iface_reg_1 |= (AIC32X4_RIGHT_JUSTIFIED_MODE <<
649 AIC32X4_IFACE1_DATATYPE_SHIFT);
650 break;
651 case SND_SOC_DAIFMT_LEFT_J:
652 iface_reg_1 |= (AIC32X4_LEFT_JUSTIFIED_MODE <<
653 AIC32X4_IFACE1_DATATYPE_SHIFT);
654 break;
655 default:
656 printk(KERN_ERR "aic32x4: invalid DAI interface format\n");
657 return -EINVAL;
658 }
659
660 aic32x4->fmt = fmt;
661
662 snd_soc_component_update_bits(component, AIC32X4_IFACE1,
663 AIC32X4_IFACE1_DATATYPE_MASK |
664 AIC32X4_IFACE1_MASTER_MASK, iface_reg_1);
665 snd_soc_component_update_bits(component, AIC32X4_IFACE2,
666 AIC32X4_DATA_OFFSET_MASK, iface_reg_2);
667 snd_soc_component_update_bits(component, AIC32X4_IFACE3,
668 AIC32X4_BCLKINV_MASK, iface_reg_3);
669
670 return 0;
671 }
672
aic32x4_set_aosr(struct snd_soc_component * component,u8 aosr)673 static int aic32x4_set_aosr(struct snd_soc_component *component, u8 aosr)
674 {
675 return snd_soc_component_write(component, AIC32X4_AOSR, aosr);
676 }
677
aic32x4_set_dosr(struct snd_soc_component * component,u16 dosr)678 static int aic32x4_set_dosr(struct snd_soc_component *component, u16 dosr)
679 {
680 snd_soc_component_write(component, AIC32X4_DOSRMSB, dosr >> 8);
681 snd_soc_component_write(component, AIC32X4_DOSRLSB,
682 (dosr & 0xff));
683
684 return 0;
685 }
686
aic32x4_set_processing_blocks(struct snd_soc_component * component,u8 r_block,u8 p_block)687 static int aic32x4_set_processing_blocks(struct snd_soc_component *component,
688 u8 r_block, u8 p_block)
689 {
690 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
691
692 if (aic32x4->type == AIC32X4_TYPE_TAS2505) {
693 if (r_block || p_block > 3)
694 return -EINVAL;
695
696 snd_soc_component_write(component, AIC32X4_DACSPB, p_block);
697 } else { /* AIC32x4 */
698 if (r_block > 18 || p_block > 25)
699 return -EINVAL;
700
701 snd_soc_component_write(component, AIC32X4_ADCSPB, r_block);
702 snd_soc_component_write(component, AIC32X4_DACSPB, p_block);
703 }
704
705 return 0;
706 }
707
aic32x4_setup_clocks(struct snd_soc_component * component,unsigned int sample_rate,unsigned int channels,unsigned int bit_depth)708 static int aic32x4_setup_clocks(struct snd_soc_component *component,
709 unsigned int sample_rate, unsigned int channels,
710 unsigned int bit_depth)
711 {
712 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
713 u8 aosr;
714 u16 dosr;
715 u8 adc_resource_class, dac_resource_class;
716 u8 madc, nadc, mdac, ndac, max_nadc, min_mdac, max_ndac;
717 u8 dosr_increment;
718 u16 max_dosr, min_dosr;
719 unsigned long adc_clock_rate, dac_clock_rate;
720 int ret;
721
722 static struct clk_bulk_data clocks[] = {
723 { .id = "pll" },
724 { .id = "nadc" },
725 { .id = "madc" },
726 { .id = "ndac" },
727 { .id = "mdac" },
728 { .id = "bdiv" },
729 };
730 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
731 if (ret)
732 return ret;
733
734 if (sample_rate <= 48000) {
735 aosr = 128;
736 adc_resource_class = 6;
737 dac_resource_class = 8;
738 dosr_increment = 8;
739 if (aic32x4->type == AIC32X4_TYPE_TAS2505)
740 aic32x4_set_processing_blocks(component, 0, 1);
741 else
742 aic32x4_set_processing_blocks(component, 1, 1);
743 } else if (sample_rate <= 96000) {
744 aosr = 64;
745 adc_resource_class = 6;
746 dac_resource_class = 8;
747 dosr_increment = 4;
748 if (aic32x4->type == AIC32X4_TYPE_TAS2505)
749 aic32x4_set_processing_blocks(component, 0, 1);
750 else
751 aic32x4_set_processing_blocks(component, 1, 9);
752 } else if (sample_rate == 192000) {
753 aosr = 32;
754 adc_resource_class = 3;
755 dac_resource_class = 4;
756 dosr_increment = 2;
757 if (aic32x4->type == AIC32X4_TYPE_TAS2505)
758 aic32x4_set_processing_blocks(component, 0, 1);
759 else
760 aic32x4_set_processing_blocks(component, 13, 19);
761 } else {
762 dev_err(component->dev, "Sampling rate not supported\n");
763 return -EINVAL;
764 }
765
766 /* PCM over I2S is always 2-channel */
767 if ((aic32x4->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S)
768 channels = 2;
769
770 madc = DIV_ROUND_UP((32 * adc_resource_class), aosr);
771 max_dosr = (AIC32X4_MAX_DOSR_FREQ / sample_rate / dosr_increment) *
772 dosr_increment;
773 min_dosr = (AIC32X4_MIN_DOSR_FREQ / sample_rate / dosr_increment) *
774 dosr_increment;
775 max_nadc = AIC32X4_MAX_CODEC_CLKIN_FREQ / (madc * aosr * sample_rate);
776
777 for (nadc = max_nadc; nadc > 0; --nadc) {
778 adc_clock_rate = nadc * madc * aosr * sample_rate;
779 for (dosr = max_dosr; dosr >= min_dosr;
780 dosr -= dosr_increment) {
781 min_mdac = DIV_ROUND_UP((32 * dac_resource_class), dosr);
782 max_ndac = AIC32X4_MAX_CODEC_CLKIN_FREQ /
783 (min_mdac * dosr * sample_rate);
784 for (mdac = min_mdac; mdac <= 128; ++mdac) {
785 for (ndac = max_ndac; ndac > 0; --ndac) {
786 dac_clock_rate = ndac * mdac * dosr *
787 sample_rate;
788 if (dac_clock_rate == adc_clock_rate) {
789 if (clk_round_rate(clocks[0].clk, dac_clock_rate) == 0)
790 continue;
791
792 clk_set_rate(clocks[0].clk,
793 dac_clock_rate);
794
795 clk_set_rate(clocks[1].clk,
796 sample_rate * aosr *
797 madc);
798 clk_set_rate(clocks[2].clk,
799 sample_rate * aosr);
800 aic32x4_set_aosr(component,
801 aosr);
802
803 clk_set_rate(clocks[3].clk,
804 sample_rate * dosr *
805 mdac);
806 clk_set_rate(clocks[4].clk,
807 sample_rate * dosr);
808 aic32x4_set_dosr(component,
809 dosr);
810
811 clk_set_rate(clocks[5].clk,
812 sample_rate * channels *
813 bit_depth);
814
815 return 0;
816 }
817 }
818 }
819 }
820 }
821
822 dev_err(component->dev,
823 "Could not set clocks to support sample rate.\n");
824 return -EINVAL;
825 }
826
aic32x4_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)827 static int aic32x4_hw_params(struct snd_pcm_substream *substream,
828 struct snd_pcm_hw_params *params,
829 struct snd_soc_dai *dai)
830 {
831 struct snd_soc_component *component = dai->component;
832 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
833 u8 iface1_reg = 0;
834 u8 dacsetup_reg = 0;
835
836 aic32x4_setup_clocks(component, params_rate(params),
837 params_channels(params),
838 params_physical_width(params));
839
840 switch (params_physical_width(params)) {
841 case 16:
842 iface1_reg |= (AIC32X4_WORD_LEN_16BITS <<
843 AIC32X4_IFACE1_DATALEN_SHIFT);
844 break;
845 case 20:
846 iface1_reg |= (AIC32X4_WORD_LEN_20BITS <<
847 AIC32X4_IFACE1_DATALEN_SHIFT);
848 break;
849 case 24:
850 iface1_reg |= (AIC32X4_WORD_LEN_24BITS <<
851 AIC32X4_IFACE1_DATALEN_SHIFT);
852 break;
853 case 32:
854 iface1_reg |= (AIC32X4_WORD_LEN_32BITS <<
855 AIC32X4_IFACE1_DATALEN_SHIFT);
856 break;
857 }
858 snd_soc_component_update_bits(component, AIC32X4_IFACE1,
859 AIC32X4_IFACE1_DATALEN_MASK, iface1_reg);
860
861 if (params_channels(params) == 1) {
862 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN;
863 } else {
864 if (aic32x4->swapdacs)
865 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN;
866 else
867 dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
868 }
869 snd_soc_component_update_bits(component, AIC32X4_DACSETUP,
870 AIC32X4_DAC_CHAN_MASK, dacsetup_reg);
871
872 return 0;
873 }
874
aic32x4_mute(struct snd_soc_dai * dai,int mute,int direction)875 static int aic32x4_mute(struct snd_soc_dai *dai, int mute, int direction)
876 {
877 struct snd_soc_component *component = dai->component;
878
879 snd_soc_component_update_bits(component, AIC32X4_DACMUTE,
880 AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0);
881
882 return 0;
883 }
884
aic32x4_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)885 static int aic32x4_set_bias_level(struct snd_soc_component *component,
886 enum snd_soc_bias_level level)
887 {
888 int ret;
889
890 static struct clk_bulk_data clocks[] = {
891 { .id = "madc" },
892 { .id = "mdac" },
893 { .id = "bdiv" },
894 };
895
896 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
897 if (ret)
898 return ret;
899
900 switch (level) {
901 case SND_SOC_BIAS_ON:
902 ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks);
903 if (ret) {
904 dev_err(component->dev, "Failed to enable clocks\n");
905 return ret;
906 }
907 break;
908 case SND_SOC_BIAS_PREPARE:
909 break;
910 case SND_SOC_BIAS_STANDBY:
911 /* Initial cold start */
912 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
913 break;
914
915 clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks);
916 break;
917 case SND_SOC_BIAS_OFF:
918 break;
919 }
920 return 0;
921 }
922
923 #define AIC32X4_RATES SNDRV_PCM_RATE_8000_192000
924 #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
925 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_3LE \
926 | SNDRV_PCM_FMTBIT_S32_LE)
927
928 static const struct snd_soc_dai_ops aic32x4_ops = {
929 .hw_params = aic32x4_hw_params,
930 .mute_stream = aic32x4_mute,
931 .set_fmt = aic32x4_set_dai_fmt,
932 .set_sysclk = aic32x4_set_dai_sysclk,
933 .no_capture_mute = 1,
934 };
935
936 static struct snd_soc_dai_driver aic32x4_dai = {
937 .name = "tlv320aic32x4-hifi",
938 .playback = {
939 .stream_name = "Playback",
940 .channels_min = 1,
941 .channels_max = 2,
942 .rates = AIC32X4_RATES,
943 .formats = AIC32X4_FORMATS,},
944 .capture = {
945 .stream_name = "Capture",
946 .channels_min = 1,
947 .channels_max = 8,
948 .rates = AIC32X4_RATES,
949 .formats = AIC32X4_FORMATS,},
950 .ops = &aic32x4_ops,
951 .symmetric_rate = 1,
952 };
953
aic32x4_setup_gpios(struct snd_soc_component * component)954 static void aic32x4_setup_gpios(struct snd_soc_component *component)
955 {
956 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
957
958 /* setup GPIO functions */
959 /* MFP1 */
960 if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) {
961 snd_soc_component_write(component, AIC32X4_DINCTL,
962 aic32x4->setup->gpio_func[0]);
963 snd_soc_add_component_controls(component, aic32x4_mfp1,
964 ARRAY_SIZE(aic32x4_mfp1));
965 }
966
967 /* MFP2 */
968 if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) {
969 snd_soc_component_write(component, AIC32X4_DOUTCTL,
970 aic32x4->setup->gpio_func[1]);
971 snd_soc_add_component_controls(component, aic32x4_mfp2,
972 ARRAY_SIZE(aic32x4_mfp2));
973 }
974
975 /* MFP3 */
976 if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) {
977 snd_soc_component_write(component, AIC32X4_SCLKCTL,
978 aic32x4->setup->gpio_func[2]);
979 snd_soc_add_component_controls(component, aic32x4_mfp3,
980 ARRAY_SIZE(aic32x4_mfp3));
981 }
982
983 /* MFP4 */
984 if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) {
985 snd_soc_component_write(component, AIC32X4_MISOCTL,
986 aic32x4->setup->gpio_func[3]);
987 snd_soc_add_component_controls(component, aic32x4_mfp4,
988 ARRAY_SIZE(aic32x4_mfp4));
989 }
990
991 /* MFP5 */
992 if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) {
993 snd_soc_component_write(component, AIC32X4_GPIOCTL,
994 aic32x4->setup->gpio_func[4]);
995 snd_soc_add_component_controls(component, aic32x4_mfp5,
996 ARRAY_SIZE(aic32x4_mfp5));
997 }
998 }
999
aic32x4_component_probe(struct snd_soc_component * component)1000 static int aic32x4_component_probe(struct snd_soc_component *component)
1001 {
1002 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
1003 u32 tmp_reg;
1004 int ret;
1005
1006 static struct clk_bulk_data clocks[] = {
1007 { .id = "codec_clkin" },
1008 { .id = "pll" },
1009 { .id = "bdiv" },
1010 { .id = "mdac" },
1011 };
1012
1013 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
1014 if (ret)
1015 return ret;
1016
1017 if (aic32x4->setup)
1018 aic32x4_setup_gpios(component);
1019
1020 clk_set_parent(clocks[0].clk, clocks[1].clk);
1021 clk_set_parent(clocks[2].clk, clocks[3].clk);
1022
1023 /* Power platform configuration */
1024 if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
1025 snd_soc_component_write(component, AIC32X4_MICBIAS,
1026 AIC32X4_MICBIAS_LDOIN | AIC32X4_MICBIAS_2075V);
1027 }
1028 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
1029 snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
1030
1031 tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
1032 AIC32X4_LDOCTLEN : 0;
1033 snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg);
1034
1035 tmp_reg = snd_soc_component_read(component, AIC32X4_CMMODE);
1036 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36)
1037 tmp_reg |= AIC32X4_LDOIN_18_36;
1038 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED)
1039 tmp_reg |= AIC32X4_LDOIN2HP;
1040 snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg);
1041
1042 /* Mic PGA routing */
1043 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K)
1044 snd_soc_component_write(component, AIC32X4_LMICPGANIN,
1045 AIC32X4_LMICPGANIN_IN2R_10K);
1046 else
1047 snd_soc_component_write(component, AIC32X4_LMICPGANIN,
1048 AIC32X4_LMICPGANIN_CM1L_10K);
1049 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K)
1050 snd_soc_component_write(component, AIC32X4_RMICPGANIN,
1051 AIC32X4_RMICPGANIN_IN1L_10K);
1052 else
1053 snd_soc_component_write(component, AIC32X4_RMICPGANIN,
1054 AIC32X4_RMICPGANIN_CM1R_10K);
1055
1056 /*
1057 * Workaround: for an unknown reason, the ADC needs to be powered up
1058 * and down for the first capture to work properly. It seems related to
1059 * a HW BUG or some kind of behavior not documented in the datasheet.
1060 */
1061 tmp_reg = snd_soc_component_read(component, AIC32X4_ADCSETUP);
1062 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg |
1063 AIC32X4_LADC_EN | AIC32X4_RADC_EN);
1064 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg);
1065
1066 /*
1067 * Enable the fast charging feature and ensure the needed 40ms ellapsed
1068 * before using the analog circuits.
1069 */
1070 snd_soc_component_write(component, AIC32X4_REFPOWERUP,
1071 AIC32X4_REFPOWERUP_40MS);
1072 msleep(40);
1073
1074 return 0;
1075 }
1076
1077 static const struct snd_soc_component_driver soc_component_dev_aic32x4 = {
1078 .probe = aic32x4_component_probe,
1079 .set_bias_level = aic32x4_set_bias_level,
1080 .controls = aic32x4_snd_controls,
1081 .num_controls = ARRAY_SIZE(aic32x4_snd_controls),
1082 .dapm_widgets = aic32x4_dapm_widgets,
1083 .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets),
1084 .dapm_routes = aic32x4_dapm_routes,
1085 .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes),
1086 .suspend_bias_off = 1,
1087 .idle_bias_on = 1,
1088 .use_pmdown_time = 1,
1089 .endianness = 1,
1090 .non_legacy_dai_naming = 1,
1091 };
1092
1093 static const struct snd_kcontrol_new aic32x4_tas2505_snd_controls[] = {
1094 SOC_SINGLE_S8_TLV("PCM Playback Volume",
1095 AIC32X4_LDACVOL, -0x7f, 0x30, tlv_pcm),
1096 SOC_ENUM("DAC Playback PowerTune Switch", l_ptm_enum),
1097
1098 SOC_SINGLE_TLV("HP Driver Gain Volume",
1099 AIC32X4_HPLGAIN, 0, 0x74, 1, tlv_tas_driver_gain),
1100 SOC_SINGLE("HP DAC Playback Switch", AIC32X4_HPLGAIN, 6, 1, 1),
1101
1102 SOC_SINGLE_TLV("Speaker Driver Playback Volume",
1103 TAS2505_SPKVOL1, 0, 0x74, 1, tlv_tas_driver_gain),
1104 SOC_SINGLE_TLV("Speaker Amplifier Playback Volume",
1105 TAS2505_SPKVOL2, 4, 5, 0, tlv_amp_vol),
1106
1107 SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
1108 };
1109
1110 static const struct snd_kcontrol_new hp_output_mixer_controls[] = {
1111 SOC_DAPM_SINGLE("DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
1112 };
1113
1114 static const struct snd_soc_dapm_widget aic32x4_tas2505_dapm_widgets[] = {
1115 SND_SOC_DAPM_DAC("DAC", "Playback", AIC32X4_DACSETUP, 7, 0),
1116 SND_SOC_DAPM_MIXER("HP Output Mixer", SND_SOC_NOPM, 0, 0,
1117 &hp_output_mixer_controls[0],
1118 ARRAY_SIZE(hp_output_mixer_controls)),
1119 SND_SOC_DAPM_PGA("HP Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
1120
1121 SND_SOC_DAPM_PGA("Speaker Driver", TAS2505_SPK, 1, 0, NULL, 0),
1122
1123 SND_SOC_DAPM_OUTPUT("HP"),
1124 SND_SOC_DAPM_OUTPUT("Speaker"),
1125 };
1126
1127 static const struct snd_soc_dapm_route aic32x4_tas2505_dapm_routes[] = {
1128 /* Left Output */
1129 {"HP Output Mixer", "DAC Switch", "DAC"},
1130
1131 {"HP Power", NULL, "HP Output Mixer"},
1132 {"HP", NULL, "HP Power"},
1133
1134 {"Speaker Driver", NULL, "DAC"},
1135 {"Speaker", NULL, "Speaker Driver"},
1136 };
1137
1138 static struct snd_soc_dai_driver aic32x4_tas2505_dai = {
1139 .name = "tas2505-hifi",
1140 .playback = {
1141 .stream_name = "Playback",
1142 .channels_min = 1,
1143 .channels_max = 2,
1144 .rates = SNDRV_PCM_RATE_8000_96000,
1145 .formats = AIC32X4_FORMATS,},
1146 .ops = &aic32x4_ops,
1147 .symmetric_rate = 1,
1148 };
1149
aic32x4_tas2505_component_probe(struct snd_soc_component * component)1150 static int aic32x4_tas2505_component_probe(struct snd_soc_component *component)
1151 {
1152 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
1153 u32 tmp_reg;
1154 int ret;
1155
1156 static struct clk_bulk_data clocks[] = {
1157 { .id = "codec_clkin" },
1158 { .id = "pll" },
1159 { .id = "bdiv" },
1160 { .id = "mdac" },
1161 };
1162
1163 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
1164 if (ret)
1165 return ret;
1166
1167 if (aic32x4->setup)
1168 aic32x4_setup_gpios(component);
1169
1170 clk_set_parent(clocks[0].clk, clocks[1].clk);
1171 clk_set_parent(clocks[2].clk, clocks[3].clk);
1172
1173 /* Power platform configuration */
1174 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
1175 snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
1176
1177 tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
1178 AIC32X4_LDOCTLEN : 0;
1179 snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg);
1180
1181 tmp_reg = snd_soc_component_read(component, AIC32X4_CMMODE);
1182 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36)
1183 tmp_reg |= AIC32X4_LDOIN_18_36;
1184 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED)
1185 tmp_reg |= AIC32X4_LDOIN2HP;
1186 snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg);
1187
1188 /*
1189 * Enable the fast charging feature and ensure the needed 40ms ellapsed
1190 * before using the analog circuits.
1191 */
1192 snd_soc_component_write(component, TAS2505_REFPOWERUP,
1193 AIC32X4_REFPOWERUP_40MS);
1194 msleep(40);
1195
1196 return 0;
1197 }
1198
1199 static const struct snd_soc_component_driver soc_component_dev_aic32x4_tas2505 = {
1200 .probe = aic32x4_tas2505_component_probe,
1201 .set_bias_level = aic32x4_set_bias_level,
1202 .controls = aic32x4_tas2505_snd_controls,
1203 .num_controls = ARRAY_SIZE(aic32x4_tas2505_snd_controls),
1204 .dapm_widgets = aic32x4_tas2505_dapm_widgets,
1205 .num_dapm_widgets = ARRAY_SIZE(aic32x4_tas2505_dapm_widgets),
1206 .dapm_routes = aic32x4_tas2505_dapm_routes,
1207 .num_dapm_routes = ARRAY_SIZE(aic32x4_tas2505_dapm_routes),
1208 .suspend_bias_off = 1,
1209 .idle_bias_on = 1,
1210 .use_pmdown_time = 1,
1211 .endianness = 1,
1212 .non_legacy_dai_naming = 1,
1213 };
1214
aic32x4_parse_dt(struct aic32x4_priv * aic32x4,struct device_node * np)1215 static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4,
1216 struct device_node *np)
1217 {
1218 struct aic32x4_setup_data *aic32x4_setup;
1219 int ret;
1220
1221 aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup),
1222 GFP_KERNEL);
1223 if (!aic32x4_setup)
1224 return -ENOMEM;
1225
1226 ret = of_property_match_string(np, "clock-names", "mclk");
1227 if (ret < 0)
1228 return -EINVAL;
1229 aic32x4->mclk_name = of_clk_get_parent_name(np, ret);
1230
1231 aic32x4->swapdacs = false;
1232 aic32x4->micpga_routing = 0;
1233 aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0);
1234
1235 if (of_property_read_u32_array(np, "aic32x4-gpio-func",
1236 aic32x4_setup->gpio_func, 5) >= 0)
1237 aic32x4->setup = aic32x4_setup;
1238 return 0;
1239 }
1240
aic32x4_disable_regulators(struct aic32x4_priv * aic32x4)1241 static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4)
1242 {
1243 regulator_disable(aic32x4->supply_iov);
1244
1245 if (!IS_ERR(aic32x4->supply_ldo))
1246 regulator_disable(aic32x4->supply_ldo);
1247
1248 if (!IS_ERR(aic32x4->supply_dv))
1249 regulator_disable(aic32x4->supply_dv);
1250
1251 if (!IS_ERR(aic32x4->supply_av))
1252 regulator_disable(aic32x4->supply_av);
1253 }
1254
aic32x4_setup_regulators(struct device * dev,struct aic32x4_priv * aic32x4)1255 static int aic32x4_setup_regulators(struct device *dev,
1256 struct aic32x4_priv *aic32x4)
1257 {
1258 int ret = 0;
1259
1260 aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin");
1261 aic32x4->supply_iov = devm_regulator_get(dev, "iov");
1262 aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv");
1263 aic32x4->supply_av = devm_regulator_get_optional(dev, "av");
1264
1265 /* Check if the regulator requirements are fulfilled */
1266
1267 if (IS_ERR(aic32x4->supply_iov)) {
1268 dev_err(dev, "Missing supply 'iov'\n");
1269 return PTR_ERR(aic32x4->supply_iov);
1270 }
1271
1272 if (IS_ERR(aic32x4->supply_ldo)) {
1273 if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER)
1274 return -EPROBE_DEFER;
1275
1276 if (IS_ERR(aic32x4->supply_dv)) {
1277 dev_err(dev, "Missing supply 'dv' or 'ldoin'\n");
1278 return PTR_ERR(aic32x4->supply_dv);
1279 }
1280 if (IS_ERR(aic32x4->supply_av)) {
1281 dev_err(dev, "Missing supply 'av' or 'ldoin'\n");
1282 return PTR_ERR(aic32x4->supply_av);
1283 }
1284 } else {
1285 if (PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER)
1286 return -EPROBE_DEFER;
1287 if (PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER)
1288 return -EPROBE_DEFER;
1289 }
1290
1291 ret = regulator_enable(aic32x4->supply_iov);
1292 if (ret) {
1293 dev_err(dev, "Failed to enable regulator iov\n");
1294 return ret;
1295 }
1296
1297 if (!IS_ERR(aic32x4->supply_ldo)) {
1298 ret = regulator_enable(aic32x4->supply_ldo);
1299 if (ret) {
1300 dev_err(dev, "Failed to enable regulator ldo\n");
1301 goto error_ldo;
1302 }
1303 }
1304
1305 if (!IS_ERR(aic32x4->supply_dv)) {
1306 ret = regulator_enable(aic32x4->supply_dv);
1307 if (ret) {
1308 dev_err(dev, "Failed to enable regulator dv\n");
1309 goto error_dv;
1310 }
1311 }
1312
1313 if (!IS_ERR(aic32x4->supply_av)) {
1314 ret = regulator_enable(aic32x4->supply_av);
1315 if (ret) {
1316 dev_err(dev, "Failed to enable regulator av\n");
1317 goto error_av;
1318 }
1319 }
1320
1321 if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av))
1322 aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE;
1323
1324 return 0;
1325
1326 error_av:
1327 if (!IS_ERR(aic32x4->supply_dv))
1328 regulator_disable(aic32x4->supply_dv);
1329
1330 error_dv:
1331 if (!IS_ERR(aic32x4->supply_ldo))
1332 regulator_disable(aic32x4->supply_ldo);
1333
1334 error_ldo:
1335 regulator_disable(aic32x4->supply_iov);
1336 return ret;
1337 }
1338
aic32x4_probe(struct device * dev,struct regmap * regmap)1339 int aic32x4_probe(struct device *dev, struct regmap *regmap)
1340 {
1341 struct aic32x4_priv *aic32x4;
1342 struct aic32x4_pdata *pdata = dev->platform_data;
1343 struct device_node *np = dev->of_node;
1344 int ret;
1345
1346 if (IS_ERR(regmap))
1347 return PTR_ERR(regmap);
1348
1349 aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv),
1350 GFP_KERNEL);
1351 if (aic32x4 == NULL)
1352 return -ENOMEM;
1353
1354 aic32x4->dev = dev;
1355 aic32x4->type = (enum aic32x4_type)dev_get_drvdata(dev);
1356
1357 dev_set_drvdata(dev, aic32x4);
1358
1359 if (pdata) {
1360 aic32x4->power_cfg = pdata->power_cfg;
1361 aic32x4->swapdacs = pdata->swapdacs;
1362 aic32x4->micpga_routing = pdata->micpga_routing;
1363 aic32x4->rstn_gpio = pdata->rstn_gpio;
1364 aic32x4->mclk_name = "mclk";
1365 } else if (np) {
1366 ret = aic32x4_parse_dt(aic32x4, np);
1367 if (ret) {
1368 dev_err(dev, "Failed to parse DT node\n");
1369 return ret;
1370 }
1371 } else {
1372 aic32x4->power_cfg = 0;
1373 aic32x4->swapdacs = false;
1374 aic32x4->micpga_routing = 0;
1375 aic32x4->rstn_gpio = -1;
1376 aic32x4->mclk_name = "mclk";
1377 }
1378
1379 if (gpio_is_valid(aic32x4->rstn_gpio)) {
1380 ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio,
1381 GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn");
1382 if (ret != 0)
1383 return ret;
1384 }
1385
1386 ret = aic32x4_setup_regulators(dev, aic32x4);
1387 if (ret) {
1388 dev_err(dev, "Failed to setup regulators\n");
1389 return ret;
1390 }
1391
1392 if (gpio_is_valid(aic32x4->rstn_gpio)) {
1393 ndelay(10);
1394 gpio_set_value_cansleep(aic32x4->rstn_gpio, 1);
1395 mdelay(1);
1396 }
1397
1398 ret = regmap_write(regmap, AIC32X4_RESET, 0x01);
1399 if (ret)
1400 goto err_disable_regulators;
1401
1402 ret = aic32x4_register_clocks(dev, aic32x4->mclk_name);
1403 if (ret)
1404 goto err_disable_regulators;
1405
1406 switch (aic32x4->type) {
1407 case AIC32X4_TYPE_TAS2505:
1408 ret = devm_snd_soc_register_component(dev,
1409 &soc_component_dev_aic32x4_tas2505, &aic32x4_tas2505_dai, 1);
1410 break;
1411 default:
1412 ret = devm_snd_soc_register_component(dev,
1413 &soc_component_dev_aic32x4, &aic32x4_dai, 1);
1414 }
1415
1416 if (ret) {
1417 dev_err(dev, "Failed to register component\n");
1418 goto err_disable_regulators;
1419 }
1420
1421 return 0;
1422
1423 err_disable_regulators:
1424 aic32x4_disable_regulators(aic32x4);
1425
1426 return ret;
1427 }
1428 EXPORT_SYMBOL(aic32x4_probe);
1429
aic32x4_remove(struct device * dev)1430 int aic32x4_remove(struct device *dev)
1431 {
1432 struct aic32x4_priv *aic32x4 = dev_get_drvdata(dev);
1433
1434 aic32x4_disable_regulators(aic32x4);
1435
1436 return 0;
1437 }
1438 EXPORT_SYMBOL(aic32x4_remove);
1439
1440 MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver");
1441 MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
1442 MODULE_LICENSE("GPL");
1443