1 /*
2 * ALSA SoC Synopsys I2S Audio Layer
3 *
4 * sound/soc/dwc/designware_i2s.c
5 *
6 * Copyright (C) 2010 ST Microelectronics
7 * Rajeev Kumar <rajeevkumar.linux@gmail.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14 #include <linux/clk.h>
15 #include <linux/device.h>
16 #include <linux/init.h>
17 #include <linux/io.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/slab.h>
21 #include <linux/pm_runtime.h>
22 #include <sound/designware_i2s.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/dmaengine_pcm.h>
27 #include "local.h"
28
i2s_write_reg(void __iomem * io_base,int reg,u32 val)29 static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val)
30 {
31 writel(val, io_base + reg);
32 }
33
i2s_read_reg(void __iomem * io_base,int reg)34 static inline u32 i2s_read_reg(void __iomem *io_base, int reg)
35 {
36 return readl(io_base + reg);
37 }
38
i2s_disable_channels(struct dw_i2s_dev * dev,u32 stream)39 static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream)
40 {
41 u32 i = 0;
42
43 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
44 for (i = 0; i < 4; i++)
45 i2s_write_reg(dev->i2s_base, TER(i), 0);
46 } else {
47 for (i = 0; i < 4; i++)
48 i2s_write_reg(dev->i2s_base, RER(i), 0);
49 }
50 }
51
i2s_clear_irqs(struct dw_i2s_dev * dev,u32 stream)52 static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream)
53 {
54 u32 i = 0;
55
56 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
57 for (i = 0; i < 4; i++)
58 i2s_read_reg(dev->i2s_base, TOR(i));
59 } else {
60 for (i = 0; i < 4; i++)
61 i2s_read_reg(dev->i2s_base, ROR(i));
62 }
63 }
64
i2s_disable_irqs(struct dw_i2s_dev * dev,u32 stream,int chan_nr)65 static inline void i2s_disable_irqs(struct dw_i2s_dev *dev, u32 stream,
66 int chan_nr)
67 {
68 u32 i, irq;
69
70 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
71 for (i = 0; i < (chan_nr / 2); i++) {
72 irq = i2s_read_reg(dev->i2s_base, IMR(i));
73 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30);
74 }
75 } else {
76 for (i = 0; i < (chan_nr / 2); i++) {
77 irq = i2s_read_reg(dev->i2s_base, IMR(i));
78 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03);
79 }
80 }
81 }
82
i2s_enable_irqs(struct dw_i2s_dev * dev,u32 stream,int chan_nr)83 static inline void i2s_enable_irqs(struct dw_i2s_dev *dev, u32 stream,
84 int chan_nr)
85 {
86 u32 i, irq;
87
88 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
89 for (i = 0; i < (chan_nr / 2); i++) {
90 irq = i2s_read_reg(dev->i2s_base, IMR(i));
91 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30);
92 }
93 } else {
94 for (i = 0; i < (chan_nr / 2); i++) {
95 irq = i2s_read_reg(dev->i2s_base, IMR(i));
96 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03);
97 }
98 }
99 }
100
i2s_irq_handler(int irq,void * dev_id)101 static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
102 {
103 struct dw_i2s_dev *dev = dev_id;
104 bool irq_valid = false;
105 u32 isr[4];
106 int i;
107
108 for (i = 0; i < 4; i++)
109 isr[i] = i2s_read_reg(dev->i2s_base, ISR(i));
110
111 i2s_clear_irqs(dev, SNDRV_PCM_STREAM_PLAYBACK);
112 i2s_clear_irqs(dev, SNDRV_PCM_STREAM_CAPTURE);
113
114 for (i = 0; i < 4; i++) {
115 /*
116 * Check if TX fifo is empty. If empty fill FIFO with samples
117 * NOTE: Only two channels supported
118 */
119 if ((isr[i] & ISR_TXFE) && (i == 0) && dev->use_pio) {
120 dw_pcm_push_tx(dev);
121 irq_valid = true;
122 }
123
124 /*
125 * Data available. Retrieve samples from FIFO
126 * NOTE: Only two channels supported
127 */
128 if ((isr[i] & ISR_RXDA) && (i == 0) && dev->use_pio) {
129 dw_pcm_pop_rx(dev);
130 irq_valid = true;
131 }
132
133 /* Error Handling: TX */
134 if (isr[i] & ISR_TXFO) {
135 dev_err_ratelimited(dev->dev, "TX overrun (ch_id=%d)\n", i);
136 irq_valid = true;
137 }
138
139 /* Error Handling: TX */
140 if (isr[i] & ISR_RXFO) {
141 dev_err_ratelimited(dev->dev, "RX overrun (ch_id=%d)\n", i);
142 irq_valid = true;
143 }
144 }
145
146 if (irq_valid)
147 return IRQ_HANDLED;
148 else
149 return IRQ_NONE;
150 }
151
i2s_start(struct dw_i2s_dev * dev,struct snd_pcm_substream * substream)152 static void i2s_start(struct dw_i2s_dev *dev,
153 struct snd_pcm_substream *substream)
154 {
155 struct i2s_clk_config_data *config = &dev->config;
156
157 i2s_write_reg(dev->i2s_base, IER, 1);
158 i2s_enable_irqs(dev, substream->stream, config->chan_nr);
159
160 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
161 i2s_write_reg(dev->i2s_base, ITER, 1);
162 else
163 i2s_write_reg(dev->i2s_base, IRER, 1);
164
165 i2s_write_reg(dev->i2s_base, CER, 1);
166 }
167
i2s_stop(struct dw_i2s_dev * dev,struct snd_pcm_substream * substream)168 static void i2s_stop(struct dw_i2s_dev *dev,
169 struct snd_pcm_substream *substream)
170 {
171
172 i2s_clear_irqs(dev, substream->stream);
173 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
174 i2s_write_reg(dev->i2s_base, ITER, 0);
175 else
176 i2s_write_reg(dev->i2s_base, IRER, 0);
177
178 i2s_disable_irqs(dev, substream->stream, 8);
179
180 if (!dev->active) {
181 i2s_write_reg(dev->i2s_base, CER, 0);
182 i2s_write_reg(dev->i2s_base, IER, 0);
183 }
184 }
185
dw_i2s_config(struct dw_i2s_dev * dev,int stream)186 static void dw_i2s_config(struct dw_i2s_dev *dev, int stream)
187 {
188 u32 ch_reg;
189 struct i2s_clk_config_data *config = &dev->config;
190
191
192 i2s_disable_channels(dev, stream);
193
194 for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) {
195 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
196 i2s_write_reg(dev->i2s_base, TCR(ch_reg),
197 dev->xfer_resolution);
198 i2s_write_reg(dev->i2s_base, TFCR(ch_reg),
199 dev->fifo_th - 1);
200 i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
201 } else {
202 i2s_write_reg(dev->i2s_base, RCR(ch_reg),
203 dev->xfer_resolution);
204 i2s_write_reg(dev->i2s_base, RFCR(ch_reg),
205 dev->fifo_th - 1);
206 i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
207 }
208
209 }
210 }
211
dw_i2s_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)212 static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
213 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
214 {
215 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
216 struct i2s_clk_config_data *config = &dev->config;
217 int ret;
218
219 switch (params_format(params)) {
220 case SNDRV_PCM_FORMAT_S16_LE:
221 config->data_width = 16;
222 dev->ccr = 0x00;
223 dev->xfer_resolution = 0x02;
224 break;
225
226 case SNDRV_PCM_FORMAT_S24_LE:
227 config->data_width = 24;
228 dev->ccr = 0x08;
229 dev->xfer_resolution = 0x04;
230 break;
231
232 case SNDRV_PCM_FORMAT_S32_LE:
233 config->data_width = 32;
234 dev->ccr = 0x10;
235 dev->xfer_resolution = 0x05;
236 break;
237
238 default:
239 dev_err(dev->dev, "designware-i2s: unsupported PCM fmt");
240 return -EINVAL;
241 }
242
243 config->chan_nr = params_channels(params);
244
245 switch (config->chan_nr) {
246 case EIGHT_CHANNEL_SUPPORT:
247 case SIX_CHANNEL_SUPPORT:
248 case FOUR_CHANNEL_SUPPORT:
249 case TWO_CHANNEL_SUPPORT:
250 break;
251 default:
252 dev_err(dev->dev, "channel not supported\n");
253 return -EINVAL;
254 }
255
256 dw_i2s_config(dev, substream->stream);
257
258 i2s_write_reg(dev->i2s_base, CCR, dev->ccr);
259
260 config->sample_rate = params_rate(params);
261
262 if (dev->capability & DW_I2S_MASTER) {
263 if (dev->i2s_clk_cfg) {
264 ret = dev->i2s_clk_cfg(config);
265 if (ret < 0) {
266 dev_err(dev->dev, "runtime audio clk config fail\n");
267 return ret;
268 }
269 } else {
270 u32 bitclk = config->sample_rate *
271 config->data_width * 2;
272
273 ret = clk_set_rate(dev->clk, bitclk);
274 if (ret) {
275 dev_err(dev->dev, "Can't set I2S clock rate: %d\n",
276 ret);
277 return ret;
278 }
279 }
280 }
281 return 0;
282 }
283
dw_i2s_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)284 static int dw_i2s_prepare(struct snd_pcm_substream *substream,
285 struct snd_soc_dai *dai)
286 {
287 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
288
289 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
290 i2s_write_reg(dev->i2s_base, TXFFR, 1);
291 else
292 i2s_write_reg(dev->i2s_base, RXFFR, 1);
293
294 return 0;
295 }
296
dw_i2s_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)297 static int dw_i2s_trigger(struct snd_pcm_substream *substream,
298 int cmd, struct snd_soc_dai *dai)
299 {
300 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
301 int ret = 0;
302
303 switch (cmd) {
304 case SNDRV_PCM_TRIGGER_START:
305 case SNDRV_PCM_TRIGGER_RESUME:
306 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
307 dev->active++;
308 i2s_start(dev, substream);
309 break;
310
311 case SNDRV_PCM_TRIGGER_STOP:
312 case SNDRV_PCM_TRIGGER_SUSPEND:
313 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
314 dev->active--;
315 i2s_stop(dev, substream);
316 break;
317 default:
318 ret = -EINVAL;
319 break;
320 }
321 return ret;
322 }
323
dw_i2s_set_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)324 static int dw_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
325 {
326 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
327 int ret = 0;
328
329 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
330 case SND_SOC_DAIFMT_CBM_CFM:
331 if (dev->capability & DW_I2S_SLAVE)
332 ret = 0;
333 else
334 ret = -EINVAL;
335 break;
336 case SND_SOC_DAIFMT_CBS_CFS:
337 if (dev->capability & DW_I2S_MASTER)
338 ret = 0;
339 else
340 ret = -EINVAL;
341 break;
342 case SND_SOC_DAIFMT_CBM_CFS:
343 case SND_SOC_DAIFMT_CBS_CFM:
344 ret = -EINVAL;
345 break;
346 default:
347 dev_dbg(dev->dev, "dwc : Invalid master/slave format\n");
348 ret = -EINVAL;
349 break;
350 }
351 return ret;
352 }
353
354 static const struct snd_soc_dai_ops dw_i2s_dai_ops = {
355 .hw_params = dw_i2s_hw_params,
356 .prepare = dw_i2s_prepare,
357 .trigger = dw_i2s_trigger,
358 .set_fmt = dw_i2s_set_fmt,
359 };
360
361 #ifdef CONFIG_PM
dw_i2s_runtime_suspend(struct device * dev)362 static int dw_i2s_runtime_suspend(struct device *dev)
363 {
364 struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev);
365
366 if (dw_dev->capability & DW_I2S_MASTER)
367 clk_disable(dw_dev->clk);
368 return 0;
369 }
370
dw_i2s_runtime_resume(struct device * dev)371 static int dw_i2s_runtime_resume(struct device *dev)
372 {
373 struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev);
374 int ret;
375
376 if (dw_dev->capability & DW_I2S_MASTER) {
377 ret = clk_enable(dw_dev->clk);
378 if (ret)
379 return ret;
380 }
381 return 0;
382 }
383
dw_i2s_suspend(struct snd_soc_component * component)384 static int dw_i2s_suspend(struct snd_soc_component *component)
385 {
386 struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component);
387
388 if (dev->capability & DW_I2S_MASTER)
389 clk_disable(dev->clk);
390 return 0;
391 }
392
dw_i2s_resume(struct snd_soc_component * component)393 static int dw_i2s_resume(struct snd_soc_component *component)
394 {
395 struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component);
396 struct snd_soc_dai *dai;
397 int stream, ret;
398
399 if (dev->capability & DW_I2S_MASTER) {
400 ret = clk_enable(dev->clk);
401 if (ret)
402 return ret;
403 }
404
405 for_each_component_dais(component, dai) {
406 for_each_pcm_streams(stream)
407 if (snd_soc_dai_stream_active(dai, stream))
408 dw_i2s_config(dev, stream);
409 }
410
411 return 0;
412 }
413
414 #else
415 #define dw_i2s_suspend NULL
416 #define dw_i2s_resume NULL
417 #endif
418
419 static const struct snd_soc_component_driver dw_i2s_component = {
420 .name = "dw-i2s",
421 .suspend = dw_i2s_suspend,
422 .resume = dw_i2s_resume,
423 };
424
425 /*
426 * The following tables allow a direct lookup of various parameters
427 * defined in the I2S block's configuration in terms of sound system
428 * parameters. Each table is sized to the number of entries possible
429 * according to the number of configuration bits describing an I2S
430 * block parameter.
431 */
432
433 /* Maximum bit resolution of a channel - not uniformly spaced */
434 static const u32 fifo_width[COMP_MAX_WORDSIZE] = {
435 12, 16, 20, 24, 32, 0, 0, 0
436 };
437
438 /* Width of (DMA) bus */
439 static const u32 bus_widths[COMP_MAX_DATA_WIDTH] = {
440 DMA_SLAVE_BUSWIDTH_1_BYTE,
441 DMA_SLAVE_BUSWIDTH_2_BYTES,
442 DMA_SLAVE_BUSWIDTH_4_BYTES,
443 DMA_SLAVE_BUSWIDTH_UNDEFINED
444 };
445
446 /* PCM format to support channel resolution */
447 static const u32 formats[COMP_MAX_WORDSIZE] = {
448 SNDRV_PCM_FMTBIT_S16_LE,
449 SNDRV_PCM_FMTBIT_S16_LE,
450 SNDRV_PCM_FMTBIT_S24_LE,
451 SNDRV_PCM_FMTBIT_S24_LE,
452 SNDRV_PCM_FMTBIT_S32_LE,
453 0,
454 0,
455 0
456 };
457
dw_configure_dai(struct dw_i2s_dev * dev,struct snd_soc_dai_driver * dw_i2s_dai,unsigned int rates)458 static int dw_configure_dai(struct dw_i2s_dev *dev,
459 struct snd_soc_dai_driver *dw_i2s_dai,
460 unsigned int rates)
461 {
462 /*
463 * Read component parameter registers to extract
464 * the I2S block's configuration.
465 */
466 u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
467 u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2);
468 u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
469 u32 idx;
470
471 if (dev->capability & DWC_I2S_RECORD &&
472 dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
473 comp1 = comp1 & ~BIT(5);
474
475 if (dev->capability & DWC_I2S_PLAY &&
476 dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
477 comp1 = comp1 & ~BIT(6);
478
479 if (COMP1_TX_ENABLED(comp1)) {
480 dev_dbg(dev->dev, " designware: play supported\n");
481 idx = COMP1_TX_WORDSIZE_0(comp1);
482 if (WARN_ON(idx >= ARRAY_SIZE(formats)))
483 return -EINVAL;
484 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
485 idx = 1;
486 dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM;
487 dw_i2s_dai->playback.channels_max =
488 1 << (COMP1_TX_CHANNELS(comp1) + 1);
489 dw_i2s_dai->playback.formats = formats[idx];
490 dw_i2s_dai->playback.rates = rates;
491 }
492
493 if (COMP1_RX_ENABLED(comp1)) {
494 dev_dbg(dev->dev, "designware: record supported\n");
495 idx = COMP2_RX_WORDSIZE_0(comp2);
496 if (WARN_ON(idx >= ARRAY_SIZE(formats)))
497 return -EINVAL;
498 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
499 idx = 1;
500 dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM;
501 dw_i2s_dai->capture.channels_max =
502 1 << (COMP1_RX_CHANNELS(comp1) + 1);
503 dw_i2s_dai->capture.formats = formats[idx];
504 dw_i2s_dai->capture.rates = rates;
505 }
506
507 if (COMP1_MODE_EN(comp1)) {
508 dev_dbg(dev->dev, "designware: i2s master mode supported\n");
509 dev->capability |= DW_I2S_MASTER;
510 } else {
511 dev_dbg(dev->dev, "designware: i2s slave mode supported\n");
512 dev->capability |= DW_I2S_SLAVE;
513 }
514
515 dev->fifo_th = fifo_depth / 2;
516 return 0;
517 }
518
dw_configure_dai_by_pd(struct dw_i2s_dev * dev,struct snd_soc_dai_driver * dw_i2s_dai,struct resource * res,const struct i2s_platform_data * pdata)519 static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev,
520 struct snd_soc_dai_driver *dw_i2s_dai,
521 struct resource *res,
522 const struct i2s_platform_data *pdata)
523 {
524 u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
525 u32 idx = COMP1_APB_DATA_WIDTH(comp1);
526 int ret;
527
528 if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
529 return -EINVAL;
530
531 ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates);
532 if (ret < 0)
533 return ret;
534
535 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
536 idx = 1;
537 /* Set DMA slaves info */
538 dev->play_dma_data.pd.data = pdata->play_dma_data;
539 dev->capture_dma_data.pd.data = pdata->capture_dma_data;
540 dev->play_dma_data.pd.addr = res->start + I2S_TXDMA;
541 dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA;
542 dev->play_dma_data.pd.max_burst = 16;
543 dev->capture_dma_data.pd.max_burst = 16;
544 dev->play_dma_data.pd.addr_width = bus_widths[idx];
545 dev->capture_dma_data.pd.addr_width = bus_widths[idx];
546 dev->play_dma_data.pd.filter = pdata->filter;
547 dev->capture_dma_data.pd.filter = pdata->filter;
548
549 return 0;
550 }
551
dw_configure_dai_by_dt(struct dw_i2s_dev * dev,struct snd_soc_dai_driver * dw_i2s_dai,struct resource * res)552 static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev,
553 struct snd_soc_dai_driver *dw_i2s_dai,
554 struct resource *res)
555 {
556 u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);
557 u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);
558 u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
559 u32 idx = COMP1_APB_DATA_WIDTH(comp1);
560 u32 idx2;
561 int ret;
562
563 if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
564 return -EINVAL;
565
566 ret = dw_configure_dai(dev, dw_i2s_dai, SNDRV_PCM_RATE_8000_192000);
567 if (ret < 0)
568 return ret;
569
570 if (COMP1_TX_ENABLED(comp1)) {
571 idx2 = COMP1_TX_WORDSIZE_0(comp1);
572
573 dev->capability |= DWC_I2S_PLAY;
574 dev->play_dma_data.dt.addr = res->start + I2S_TXDMA;
575 dev->play_dma_data.dt.addr_width = bus_widths[idx];
576 dev->play_dma_data.dt.fifo_size = fifo_depth *
577 (fifo_width[idx2]) >> 8;
578 dev->play_dma_data.dt.maxburst = 16;
579 }
580 if (COMP1_RX_ENABLED(comp1)) {
581 idx2 = COMP2_RX_WORDSIZE_0(comp2);
582
583 dev->capability |= DWC_I2S_RECORD;
584 dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA;
585 dev->capture_dma_data.dt.addr_width = bus_widths[idx];
586 dev->capture_dma_data.dt.fifo_size = fifo_depth *
587 (fifo_width[idx2] >> 8);
588 dev->capture_dma_data.dt.maxburst = 16;
589 }
590
591 return 0;
592
593 }
594
dw_i2s_dai_probe(struct snd_soc_dai * dai)595 static int dw_i2s_dai_probe(struct snd_soc_dai *dai)
596 {
597 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
598
599 snd_soc_dai_init_dma_data(dai, &dev->play_dma_data, &dev->capture_dma_data);
600 return 0;
601 }
602
dw_i2s_probe(struct platform_device * pdev)603 static int dw_i2s_probe(struct platform_device *pdev)
604 {
605 const struct i2s_platform_data *pdata = pdev->dev.platform_data;
606 struct dw_i2s_dev *dev;
607 struct resource *res;
608 int ret, irq;
609 struct snd_soc_dai_driver *dw_i2s_dai;
610 const char *clk_id;
611
612 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
613 if (!dev)
614 return -ENOMEM;
615
616 dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL);
617 if (!dw_i2s_dai)
618 return -ENOMEM;
619
620 dw_i2s_dai->ops = &dw_i2s_dai_ops;
621 dw_i2s_dai->probe = dw_i2s_dai_probe;
622
623 dev->i2s_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
624 if (IS_ERR(dev->i2s_base))
625 return PTR_ERR(dev->i2s_base);
626
627 dev->dev = &pdev->dev;
628
629 irq = platform_get_irq_optional(pdev, 0);
630 if (irq >= 0) {
631 ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0,
632 pdev->name, dev);
633 if (ret < 0) {
634 dev_err(&pdev->dev, "failed to request irq\n");
635 return ret;
636 }
637 }
638
639 dev->i2s_reg_comp1 = I2S_COMP_PARAM_1;
640 dev->i2s_reg_comp2 = I2S_COMP_PARAM_2;
641 if (pdata) {
642 dev->capability = pdata->cap;
643 clk_id = NULL;
644 dev->quirks = pdata->quirks;
645 if (dev->quirks & DW_I2S_QUIRK_COMP_REG_OFFSET) {
646 dev->i2s_reg_comp1 = pdata->i2s_reg_comp1;
647 dev->i2s_reg_comp2 = pdata->i2s_reg_comp2;
648 }
649 ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata);
650 } else {
651 clk_id = "i2sclk";
652 ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res);
653 }
654 if (ret < 0)
655 return ret;
656
657 if (dev->capability & DW_I2S_MASTER) {
658 if (pdata) {
659 dev->i2s_clk_cfg = pdata->i2s_clk_cfg;
660 if (!dev->i2s_clk_cfg) {
661 dev_err(&pdev->dev, "no clock configure method\n");
662 return -ENODEV;
663 }
664 }
665 dev->clk = devm_clk_get(&pdev->dev, clk_id);
666
667 if (IS_ERR(dev->clk))
668 return PTR_ERR(dev->clk);
669
670 ret = clk_prepare_enable(dev->clk);
671 if (ret < 0)
672 return ret;
673 }
674
675 dev_set_drvdata(&pdev->dev, dev);
676 ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component,
677 dw_i2s_dai, 1);
678 if (ret != 0) {
679 dev_err(&pdev->dev, "not able to register dai\n");
680 goto err_clk_disable;
681 }
682
683 if (!pdata) {
684 if (irq >= 0) {
685 ret = dw_pcm_register(pdev);
686 dev->use_pio = true;
687 } else {
688 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
689 0);
690 dev->use_pio = false;
691 }
692
693 if (ret) {
694 dev_err(&pdev->dev, "could not register pcm: %d\n",
695 ret);
696 goto err_clk_disable;
697 }
698 }
699
700 pm_runtime_enable(&pdev->dev);
701 return 0;
702
703 err_clk_disable:
704 if (dev->capability & DW_I2S_MASTER)
705 clk_disable_unprepare(dev->clk);
706 return ret;
707 }
708
dw_i2s_remove(struct platform_device * pdev)709 static int dw_i2s_remove(struct platform_device *pdev)
710 {
711 struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev);
712
713 if (dev->capability & DW_I2S_MASTER)
714 clk_disable_unprepare(dev->clk);
715
716 pm_runtime_disable(&pdev->dev);
717 return 0;
718 }
719
720 #ifdef CONFIG_OF
721 static const struct of_device_id dw_i2s_of_match[] = {
722 { .compatible = "snps,designware-i2s", },
723 {},
724 };
725
726 MODULE_DEVICE_TABLE(of, dw_i2s_of_match);
727 #endif
728
729 static const struct dev_pm_ops dwc_pm_ops = {
730 SET_RUNTIME_PM_OPS(dw_i2s_runtime_suspend, dw_i2s_runtime_resume, NULL)
731 };
732
733 static struct platform_driver dw_i2s_driver = {
734 .probe = dw_i2s_probe,
735 .remove = dw_i2s_remove,
736 .driver = {
737 .name = "designware-i2s",
738 .of_match_table = of_match_ptr(dw_i2s_of_match),
739 .pm = &dwc_pm_ops,
740 },
741 };
742
743 module_platform_driver(dw_i2s_driver);
744
745 MODULE_AUTHOR("Rajeev Kumar <rajeevkumar.linux@gmail.com>");
746 MODULE_DESCRIPTION("DESIGNWARE I2S SoC Interface");
747 MODULE_LICENSE("GPL");
748 MODULE_ALIAS("platform:designware_i2s");
749