1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
4 *
5 * Copyright (C) 2008 Nokia Corporation
6 *
7 * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
8 * Peter Ujfalusi <peter.ujfalusi@ti.com>
9 */
10
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/of.h>
16 #include <linux/of_device.h>
17 #include <sound/core.h>
18 #include <sound/pcm.h>
19 #include <sound/pcm_params.h>
20 #include <sound/initval.h>
21 #include <sound/soc.h>
22 #include <sound/dmaengine_pcm.h>
23
24 #include "omap-mcbsp-priv.h"
25 #include "omap-mcbsp.h"
26 #include "sdma-pcm.h"
27
28 #define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
29
30 enum {
31 OMAP_MCBSP_WORD_8 = 0,
32 OMAP_MCBSP_WORD_12,
33 OMAP_MCBSP_WORD_16,
34 OMAP_MCBSP_WORD_20,
35 OMAP_MCBSP_WORD_24,
36 OMAP_MCBSP_WORD_32,
37 };
38
omap_mcbsp_dump_reg(struct omap_mcbsp * mcbsp)39 static void omap_mcbsp_dump_reg(struct omap_mcbsp *mcbsp)
40 {
41 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
42 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n", MCBSP_READ(mcbsp, DRR2));
43 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n", MCBSP_READ(mcbsp, DRR1));
44 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n", MCBSP_READ(mcbsp, DXR2));
45 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n", MCBSP_READ(mcbsp, DXR1));
46 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n", MCBSP_READ(mcbsp, SPCR2));
47 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n", MCBSP_READ(mcbsp, SPCR1));
48 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n", MCBSP_READ(mcbsp, RCR2));
49 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n", MCBSP_READ(mcbsp, RCR1));
50 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n", MCBSP_READ(mcbsp, XCR2));
51 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n", MCBSP_READ(mcbsp, XCR1));
52 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n", MCBSP_READ(mcbsp, SRGR2));
53 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n", MCBSP_READ(mcbsp, SRGR1));
54 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n", MCBSP_READ(mcbsp, PCR0));
55 dev_dbg(mcbsp->dev, "***********************\n");
56 }
57
omap2_mcbsp_set_clks_src(struct omap_mcbsp * mcbsp,u8 fck_src_id)58 static int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id)
59 {
60 struct clk *fck_src;
61 const char *src;
62 int r;
63
64 if (fck_src_id == MCBSP_CLKS_PAD_SRC)
65 src = "pad_fck";
66 else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
67 src = "prcm_fck";
68 else
69 return -EINVAL;
70
71 fck_src = clk_get(mcbsp->dev, src);
72 if (IS_ERR(fck_src)) {
73 dev_err(mcbsp->dev, "CLKS: could not clk_get() %s\n", src);
74 return -EINVAL;
75 }
76
77 if (mcbsp->active)
78 pm_runtime_put_sync(mcbsp->dev);
79
80 r = clk_set_parent(mcbsp->fclk, fck_src);
81 if (r)
82 dev_err(mcbsp->dev, "CLKS: could not clk_set_parent() to %s\n",
83 src);
84
85 if (mcbsp->active)
86 pm_runtime_get_sync(mcbsp->dev);
87
88 clk_put(fck_src);
89
90 return r;
91 }
92
omap_mcbsp_irq_handler(int irq,void * data)93 static irqreturn_t omap_mcbsp_irq_handler(int irq, void *data)
94 {
95 struct omap_mcbsp *mcbsp = data;
96 u16 irqst;
97
98 irqst = MCBSP_READ(mcbsp, IRQST);
99 dev_dbg(mcbsp->dev, "IRQ callback : 0x%x\n", irqst);
100
101 if (irqst & RSYNCERREN)
102 dev_err(mcbsp->dev, "RX Frame Sync Error!\n");
103 if (irqst & RFSREN)
104 dev_dbg(mcbsp->dev, "RX Frame Sync\n");
105 if (irqst & REOFEN)
106 dev_dbg(mcbsp->dev, "RX End Of Frame\n");
107 if (irqst & RRDYEN)
108 dev_dbg(mcbsp->dev, "RX Buffer Threshold Reached\n");
109 if (irqst & RUNDFLEN)
110 dev_err(mcbsp->dev, "RX Buffer Underflow!\n");
111 if (irqst & ROVFLEN)
112 dev_err(mcbsp->dev, "RX Buffer Overflow!\n");
113
114 if (irqst & XSYNCERREN)
115 dev_err(mcbsp->dev, "TX Frame Sync Error!\n");
116 if (irqst & XFSXEN)
117 dev_dbg(mcbsp->dev, "TX Frame Sync\n");
118 if (irqst & XEOFEN)
119 dev_dbg(mcbsp->dev, "TX End Of Frame\n");
120 if (irqst & XRDYEN)
121 dev_dbg(mcbsp->dev, "TX Buffer threshold Reached\n");
122 if (irqst & XUNDFLEN)
123 dev_err(mcbsp->dev, "TX Buffer Underflow!\n");
124 if (irqst & XOVFLEN)
125 dev_err(mcbsp->dev, "TX Buffer Overflow!\n");
126 if (irqst & XEMPTYEOFEN)
127 dev_dbg(mcbsp->dev, "TX Buffer empty at end of frame\n");
128
129 MCBSP_WRITE(mcbsp, IRQST, irqst);
130
131 return IRQ_HANDLED;
132 }
133
omap_mcbsp_tx_irq_handler(int irq,void * data)134 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *data)
135 {
136 struct omap_mcbsp *mcbsp = data;
137 u16 irqst_spcr2;
138
139 irqst_spcr2 = MCBSP_READ(mcbsp, SPCR2);
140 dev_dbg(mcbsp->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
141
142 if (irqst_spcr2 & XSYNC_ERR) {
143 dev_err(mcbsp->dev, "TX Frame Sync Error! : 0x%x\n",
144 irqst_spcr2);
145 /* Writing zero to XSYNC_ERR clears the IRQ */
146 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
147 }
148
149 return IRQ_HANDLED;
150 }
151
omap_mcbsp_rx_irq_handler(int irq,void * data)152 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *data)
153 {
154 struct omap_mcbsp *mcbsp = data;
155 u16 irqst_spcr1;
156
157 irqst_spcr1 = MCBSP_READ(mcbsp, SPCR1);
158 dev_dbg(mcbsp->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
159
160 if (irqst_spcr1 & RSYNC_ERR) {
161 dev_err(mcbsp->dev, "RX Frame Sync Error! : 0x%x\n",
162 irqst_spcr1);
163 /* Writing zero to RSYNC_ERR clears the IRQ */
164 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
165 }
166
167 return IRQ_HANDLED;
168 }
169
170 /*
171 * omap_mcbsp_config simply write a config to the
172 * appropriate McBSP.
173 * You either call this function or set the McBSP registers
174 * by yourself before calling omap_mcbsp_start().
175 */
omap_mcbsp_config(struct omap_mcbsp * mcbsp,const struct omap_mcbsp_reg_cfg * config)176 static void omap_mcbsp_config(struct omap_mcbsp *mcbsp,
177 const struct omap_mcbsp_reg_cfg *config)
178 {
179 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
180 mcbsp->id, mcbsp->phys_base);
181
182 /* We write the given config */
183 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
184 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
185 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
186 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
187 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
188 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
189 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
190 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
191 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
192 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
193 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
194 if (mcbsp->pdata->has_ccr) {
195 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
196 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
197 }
198 /* Enable wakeup behavior */
199 if (mcbsp->pdata->has_wakeup)
200 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
201
202 /* Enable TX/RX sync error interrupts by default */
203 if (mcbsp->irq)
204 MCBSP_WRITE(mcbsp, IRQEN, RSYNCERREN | XSYNCERREN |
205 RUNDFLEN | ROVFLEN | XUNDFLEN | XOVFLEN);
206 }
207
208 /**
209 * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
210 * @mcbsp: omap_mcbsp struct for the McBSP instance
211 * @stream: Stream direction (playback/capture)
212 *
213 * Returns the address of mcbsp data transmit register or data receive register
214 * to be used by DMA for transferring/receiving data
215 */
omap_mcbsp_dma_reg_params(struct omap_mcbsp * mcbsp,unsigned int stream)216 static int omap_mcbsp_dma_reg_params(struct omap_mcbsp *mcbsp,
217 unsigned int stream)
218 {
219 int data_reg;
220
221 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
222 if (mcbsp->pdata->reg_size == 2)
223 data_reg = OMAP_MCBSP_REG_DXR1;
224 else
225 data_reg = OMAP_MCBSP_REG_DXR;
226 } else {
227 if (mcbsp->pdata->reg_size == 2)
228 data_reg = OMAP_MCBSP_REG_DRR1;
229 else
230 data_reg = OMAP_MCBSP_REG_DRR;
231 }
232
233 return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
234 }
235
236 /*
237 * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
238 * The threshold parameter is 1 based, and it is converted (threshold - 1)
239 * for the THRSH2 register.
240 */
omap_mcbsp_set_tx_threshold(struct omap_mcbsp * mcbsp,u16 threshold)241 static void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
242 {
243 if (threshold && threshold <= mcbsp->max_tx_thres)
244 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
245 }
246
247 /*
248 * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
249 * The threshold parameter is 1 based, and it is converted (threshold - 1)
250 * for the THRSH1 register.
251 */
omap_mcbsp_set_rx_threshold(struct omap_mcbsp * mcbsp,u16 threshold)252 static void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
253 {
254 if (threshold && threshold <= mcbsp->max_rx_thres)
255 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
256 }
257
258 /*
259 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
260 */
omap_mcbsp_get_tx_delay(struct omap_mcbsp * mcbsp)261 static u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp)
262 {
263 u16 buffstat;
264
265 /* Returns the number of free locations in the buffer */
266 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
267
268 /* Number of slots are different in McBSP ports */
269 return mcbsp->pdata->buffer_size - buffstat;
270 }
271
272 /*
273 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
274 * to reach the threshold value (when the DMA will be triggered to read it)
275 */
omap_mcbsp_get_rx_delay(struct omap_mcbsp * mcbsp)276 static u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp)
277 {
278 u16 buffstat, threshold;
279
280 /* Returns the number of used locations in the buffer */
281 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
282 /* RX threshold */
283 threshold = MCBSP_READ(mcbsp, THRSH1);
284
285 /* Return the number of location till we reach the threshold limit */
286 if (threshold <= buffstat)
287 return 0;
288 else
289 return threshold - buffstat;
290 }
291
omap_mcbsp_request(struct omap_mcbsp * mcbsp)292 static int omap_mcbsp_request(struct omap_mcbsp *mcbsp)
293 {
294 void *reg_cache;
295 int err;
296
297 reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
298 if (!reg_cache)
299 return -ENOMEM;
300
301 spin_lock(&mcbsp->lock);
302 if (!mcbsp->free) {
303 dev_err(mcbsp->dev, "McBSP%d is currently in use\n", mcbsp->id);
304 err = -EBUSY;
305 goto err_kfree;
306 }
307
308 mcbsp->free = false;
309 mcbsp->reg_cache = reg_cache;
310 spin_unlock(&mcbsp->lock);
311
312 if(mcbsp->pdata->ops && mcbsp->pdata->ops->request)
313 mcbsp->pdata->ops->request(mcbsp->id - 1);
314
315 /*
316 * Make sure that transmitter, receiver and sample-rate generator are
317 * not running before activating IRQs.
318 */
319 MCBSP_WRITE(mcbsp, SPCR1, 0);
320 MCBSP_WRITE(mcbsp, SPCR2, 0);
321
322 if (mcbsp->irq) {
323 err = request_irq(mcbsp->irq, omap_mcbsp_irq_handler, 0,
324 "McBSP", (void *)mcbsp);
325 if (err != 0) {
326 dev_err(mcbsp->dev, "Unable to request IRQ\n");
327 goto err_clk_disable;
328 }
329 } else {
330 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler, 0,
331 "McBSP TX", (void *)mcbsp);
332 if (err != 0) {
333 dev_err(mcbsp->dev, "Unable to request TX IRQ\n");
334 goto err_clk_disable;
335 }
336
337 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler, 0,
338 "McBSP RX", (void *)mcbsp);
339 if (err != 0) {
340 dev_err(mcbsp->dev, "Unable to request RX IRQ\n");
341 goto err_free_irq;
342 }
343 }
344
345 return 0;
346 err_free_irq:
347 free_irq(mcbsp->tx_irq, (void *)mcbsp);
348 err_clk_disable:
349 if(mcbsp->pdata->ops && mcbsp->pdata->ops->free)
350 mcbsp->pdata->ops->free(mcbsp->id - 1);
351
352 /* Disable wakeup behavior */
353 if (mcbsp->pdata->has_wakeup)
354 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
355
356 spin_lock(&mcbsp->lock);
357 mcbsp->free = true;
358 mcbsp->reg_cache = NULL;
359 err_kfree:
360 spin_unlock(&mcbsp->lock);
361 kfree(reg_cache);
362
363 return err;
364 }
365
omap_mcbsp_free(struct omap_mcbsp * mcbsp)366 static void omap_mcbsp_free(struct omap_mcbsp *mcbsp)
367 {
368 void *reg_cache;
369
370 if(mcbsp->pdata->ops && mcbsp->pdata->ops->free)
371 mcbsp->pdata->ops->free(mcbsp->id - 1);
372
373 /* Disable wakeup behavior */
374 if (mcbsp->pdata->has_wakeup)
375 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
376
377 /* Disable interrupt requests */
378 if (mcbsp->irq) {
379 MCBSP_WRITE(mcbsp, IRQEN, 0);
380
381 free_irq(mcbsp->irq, (void *)mcbsp);
382 } else {
383 free_irq(mcbsp->rx_irq, (void *)mcbsp);
384 free_irq(mcbsp->tx_irq, (void *)mcbsp);
385 }
386
387 reg_cache = mcbsp->reg_cache;
388
389 /*
390 * Select CLKS source from internal source unconditionally before
391 * marking the McBSP port as free.
392 * If the external clock source via MCBSP_CLKS pin has been selected the
393 * system will refuse to enter idle if the CLKS pin source is not reset
394 * back to internal source.
395 */
396 if (!mcbsp_omap1())
397 omap2_mcbsp_set_clks_src(mcbsp, MCBSP_CLKS_PRCM_SRC);
398
399 spin_lock(&mcbsp->lock);
400 if (mcbsp->free)
401 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
402 else
403 mcbsp->free = true;
404 mcbsp->reg_cache = NULL;
405 spin_unlock(&mcbsp->lock);
406
407 kfree(reg_cache);
408 }
409
410 /*
411 * Here we start the McBSP, by enabling transmitter, receiver or both.
412 * If no transmitter or receiver is active prior calling, then sample-rate
413 * generator and frame sync are started.
414 */
omap_mcbsp_start(struct omap_mcbsp * mcbsp,int stream)415 static void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int stream)
416 {
417 int tx = (stream == SNDRV_PCM_STREAM_PLAYBACK);
418 int rx = !tx;
419 int enable_srg = 0;
420 u16 w;
421
422 if (mcbsp->st_data)
423 omap_mcbsp_st_start(mcbsp);
424
425 /* Only enable SRG, if McBSP is master */
426 w = MCBSP_READ_CACHE(mcbsp, PCR0);
427 if (w & (FSXM | FSRM | CLKXM | CLKRM))
428 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
429 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
430
431 if (enable_srg) {
432 /* Start the sample generator */
433 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
434 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
435 }
436
437 /* Enable transmitter and receiver */
438 tx &= 1;
439 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
440 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
441
442 rx &= 1;
443 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
444 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
445
446 /*
447 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
448 * REVISIT: 100us may give enough time for two CLKSRG, however
449 * due to some unknown PM related, clock gating etc. reason it
450 * is now at 500us.
451 */
452 udelay(500);
453
454 if (enable_srg) {
455 /* Start frame sync */
456 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
457 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
458 }
459
460 if (mcbsp->pdata->has_ccr) {
461 /* Release the transmitter and receiver */
462 w = MCBSP_READ_CACHE(mcbsp, XCCR);
463 w &= ~(tx ? XDISABLE : 0);
464 MCBSP_WRITE(mcbsp, XCCR, w);
465 w = MCBSP_READ_CACHE(mcbsp, RCCR);
466 w &= ~(rx ? RDISABLE : 0);
467 MCBSP_WRITE(mcbsp, RCCR, w);
468 }
469
470 /* Dump McBSP Regs */
471 omap_mcbsp_dump_reg(mcbsp);
472 }
473
omap_mcbsp_stop(struct omap_mcbsp * mcbsp,int stream)474 static void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int stream)
475 {
476 int tx = (stream == SNDRV_PCM_STREAM_PLAYBACK);
477 int rx = !tx;
478 int idle;
479 u16 w;
480
481 /* Reset transmitter */
482 tx &= 1;
483 if (mcbsp->pdata->has_ccr) {
484 w = MCBSP_READ_CACHE(mcbsp, XCCR);
485 w |= (tx ? XDISABLE : 0);
486 MCBSP_WRITE(mcbsp, XCCR, w);
487 }
488 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
489 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
490
491 /* Reset receiver */
492 rx &= 1;
493 if (mcbsp->pdata->has_ccr) {
494 w = MCBSP_READ_CACHE(mcbsp, RCCR);
495 w |= (rx ? RDISABLE : 0);
496 MCBSP_WRITE(mcbsp, RCCR, w);
497 }
498 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
499 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
500
501 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
502 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
503
504 if (idle) {
505 /* Reset the sample rate generator */
506 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
507 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
508 }
509
510 if (mcbsp->st_data)
511 omap_mcbsp_st_stop(mcbsp);
512 }
513
514 #define max_thres(m) (mcbsp->pdata->buffer_size)
515 #define valid_threshold(m, val) ((val) <= max_thres(m))
516 #define THRESHOLD_PROP_BUILDER(prop) \
517 static ssize_t prop##_show(struct device *dev, \
518 struct device_attribute *attr, char *buf) \
519 { \
520 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
521 \
522 return sprintf(buf, "%u\n", mcbsp->prop); \
523 } \
524 \
525 static ssize_t prop##_store(struct device *dev, \
526 struct device_attribute *attr, \
527 const char *buf, size_t size) \
528 { \
529 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
530 unsigned long val; \
531 int status; \
532 \
533 status = kstrtoul(buf, 0, &val); \
534 if (status) \
535 return status; \
536 \
537 if (!valid_threshold(mcbsp, val)) \
538 return -EDOM; \
539 \
540 mcbsp->prop = val; \
541 return size; \
542 } \
543 \
544 static DEVICE_ATTR_RW(prop)
545
546 THRESHOLD_PROP_BUILDER(max_tx_thres);
547 THRESHOLD_PROP_BUILDER(max_rx_thres);
548
549 static const char * const dma_op_modes[] = {
550 "element", "threshold",
551 };
552
dma_op_mode_show(struct device * dev,struct device_attribute * attr,char * buf)553 static ssize_t dma_op_mode_show(struct device *dev,
554 struct device_attribute *attr, char *buf)
555 {
556 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
557 int dma_op_mode, i = 0;
558 ssize_t len = 0;
559 const char * const *s;
560
561 dma_op_mode = mcbsp->dma_op_mode;
562
563 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
564 if (dma_op_mode == i)
565 len += sprintf(buf + len, "[%s] ", *s);
566 else
567 len += sprintf(buf + len, "%s ", *s);
568 }
569 len += sprintf(buf + len, "\n");
570
571 return len;
572 }
573
dma_op_mode_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t size)574 static ssize_t dma_op_mode_store(struct device *dev,
575 struct device_attribute *attr, const char *buf,
576 size_t size)
577 {
578 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
579 int i;
580
581 i = sysfs_match_string(dma_op_modes, buf);
582 if (i < 0)
583 return i;
584
585 spin_lock_irq(&mcbsp->lock);
586 if (!mcbsp->free) {
587 size = -EBUSY;
588 goto unlock;
589 }
590 mcbsp->dma_op_mode = i;
591
592 unlock:
593 spin_unlock_irq(&mcbsp->lock);
594
595 return size;
596 }
597
598 static DEVICE_ATTR_RW(dma_op_mode);
599
600 static const struct attribute *additional_attrs[] = {
601 &dev_attr_max_tx_thres.attr,
602 &dev_attr_max_rx_thres.attr,
603 &dev_attr_dma_op_mode.attr,
604 NULL,
605 };
606
607 static const struct attribute_group additional_attr_group = {
608 .attrs = (struct attribute **)additional_attrs,
609 };
610
611 /*
612 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
613 * 730 has only 2 McBSP, and both of them are MPU peripherals.
614 */
omap_mcbsp_init(struct platform_device * pdev)615 static int omap_mcbsp_init(struct platform_device *pdev)
616 {
617 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
618 struct resource *res;
619 int ret = 0;
620
621 spin_lock_init(&mcbsp->lock);
622 mcbsp->free = true;
623
624 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
625 if (!res)
626 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
627
628 mcbsp->io_base = devm_ioremap_resource(&pdev->dev, res);
629 if (IS_ERR(mcbsp->io_base))
630 return PTR_ERR(mcbsp->io_base);
631
632 mcbsp->phys_base = res->start;
633 mcbsp->reg_cache_size = resource_size(res);
634
635 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
636 if (!res)
637 mcbsp->phys_dma_base = mcbsp->phys_base;
638 else
639 mcbsp->phys_dma_base = res->start;
640
641 /*
642 * OMAP1, 2 uses two interrupt lines: TX, RX
643 * OMAP2430, OMAP3 SoC have combined IRQ line as well.
644 * OMAP4 and newer SoC only have the combined IRQ line.
645 * Use the combined IRQ if available since it gives better debugging
646 * possibilities.
647 */
648 mcbsp->irq = platform_get_irq_byname(pdev, "common");
649 if (mcbsp->irq == -ENXIO) {
650 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
651
652 if (mcbsp->tx_irq == -ENXIO) {
653 mcbsp->irq = platform_get_irq(pdev, 0);
654 mcbsp->tx_irq = 0;
655 } else {
656 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
657 mcbsp->irq = 0;
658 }
659 }
660
661 if (!pdev->dev.of_node) {
662 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
663 if (!res) {
664 dev_err(&pdev->dev, "invalid tx DMA channel\n");
665 return -ENODEV;
666 }
667 mcbsp->dma_req[0] = res->start;
668 mcbsp->dma_data[0].filter_data = &mcbsp->dma_req[0];
669
670 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
671 if (!res) {
672 dev_err(&pdev->dev, "invalid rx DMA channel\n");
673 return -ENODEV;
674 }
675 mcbsp->dma_req[1] = res->start;
676 mcbsp->dma_data[1].filter_data = &mcbsp->dma_req[1];
677 } else {
678 mcbsp->dma_data[0].filter_data = "tx";
679 mcbsp->dma_data[1].filter_data = "rx";
680 }
681
682 mcbsp->dma_data[0].addr = omap_mcbsp_dma_reg_params(mcbsp,
683 SNDRV_PCM_STREAM_PLAYBACK);
684 mcbsp->dma_data[1].addr = omap_mcbsp_dma_reg_params(mcbsp,
685 SNDRV_PCM_STREAM_CAPTURE);
686
687 mcbsp->fclk = devm_clk_get(&pdev->dev, "fck");
688 if (IS_ERR(mcbsp->fclk)) {
689 ret = PTR_ERR(mcbsp->fclk);
690 dev_err(mcbsp->dev, "unable to get fck: %d\n", ret);
691 return ret;
692 }
693
694 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
695 if (mcbsp->pdata->buffer_size) {
696 /*
697 * Initially configure the maximum thresholds to a safe value.
698 * The McBSP FIFO usage with these values should not go under
699 * 16 locations.
700 * If the whole FIFO without safety buffer is used, than there
701 * is a possibility that the DMA will be not able to push the
702 * new data on time, causing channel shifts in runtime.
703 */
704 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
705 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
706
707 ret = sysfs_create_group(&mcbsp->dev->kobj,
708 &additional_attr_group);
709 if (ret) {
710 dev_err(mcbsp->dev,
711 "Unable to create additional controls\n");
712 return ret;
713 }
714 }
715
716 ret = omap_mcbsp_st_init(pdev);
717 if (ret)
718 goto err_st;
719
720 return 0;
721
722 err_st:
723 if (mcbsp->pdata->buffer_size)
724 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
725 return ret;
726 }
727
728 /*
729 * Stream DMA parameters. DMA request line and port address are set runtime
730 * since they are different between OMAP1 and later OMAPs
731 */
omap_mcbsp_set_threshold(struct snd_pcm_substream * substream,unsigned int packet_size)732 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream,
733 unsigned int packet_size)
734 {
735 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
736 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
737 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
738 int words;
739
740 /* No need to proceed further if McBSP does not have FIFO */
741 if (mcbsp->pdata->buffer_size == 0)
742 return;
743
744 /*
745 * Configure McBSP threshold based on either:
746 * packet_size, when the sDMA is in packet mode, or based on the
747 * period size in THRESHOLD mode, otherwise use McBSP threshold = 1
748 * for mono streams.
749 */
750 if (packet_size)
751 words = packet_size;
752 else
753 words = 1;
754
755 /* Configure McBSP internal buffer usage */
756 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
757 omap_mcbsp_set_tx_threshold(mcbsp, words);
758 else
759 omap_mcbsp_set_rx_threshold(mcbsp, words);
760 }
761
omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)762 static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
763 struct snd_pcm_hw_rule *rule)
764 {
765 struct snd_interval *buffer_size = hw_param_interval(params,
766 SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
767 struct snd_interval *channels = hw_param_interval(params,
768 SNDRV_PCM_HW_PARAM_CHANNELS);
769 struct omap_mcbsp *mcbsp = rule->private;
770 struct snd_interval frames;
771 int size;
772
773 snd_interval_any(&frames);
774 size = mcbsp->pdata->buffer_size;
775
776 frames.min = size / channels->min;
777 frames.integer = 1;
778 return snd_interval_refine(buffer_size, &frames);
779 }
780
omap_mcbsp_dai_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)781 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
782 struct snd_soc_dai *cpu_dai)
783 {
784 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
785 int err = 0;
786
787 if (!snd_soc_dai_active(cpu_dai))
788 err = omap_mcbsp_request(mcbsp);
789
790 /*
791 * OMAP3 McBSP FIFO is word structured.
792 * McBSP2 has 1024 + 256 = 1280 word long buffer,
793 * McBSP1,3,4,5 has 128 word long buffer
794 * This means that the size of the FIFO depends on the sample format.
795 * For example on McBSP3:
796 * 16bit samples: size is 128 * 2 = 256 bytes
797 * 32bit samples: size is 128 * 4 = 512 bytes
798 * It is simpler to place constraint for buffer and period based on
799 * channels.
800 * McBSP3 as example again (16 or 32 bit samples):
801 * 1 channel (mono): size is 128 frames (128 words)
802 * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
803 * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
804 */
805 if (mcbsp->pdata->buffer_size) {
806 /*
807 * Rule for the buffer size. We should not allow
808 * smaller buffer than the FIFO size to avoid underruns.
809 * This applies only for the playback stream.
810 */
811 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
812 snd_pcm_hw_rule_add(substream->runtime, 0,
813 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
814 omap_mcbsp_hwrule_min_buffersize,
815 mcbsp,
816 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
817
818 /* Make sure, that the period size is always even */
819 snd_pcm_hw_constraint_step(substream->runtime, 0,
820 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
821 }
822
823 return err;
824 }
825
omap_mcbsp_dai_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)826 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
827 struct snd_soc_dai *cpu_dai)
828 {
829 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
830 int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
831 int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
832 int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK;
833
834 if (mcbsp->latency[stream2])
835 cpu_latency_qos_update_request(&mcbsp->pm_qos_req,
836 mcbsp->latency[stream2]);
837 else if (mcbsp->latency[stream1])
838 cpu_latency_qos_remove_request(&mcbsp->pm_qos_req);
839
840 mcbsp->latency[stream1] = 0;
841
842 if (!snd_soc_dai_active(cpu_dai)) {
843 omap_mcbsp_free(mcbsp);
844 mcbsp->configured = 0;
845 }
846 }
847
omap_mcbsp_dai_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)848 static int omap_mcbsp_dai_prepare(struct snd_pcm_substream *substream,
849 struct snd_soc_dai *cpu_dai)
850 {
851 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
852 struct pm_qos_request *pm_qos_req = &mcbsp->pm_qos_req;
853 int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
854 int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
855 int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK;
856 int latency = mcbsp->latency[stream2];
857
858 /* Prevent omap hardware from hitting off between FIFO fills */
859 if (!latency || mcbsp->latency[stream1] < latency)
860 latency = mcbsp->latency[stream1];
861
862 if (cpu_latency_qos_request_active(pm_qos_req))
863 cpu_latency_qos_update_request(pm_qos_req, latency);
864 else if (latency)
865 cpu_latency_qos_add_request(pm_qos_req, latency);
866
867 return 0;
868 }
869
omap_mcbsp_dai_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * cpu_dai)870 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
871 struct snd_soc_dai *cpu_dai)
872 {
873 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
874
875 switch (cmd) {
876 case SNDRV_PCM_TRIGGER_START:
877 case SNDRV_PCM_TRIGGER_RESUME:
878 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
879 mcbsp->active++;
880 omap_mcbsp_start(mcbsp, substream->stream);
881 break;
882
883 case SNDRV_PCM_TRIGGER_STOP:
884 case SNDRV_PCM_TRIGGER_SUSPEND:
885 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
886 omap_mcbsp_stop(mcbsp, substream->stream);
887 mcbsp->active--;
888 break;
889 default:
890 return -EINVAL;
891 }
892
893 return 0;
894 }
895
omap_mcbsp_dai_delay(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)896 static snd_pcm_sframes_t omap_mcbsp_dai_delay(
897 struct snd_pcm_substream *substream,
898 struct snd_soc_dai *dai)
899 {
900 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
901 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
902 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
903 u16 fifo_use;
904 snd_pcm_sframes_t delay;
905
906 /* No need to proceed further if McBSP does not have FIFO */
907 if (mcbsp->pdata->buffer_size == 0)
908 return 0;
909
910 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
911 fifo_use = omap_mcbsp_get_tx_delay(mcbsp);
912 else
913 fifo_use = omap_mcbsp_get_rx_delay(mcbsp);
914
915 /*
916 * Divide the used locations with the channel count to get the
917 * FIFO usage in samples (don't care about partial samples in the
918 * buffer).
919 */
920 delay = fifo_use / substream->runtime->channels;
921
922 return delay;
923 }
924
omap_mcbsp_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * cpu_dai)925 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
926 struct snd_pcm_hw_params *params,
927 struct snd_soc_dai *cpu_dai)
928 {
929 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
930 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
931 struct snd_dmaengine_dai_dma_data *dma_data;
932 int wlen, channels, wpf;
933 int pkt_size = 0;
934 unsigned int format, div, framesize, master;
935 unsigned int buffer_size = mcbsp->pdata->buffer_size;
936
937 dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
938 channels = params_channels(params);
939
940 switch (params_format(params)) {
941 case SNDRV_PCM_FORMAT_S16_LE:
942 wlen = 16;
943 break;
944 case SNDRV_PCM_FORMAT_S32_LE:
945 wlen = 32;
946 break;
947 default:
948 return -EINVAL;
949 }
950 if (buffer_size) {
951 int latency;
952
953 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
954 int period_words, max_thrsh;
955 int divider = 0;
956
957 period_words = params_period_bytes(params) / (wlen / 8);
958 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
959 max_thrsh = mcbsp->max_tx_thres;
960 else
961 max_thrsh = mcbsp->max_rx_thres;
962 /*
963 * Use sDMA packet mode if McBSP is in threshold mode:
964 * If period words less than the FIFO size the packet
965 * size is set to the number of period words, otherwise
966 * Look for the biggest threshold value which divides
967 * the period size evenly.
968 */
969 divider = period_words / max_thrsh;
970 if (period_words % max_thrsh)
971 divider++;
972 while (period_words % divider &&
973 divider < period_words)
974 divider++;
975 if (divider == period_words)
976 return -EINVAL;
977
978 pkt_size = period_words / divider;
979 } else if (channels > 1) {
980 /* Use packet mode for non mono streams */
981 pkt_size = channels;
982 }
983
984 latency = (buffer_size - pkt_size) / channels;
985 latency = latency * USEC_PER_SEC /
986 (params->rate_num / params->rate_den);
987 mcbsp->latency[substream->stream] = latency;
988
989 omap_mcbsp_set_threshold(substream, pkt_size);
990 }
991
992 dma_data->maxburst = pkt_size;
993
994 if (mcbsp->configured) {
995 /* McBSP already configured by another stream */
996 return 0;
997 }
998
999 regs->rcr2 &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7));
1000 regs->xcr2 &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7));
1001 regs->rcr1 &= ~(RFRLEN1(0x7f) | RWDLEN1(7));
1002 regs->xcr1 &= ~(XFRLEN1(0x7f) | XWDLEN1(7));
1003 format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
1004 wpf = channels;
1005 if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
1006 format == SND_SOC_DAIFMT_LEFT_J)) {
1007 /* Use dual-phase frames */
1008 regs->rcr2 |= RPHASE;
1009 regs->xcr2 |= XPHASE;
1010 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
1011 wpf--;
1012 regs->rcr2 |= RFRLEN2(wpf - 1);
1013 regs->xcr2 |= XFRLEN2(wpf - 1);
1014 }
1015
1016 regs->rcr1 |= RFRLEN1(wpf - 1);
1017 regs->xcr1 |= XFRLEN1(wpf - 1);
1018
1019 switch (params_format(params)) {
1020 case SNDRV_PCM_FORMAT_S16_LE:
1021 /* Set word lengths */
1022 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16);
1023 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16);
1024 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16);
1025 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16);
1026 break;
1027 case SNDRV_PCM_FORMAT_S32_LE:
1028 /* Set word lengths */
1029 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_32);
1030 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_32);
1031 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_32);
1032 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_32);
1033 break;
1034 default:
1035 /* Unsupported PCM format */
1036 return -EINVAL;
1037 }
1038
1039 /* In McBSP master modes, FRAME (i.e. sample rate) is generated
1040 * by _counting_ BCLKs. Calculate frame size in BCLKs */
1041 master = mcbsp->fmt & SND_SOC_DAIFMT_MASTER_MASK;
1042 if (master == SND_SOC_DAIFMT_CBS_CFS) {
1043 div = mcbsp->clk_div ? mcbsp->clk_div : 1;
1044 framesize = (mcbsp->in_freq / div) / params_rate(params);
1045
1046 if (framesize < wlen * channels) {
1047 printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
1048 "channels\n", __func__);
1049 return -EINVAL;
1050 }
1051 } else
1052 framesize = wlen * channels;
1053
1054 /* Set FS period and length in terms of bit clock periods */
1055 regs->srgr2 &= ~FPER(0xfff);
1056 regs->srgr1 &= ~FWID(0xff);
1057 switch (format) {
1058 case SND_SOC_DAIFMT_I2S:
1059 case SND_SOC_DAIFMT_LEFT_J:
1060 regs->srgr2 |= FPER(framesize - 1);
1061 regs->srgr1 |= FWID((framesize >> 1) - 1);
1062 break;
1063 case SND_SOC_DAIFMT_DSP_A:
1064 case SND_SOC_DAIFMT_DSP_B:
1065 regs->srgr2 |= FPER(framesize - 1);
1066 regs->srgr1 |= FWID(0);
1067 break;
1068 }
1069
1070 omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs);
1071 mcbsp->wlen = wlen;
1072 mcbsp->configured = 1;
1073
1074 return 0;
1075 }
1076
1077 /*
1078 * This must be called before _set_clkdiv and _set_sysclk since McBSP register
1079 * cache is initialized here
1080 */
omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)1081 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
1082 unsigned int fmt)
1083 {
1084 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1085 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1086 bool inv_fs = false;
1087
1088 if (mcbsp->configured)
1089 return 0;
1090
1091 mcbsp->fmt = fmt;
1092 memset(regs, 0, sizeof(*regs));
1093 /* Generic McBSP register settings */
1094 regs->spcr2 |= XINTM(3) | FREE;
1095 regs->spcr1 |= RINTM(3);
1096 /* RFIG and XFIG are not defined in 2430 and on OMAP3+ */
1097 if (!mcbsp->pdata->has_ccr) {
1098 regs->rcr2 |= RFIG;
1099 regs->xcr2 |= XFIG;
1100 }
1101
1102 /* Configure XCCR/RCCR only for revisions which have ccr registers */
1103 if (mcbsp->pdata->has_ccr) {
1104 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
1105 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
1106 }
1107
1108 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1109 case SND_SOC_DAIFMT_I2S:
1110 /* 1-bit data delay */
1111 regs->rcr2 |= RDATDLY(1);
1112 regs->xcr2 |= XDATDLY(1);
1113 break;
1114 case SND_SOC_DAIFMT_LEFT_J:
1115 /* 0-bit data delay */
1116 regs->rcr2 |= RDATDLY(0);
1117 regs->xcr2 |= XDATDLY(0);
1118 regs->spcr1 |= RJUST(2);
1119 /* Invert FS polarity configuration */
1120 inv_fs = true;
1121 break;
1122 case SND_SOC_DAIFMT_DSP_A:
1123 /* 1-bit data delay */
1124 regs->rcr2 |= RDATDLY(1);
1125 regs->xcr2 |= XDATDLY(1);
1126 /* Invert FS polarity configuration */
1127 inv_fs = true;
1128 break;
1129 case SND_SOC_DAIFMT_DSP_B:
1130 /* 0-bit data delay */
1131 regs->rcr2 |= RDATDLY(0);
1132 regs->xcr2 |= XDATDLY(0);
1133 /* Invert FS polarity configuration */
1134 inv_fs = true;
1135 break;
1136 default:
1137 /* Unsupported data format */
1138 return -EINVAL;
1139 }
1140
1141 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1142 case SND_SOC_DAIFMT_CBS_CFS:
1143 /* McBSP master. Set FS and bit clocks as outputs */
1144 regs->pcr0 |= FSXM | FSRM |
1145 CLKXM | CLKRM;
1146 /* Sample rate generator drives the FS */
1147 regs->srgr2 |= FSGM;
1148 break;
1149 case SND_SOC_DAIFMT_CBM_CFS:
1150 /* McBSP slave. FS clock as output */
1151 regs->srgr2 |= FSGM;
1152 regs->pcr0 |= FSXM | FSRM;
1153 break;
1154 case SND_SOC_DAIFMT_CBM_CFM:
1155 /* McBSP slave */
1156 break;
1157 default:
1158 /* Unsupported master/slave configuration */
1159 return -EINVAL;
1160 }
1161
1162 /* Set bit clock (CLKX/CLKR) and FS polarities */
1163 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1164 case SND_SOC_DAIFMT_NB_NF:
1165 /*
1166 * Normal BCLK + FS.
1167 * FS active low. TX data driven on falling edge of bit clock
1168 * and RX data sampled on rising edge of bit clock.
1169 */
1170 regs->pcr0 |= FSXP | FSRP |
1171 CLKXP | CLKRP;
1172 break;
1173 case SND_SOC_DAIFMT_NB_IF:
1174 regs->pcr0 |= CLKXP | CLKRP;
1175 break;
1176 case SND_SOC_DAIFMT_IB_NF:
1177 regs->pcr0 |= FSXP | FSRP;
1178 break;
1179 case SND_SOC_DAIFMT_IB_IF:
1180 break;
1181 default:
1182 return -EINVAL;
1183 }
1184 if (inv_fs)
1185 regs->pcr0 ^= FSXP | FSRP;
1186
1187 return 0;
1188 }
1189
omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai * cpu_dai,int div_id,int div)1190 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
1191 int div_id, int div)
1192 {
1193 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1194 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1195
1196 if (div_id != OMAP_MCBSP_CLKGDV)
1197 return -ENODEV;
1198
1199 mcbsp->clk_div = div;
1200 regs->srgr1 &= ~CLKGDV(0xff);
1201 regs->srgr1 |= CLKGDV(div - 1);
1202
1203 return 0;
1204 }
1205
omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai * cpu_dai,int clk_id,unsigned int freq,int dir)1206 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
1207 int clk_id, unsigned int freq,
1208 int dir)
1209 {
1210 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1211 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1212 int err = 0;
1213
1214 if (mcbsp->active) {
1215 if (freq == mcbsp->in_freq)
1216 return 0;
1217 else
1218 return -EBUSY;
1219 }
1220
1221 mcbsp->in_freq = freq;
1222 regs->srgr2 &= ~CLKSM;
1223 regs->pcr0 &= ~SCLKME;
1224
1225 switch (clk_id) {
1226 case OMAP_MCBSP_SYSCLK_CLK:
1227 regs->srgr2 |= CLKSM;
1228 break;
1229 case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
1230 if (mcbsp_omap1()) {
1231 err = -EINVAL;
1232 break;
1233 }
1234 err = omap2_mcbsp_set_clks_src(mcbsp,
1235 MCBSP_CLKS_PRCM_SRC);
1236 break;
1237 case OMAP_MCBSP_SYSCLK_CLKS_EXT:
1238 if (mcbsp_omap1()) {
1239 err = 0;
1240 break;
1241 }
1242 err = omap2_mcbsp_set_clks_src(mcbsp,
1243 MCBSP_CLKS_PAD_SRC);
1244 break;
1245
1246 case OMAP_MCBSP_SYSCLK_CLKX_EXT:
1247 regs->srgr2 |= CLKSM;
1248 regs->pcr0 |= SCLKME;
1249 /*
1250 * If McBSP is master but yet the CLKX/CLKR pin drives the SRG,
1251 * disable output on those pins. This enables to inject the
1252 * reference clock through CLKX/CLKR. For this to work
1253 * set_dai_sysclk() _needs_ to be called after set_dai_fmt().
1254 */
1255 regs->pcr0 &= ~CLKXM;
1256 break;
1257 case OMAP_MCBSP_SYSCLK_CLKR_EXT:
1258 regs->pcr0 |= SCLKME;
1259 /* Disable ouput on CLKR pin in master mode */
1260 regs->pcr0 &= ~CLKRM;
1261 break;
1262 default:
1263 err = -ENODEV;
1264 }
1265
1266 return err;
1267 }
1268
1269 static const struct snd_soc_dai_ops mcbsp_dai_ops = {
1270 .startup = omap_mcbsp_dai_startup,
1271 .shutdown = omap_mcbsp_dai_shutdown,
1272 .prepare = omap_mcbsp_dai_prepare,
1273 .trigger = omap_mcbsp_dai_trigger,
1274 .delay = omap_mcbsp_dai_delay,
1275 .hw_params = omap_mcbsp_dai_hw_params,
1276 .set_fmt = omap_mcbsp_dai_set_dai_fmt,
1277 .set_clkdiv = omap_mcbsp_dai_set_clkdiv,
1278 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
1279 };
1280
omap_mcbsp_probe(struct snd_soc_dai * dai)1281 static int omap_mcbsp_probe(struct snd_soc_dai *dai)
1282 {
1283 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
1284
1285 pm_runtime_enable(mcbsp->dev);
1286
1287 snd_soc_dai_init_dma_data(dai,
1288 &mcbsp->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
1289 &mcbsp->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
1290
1291 return 0;
1292 }
1293
omap_mcbsp_remove(struct snd_soc_dai * dai)1294 static int omap_mcbsp_remove(struct snd_soc_dai *dai)
1295 {
1296 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
1297
1298 pm_runtime_disable(mcbsp->dev);
1299
1300 return 0;
1301 }
1302
1303 static struct snd_soc_dai_driver omap_mcbsp_dai = {
1304 .probe = omap_mcbsp_probe,
1305 .remove = omap_mcbsp_remove,
1306 .playback = {
1307 .channels_min = 1,
1308 .channels_max = 16,
1309 .rates = OMAP_MCBSP_RATES,
1310 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
1311 },
1312 .capture = {
1313 .channels_min = 1,
1314 .channels_max = 16,
1315 .rates = OMAP_MCBSP_RATES,
1316 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
1317 },
1318 .ops = &mcbsp_dai_ops,
1319 };
1320
1321 static const struct snd_soc_component_driver omap_mcbsp_component = {
1322 .name = "omap-mcbsp",
1323 };
1324
1325 static struct omap_mcbsp_platform_data omap2420_pdata = {
1326 .reg_step = 4,
1327 .reg_size = 2,
1328 };
1329
1330 static struct omap_mcbsp_platform_data omap2430_pdata = {
1331 .reg_step = 4,
1332 .reg_size = 4,
1333 .has_ccr = true,
1334 };
1335
1336 static struct omap_mcbsp_platform_data omap3_pdata = {
1337 .reg_step = 4,
1338 .reg_size = 4,
1339 .has_ccr = true,
1340 .has_wakeup = true,
1341 };
1342
1343 static struct omap_mcbsp_platform_data omap4_pdata = {
1344 .reg_step = 4,
1345 .reg_size = 4,
1346 .has_ccr = true,
1347 .has_wakeup = true,
1348 };
1349
1350 static const struct of_device_id omap_mcbsp_of_match[] = {
1351 {
1352 .compatible = "ti,omap2420-mcbsp",
1353 .data = &omap2420_pdata,
1354 },
1355 {
1356 .compatible = "ti,omap2430-mcbsp",
1357 .data = &omap2430_pdata,
1358 },
1359 {
1360 .compatible = "ti,omap3-mcbsp",
1361 .data = &omap3_pdata,
1362 },
1363 {
1364 .compatible = "ti,omap4-mcbsp",
1365 .data = &omap4_pdata,
1366 },
1367 { },
1368 };
1369 MODULE_DEVICE_TABLE(of, omap_mcbsp_of_match);
1370
asoc_mcbsp_probe(struct platform_device * pdev)1371 static int asoc_mcbsp_probe(struct platform_device *pdev)
1372 {
1373 struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev);
1374 struct omap_mcbsp *mcbsp;
1375 const struct of_device_id *match;
1376 int ret;
1377
1378 match = of_match_device(omap_mcbsp_of_match, &pdev->dev);
1379 if (match) {
1380 struct device_node *node = pdev->dev.of_node;
1381 struct omap_mcbsp_platform_data *pdata_quirk = pdata;
1382 int buffer_size;
1383
1384 pdata = devm_kzalloc(&pdev->dev,
1385 sizeof(struct omap_mcbsp_platform_data),
1386 GFP_KERNEL);
1387 if (!pdata)
1388 return -ENOMEM;
1389
1390 memcpy(pdata, match->data, sizeof(*pdata));
1391 if (!of_property_read_u32(node, "ti,buffer-size", &buffer_size))
1392 pdata->buffer_size = buffer_size;
1393 if (pdata_quirk)
1394 pdata->force_ick_on = pdata_quirk->force_ick_on;
1395 } else if (!pdata) {
1396 dev_err(&pdev->dev, "missing platform data.\n");
1397 return -EINVAL;
1398 }
1399 mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL);
1400 if (!mcbsp)
1401 return -ENOMEM;
1402
1403 mcbsp->id = pdev->id;
1404 mcbsp->pdata = pdata;
1405 mcbsp->dev = &pdev->dev;
1406 platform_set_drvdata(pdev, mcbsp);
1407
1408 ret = omap_mcbsp_init(pdev);
1409 if (ret)
1410 return ret;
1411
1412 if (mcbsp->pdata->reg_size == 2) {
1413 omap_mcbsp_dai.playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
1414 omap_mcbsp_dai.capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
1415 }
1416
1417 ret = devm_snd_soc_register_component(&pdev->dev,
1418 &omap_mcbsp_component,
1419 &omap_mcbsp_dai, 1);
1420 if (ret)
1421 return ret;
1422
1423 return sdma_pcm_platform_register(&pdev->dev, "tx", "rx");
1424 }
1425
asoc_mcbsp_remove(struct platform_device * pdev)1426 static int asoc_mcbsp_remove(struct platform_device *pdev)
1427 {
1428 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1429
1430 if (mcbsp->pdata->ops && mcbsp->pdata->ops->free)
1431 mcbsp->pdata->ops->free(mcbsp->id);
1432
1433 if (cpu_latency_qos_request_active(&mcbsp->pm_qos_req))
1434 cpu_latency_qos_remove_request(&mcbsp->pm_qos_req);
1435
1436 if (mcbsp->pdata->buffer_size)
1437 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
1438
1439 omap_mcbsp_st_cleanup(pdev);
1440
1441 return 0;
1442 }
1443
1444 static struct platform_driver asoc_mcbsp_driver = {
1445 .driver = {
1446 .name = "omap-mcbsp",
1447 .of_match_table = omap_mcbsp_of_match,
1448 },
1449
1450 .probe = asoc_mcbsp_probe,
1451 .remove = asoc_mcbsp_remove,
1452 };
1453
1454 module_platform_driver(asoc_mcbsp_driver);
1455
1456 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>");
1457 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
1458 MODULE_LICENSE("GPL");
1459 MODULE_ALIAS("platform:omap-mcbsp");
1460