1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * intel_pt_decoder.h: Intel Processor Trace support
4 * Copyright (c) 2013-2014, Intel Corporation.
5 */
6
7 #ifndef INCLUDE__INTEL_PT_DECODER_H__
8 #define INCLUDE__INTEL_PT_DECODER_H__
9
10 #include <stdint.h>
11 #include <stddef.h>
12 #include <stdbool.h>
13
14 #include <linux/rbtree.h>
15
16 #include "intel-pt-insn-decoder.h"
17
18 #define INTEL_PT_IN_TX (1 << 0)
19 #define INTEL_PT_ABORT_TX (1 << 1)
20 #define INTEL_PT_ASYNC (1 << 2)
21 #define INTEL_PT_FUP_IP (1 << 3)
22 #define INTEL_PT_SAMPLE_IPC (1 << 4)
23
24 enum intel_pt_sample_type {
25 INTEL_PT_BRANCH = 1 << 0,
26 INTEL_PT_INSTRUCTION = 1 << 1,
27 INTEL_PT_TRANSACTION = 1 << 2,
28 INTEL_PT_PTW = 1 << 3,
29 INTEL_PT_MWAIT_OP = 1 << 4,
30 INTEL_PT_PWR_ENTRY = 1 << 5,
31 INTEL_PT_EX_STOP = 1 << 6,
32 INTEL_PT_PWR_EXIT = 1 << 7,
33 INTEL_PT_CBR_CHG = 1 << 8,
34 INTEL_PT_TRACE_BEGIN = 1 << 9,
35 INTEL_PT_TRACE_END = 1 << 10,
36 INTEL_PT_BLK_ITEMS = 1 << 11,
37 INTEL_PT_PSB_EVT = 1 << 12,
38 };
39
40 enum intel_pt_period_type {
41 INTEL_PT_PERIOD_NONE,
42 INTEL_PT_PERIOD_INSTRUCTIONS,
43 INTEL_PT_PERIOD_TICKS,
44 INTEL_PT_PERIOD_MTC,
45 };
46
47 enum {
48 INTEL_PT_ERR_NOMEM = 1,
49 INTEL_PT_ERR_INTERN,
50 INTEL_PT_ERR_BADPKT,
51 INTEL_PT_ERR_NODATA,
52 INTEL_PT_ERR_NOINSN,
53 INTEL_PT_ERR_MISMAT,
54 INTEL_PT_ERR_OVR,
55 INTEL_PT_ERR_LOST,
56 INTEL_PT_ERR_UNK,
57 INTEL_PT_ERR_NELOOP,
58 INTEL_PT_ERR_EPTW,
59 INTEL_PT_ERR_MAX,
60 };
61
62 enum intel_pt_param_flags {
63 /*
64 * FUP packet can contain next linear instruction pointer instead of
65 * current linear instruction pointer.
66 */
67 INTEL_PT_FUP_WITH_NLIP = 1 << 0,
68 };
69
70 enum intel_pt_blk_type {
71 INTEL_PT_GP_REGS = 1,
72 INTEL_PT_PEBS_BASIC = 4,
73 INTEL_PT_PEBS_MEM = 5,
74 INTEL_PT_LBR_0 = 8,
75 INTEL_PT_LBR_1 = 9,
76 INTEL_PT_LBR_2 = 10,
77 INTEL_PT_XMM = 16,
78 INTEL_PT_BLK_TYPE_MAX
79 };
80
81 /*
82 * The block type numbers are not sequential but here they are given sequential
83 * positions to avoid wasting space for array placement.
84 */
85 enum intel_pt_blk_type_pos {
86 INTEL_PT_GP_REGS_POS,
87 INTEL_PT_PEBS_BASIC_POS,
88 INTEL_PT_PEBS_MEM_POS,
89 INTEL_PT_LBR_0_POS,
90 INTEL_PT_LBR_1_POS,
91 INTEL_PT_LBR_2_POS,
92 INTEL_PT_XMM_POS,
93 INTEL_PT_BLK_TYPE_CNT
94 };
95
96 /* Get the array position for a block type */
intel_pt_blk_type_pos(enum intel_pt_blk_type blk_type)97 static inline int intel_pt_blk_type_pos(enum intel_pt_blk_type blk_type)
98 {
99 #define BLK_TYPE(bt) [INTEL_PT_##bt] = INTEL_PT_##bt##_POS + 1
100 const int map[INTEL_PT_BLK_TYPE_MAX] = {
101 BLK_TYPE(GP_REGS),
102 BLK_TYPE(PEBS_BASIC),
103 BLK_TYPE(PEBS_MEM),
104 BLK_TYPE(LBR_0),
105 BLK_TYPE(LBR_1),
106 BLK_TYPE(LBR_2),
107 BLK_TYPE(XMM),
108 };
109 #undef BLK_TYPE
110
111 return blk_type < INTEL_PT_BLK_TYPE_MAX ? map[blk_type] - 1 : -1;
112 }
113
114 #define INTEL_PT_BLK_ITEM_ID_CNT 32
115
116 /*
117 * Use unions so that the block items can be accessed by name or by array index.
118 * There is an array of 32-bit masks for each block type, which indicate which
119 * values are present. Then arrays of 32 64-bit values for each block type.
120 */
121 struct intel_pt_blk_items {
122 union {
123 uint32_t mask[INTEL_PT_BLK_TYPE_CNT];
124 struct {
125 uint32_t has_rflags:1;
126 uint32_t has_rip:1;
127 uint32_t has_rax:1;
128 uint32_t has_rcx:1;
129 uint32_t has_rdx:1;
130 uint32_t has_rbx:1;
131 uint32_t has_rsp:1;
132 uint32_t has_rbp:1;
133 uint32_t has_rsi:1;
134 uint32_t has_rdi:1;
135 uint32_t has_r8:1;
136 uint32_t has_r9:1;
137 uint32_t has_r10:1;
138 uint32_t has_r11:1;
139 uint32_t has_r12:1;
140 uint32_t has_r13:1;
141 uint32_t has_r14:1;
142 uint32_t has_r15:1;
143 uint32_t has_unused_0:14;
144 uint32_t has_ip:1;
145 uint32_t has_applicable_counters:1;
146 uint32_t has_timestamp:1;
147 uint32_t has_unused_1:29;
148 uint32_t has_mem_access_address:1;
149 uint32_t has_mem_aux_info:1;
150 uint32_t has_mem_access_latency:1;
151 uint32_t has_tsx_aux_info:1;
152 uint32_t has_unused_2:28;
153 uint32_t has_lbr_0;
154 uint32_t has_lbr_1;
155 uint32_t has_lbr_2;
156 uint32_t has_xmm;
157 };
158 };
159 union {
160 uint64_t val[INTEL_PT_BLK_TYPE_CNT][INTEL_PT_BLK_ITEM_ID_CNT];
161 struct {
162 struct {
163 uint64_t rflags;
164 uint64_t rip;
165 uint64_t rax;
166 uint64_t rcx;
167 uint64_t rdx;
168 uint64_t rbx;
169 uint64_t rsp;
170 uint64_t rbp;
171 uint64_t rsi;
172 uint64_t rdi;
173 uint64_t r8;
174 uint64_t r9;
175 uint64_t r10;
176 uint64_t r11;
177 uint64_t r12;
178 uint64_t r13;
179 uint64_t r14;
180 uint64_t r15;
181 uint64_t unused_0[INTEL_PT_BLK_ITEM_ID_CNT - 18];
182 };
183 struct {
184 uint64_t ip;
185 uint64_t applicable_counters;
186 uint64_t timestamp;
187 uint64_t unused_1[INTEL_PT_BLK_ITEM_ID_CNT - 3];
188 };
189 struct {
190 uint64_t mem_access_address;
191 uint64_t mem_aux_info;
192 uint64_t mem_access_latency;
193 uint64_t tsx_aux_info;
194 uint64_t unused_2[INTEL_PT_BLK_ITEM_ID_CNT - 4];
195 };
196 uint64_t lbr_0[INTEL_PT_BLK_ITEM_ID_CNT];
197 uint64_t lbr_1[INTEL_PT_BLK_ITEM_ID_CNT];
198 uint64_t lbr_2[INTEL_PT_BLK_ITEM_ID_CNT];
199 uint64_t xmm[INTEL_PT_BLK_ITEM_ID_CNT];
200 };
201 };
202 bool is_32_bit;
203 };
204
205 struct intel_pt_vmcs_info {
206 struct rb_node rb_node;
207 uint64_t vmcs;
208 uint64_t tsc_offset;
209 bool reliable;
210 bool error_printed;
211 };
212
213 struct intel_pt_state {
214 enum intel_pt_sample_type type;
215 bool from_nr;
216 bool to_nr;
217 int err;
218 uint64_t from_ip;
219 uint64_t to_ip;
220 uint64_t tot_insn_cnt;
221 uint64_t tot_cyc_cnt;
222 uint64_t timestamp;
223 uint64_t est_timestamp;
224 uint64_t trace_nr;
225 uint64_t ptw_payload;
226 uint64_t mwait_payload;
227 uint64_t pwre_payload;
228 uint64_t pwrx_payload;
229 uint64_t cbr_payload;
230 uint64_t psb_offset;
231 uint32_t cbr;
232 uint32_t flags;
233 enum intel_pt_insn_op insn_op;
234 int insn_len;
235 char insn[INTEL_PT_INSN_BUF_SZ];
236 struct intel_pt_blk_items items;
237 };
238
239 struct intel_pt_insn;
240
241 struct intel_pt_buffer {
242 const unsigned char *buf;
243 size_t len;
244 bool consecutive;
245 uint64_t ref_timestamp;
246 uint64_t trace_nr;
247 };
248
249 typedef int (*intel_pt_lookahead_cb_t)(struct intel_pt_buffer *, void *);
250
251 struct intel_pt_params {
252 int (*get_trace)(struct intel_pt_buffer *buffer, void *data);
253 int (*walk_insn)(struct intel_pt_insn *intel_pt_insn,
254 uint64_t *insn_cnt_ptr, uint64_t *ip, uint64_t to_ip,
255 uint64_t max_insn_cnt, void *data);
256 bool (*pgd_ip)(uint64_t ip, void *data);
257 int (*lookahead)(void *data, intel_pt_lookahead_cb_t cb, void *cb_data);
258 struct intel_pt_vmcs_info *(*findnew_vmcs_info)(void *data, uint64_t vmcs);
259 void *data;
260 bool return_compression;
261 bool branch_enable;
262 bool vm_time_correlation;
263 bool vm_tm_corr_dry_run;
264 uint64_t first_timestamp;
265 uint64_t ctl;
266 uint64_t period;
267 enum intel_pt_period_type period_type;
268 unsigned max_non_turbo_ratio;
269 unsigned int mtc_period;
270 uint32_t tsc_ctc_ratio_n;
271 uint32_t tsc_ctc_ratio_d;
272 enum intel_pt_param_flags flags;
273 unsigned int quick;
274 int max_loops;
275 };
276
277 struct intel_pt_decoder;
278
279 struct intel_pt_decoder *intel_pt_decoder_new(struct intel_pt_params *params);
280 void intel_pt_decoder_free(struct intel_pt_decoder *decoder);
281
282 const struct intel_pt_state *intel_pt_decode(struct intel_pt_decoder *decoder);
283
284 int intel_pt_fast_forward(struct intel_pt_decoder *decoder, uint64_t timestamp);
285
286 unsigned char *intel_pt_find_overlap(unsigned char *buf_a, size_t len_a,
287 unsigned char *buf_b, size_t len_b,
288 bool have_tsc, bool *consecutive,
289 bool ooo_tsc);
290
291 int intel_pt__strerror(int code, char *buf, size_t buflen);
292
293 void intel_pt_set_first_timestamp(struct intel_pt_decoder *decoder,
294 uint64_t first_timestamp);
295
296 #endif
297