133 	struct geni_se se;  member
218 	port->se.base = uport->membase;  in qcom_geni_serial_request_port()
506 		geni_se_cancel_m_cmd(&port->se);  in qcom_geni_serial_console_write()
509 			geni_se_abort_m_cmd(&port->se);  in qcom_geni_serial_console_write()
642 	geni_se_cancel_m_cmd(&port->se);  in qcom_geni_serial_stop_tx()
645 		geni_se_abort_m_cmd(&port->se);  in qcom_geni_serial_stop_tx()
663 	geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);  in qcom_geni_serial_start_rx()
694 	geni_se_cancel_s_cmd(&port->se);  in qcom_geni_serial_stop_rx()
888 	port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);  in setup_fifos()
889 	port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);  in setup_fifos()
890 	port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);  in setup_fifos()
919 	proto = geni_se_read_proto(&port->se);  in qcom_geni_serial_port_setup()
952 	geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,  in qcom_geni_serial_port_setup()
954 	geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);  in qcom_geni_serial_port_setup()
955 	geni_se_select_mode(&port->se, GENI_SE_FIFO);  in qcom_geni_serial_port_setup()
1029 	ver = geni_se_get_qup_hw_version(&port->se);  in qcom_geni_serial_set_termios()
1049 	port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core;  in qcom_geni_serial_set_termios()
1050 	port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud);  in qcom_geni_serial_set_termios()
1051 	geni_icc_set_bw(&port->se);  in qcom_geni_serial_set_termios()
1183 static void __init qcom_geni_serial_enable_early_read(struct geni_se *se,  in qcom_geni_serial_enable_early_read()  argument
1186 	geni_se_setup_s_cmd(se, UART_START_READ, 0);  in qcom_geni_serial_enable_early_read()
1190 static inline void qcom_geni_serial_enable_early_read(struct geni_se *se,  in qcom_geni_serial_enable_early_read()  argument
1206 	struct geni_se se;  in qcom_geni_serial_earlycon_setup()  local
1213 	memset(&se, 0, sizeof(se));  in qcom_geni_serial_earlycon_setup()
1214 	se.base = uport->membase;  in qcom_geni_serial_earlycon_setup()
1215 	if (geni_se_read_proto(&se) != GENI_SE_UART)  in qcom_geni_serial_earlycon_setup()
1230 	geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,  in qcom_geni_serial_earlycon_setup()
1232 	geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);  in qcom_geni_serial_earlycon_setup()
1233 	geni_se_select_mode(&se, GENI_SE_FIFO);  in qcom_geni_serial_earlycon_setup()
1245 	qcom_geni_serial_enable_early_read(&se, dev->con);  in qcom_geni_serial_earlycon_setup()
1307 		geni_icc_enable(&port->se);  in qcom_geni_serial_pm()
1310 		geni_se_resources_on(&port->se);  in qcom_geni_serial_pm()
1313 		geni_se_resources_off(&port->se);  in qcom_geni_serial_pm()
1315 		geni_icc_disable(&port->se);  in qcom_geni_serial_pm()
1403 	port->se.dev = &pdev->dev;  in qcom_geni_serial_probe()
1404 	port->se.wrapper = dev_get_drvdata(pdev->dev.parent);  in qcom_geni_serial_probe()
1405 	port->se.clk = devm_clk_get(&pdev->dev, "se");  in qcom_geni_serial_probe()
1406 	if (IS_ERR(port->se.clk)) {  in qcom_geni_serial_probe()
1407 		ret = PTR_ERR(port->se.clk);  in qcom_geni_serial_probe()
1428 	ret = geni_icc_get(&port->se, NULL);  in qcom_geni_serial_probe()
1431 	port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;  in qcom_geni_serial_probe()
1432 	port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;  in qcom_geni_serial_probe()
1435 	ret = geni_icc_set_bw(&port->se);  in qcom_geni_serial_probe()
1539 		geni_icc_set_tag(&port->se, 0x3);  in qcom_geni_serial_sys_suspend()
1540 		geni_icc_set_bw(&port->se);  in qcom_geni_serial_sys_suspend()
1563 		geni_icc_set_tag(&port->se, 0x7);  in qcom_geni_serial_sys_resume()
1564 		geni_icc_set_bw(&port->se);  in qcom_geni_serial_sys_resume()