| /drivers/media/platform/s3c-camif/ |
| D | camif-regs.h | 65 #define CIGCTRL_IRQ_CLR(id) BIT(19 - (id)) argument
71 #define S3C_CAMIF_REG_CIYSA(id, n) (0x18 + (id) * 0x54 + (n) * 4) argument
73 #define S3C_CAMIF_REG_CICBSA(id, n) (0x28 + (id) * 0x54 + (n) * 4) argument
75 #define S3C_CAMIF_REG_CICRSA(id, n) (0x38 + (id) * 0x54 + (n) * 4) argument
78 #define S3C_CAMIF_REG_CITRGFMT(id, _offs) (0x48 + (id) * (0x34 + (_offs))) argument
98 #define S3C_CAMIF_REG_CICTRL(id, _offs) (0x4c + (id) * (0x34 + (_offs))) argument
111 #define S3C_CAMIF_REG_CISCPRERATIO(id, _offs) (0x50 + (id) * (0x34 + (_offs))) argument
114 #define S3C_CAMIF_REG_CISCPREDST(id, _offs) (0x54 + (id) * (0x34 + (_offs))) argument
117 #define S3C_CAMIF_REG_CISCCTRL(id, _offs) (0x58 + (id) * (0x34 + (_offs))) argument
147 #define S3C_CAMIF_REG_CITAREA(id, _offs) (0x5c + (id) * (0x34 + (_offs))) argument
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| /drivers/gpu/drm/msm/dsi/ |
| D | dsi_manager.c | 33 #define IS_MASTER_DSI_LINK(id) (msm_dsim_glb.master_dsi_link_id == id) argument
35 static inline struct msm_dsi *dsi_mgr_get_dsi(int id) in dsi_mgr_get_dsi()
40 static inline struct msm_dsi *dsi_mgr_get_other_dsi(int id) in dsi_mgr_get_other_dsi()
45 static int dsi_mgr_parse_of(struct device_node *np, int id) in dsi_mgr_parse_of()
66 static int dsi_mgr_setup_components(int id) in dsi_mgr_setup_components()
131 dsi_mgr_phy_enable(int id, in dsi_mgr_phy_enable()
172 static void dsi_mgr_phy_disable(int id) in dsi_mgr_phy_disable()
195 int id; member
200 int id; member
218 static int msm_dsi_manager_panel_init(struct drm_connector *conn, u8 id) in msm_dsi_manager_panel_init()
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| /drivers/reset/ |
| D | reset-uniphier.c | 16 unsigned int id; member
143 #define UNIPHIER_MIO_RESET_SD(id, ch) \ argument
146 #define UNIPHIER_MIO_RESET_SD_BRIDGE(id, ch) \ argument
149 #define UNIPHIER_MIO_RESET_EMMC_HW_RESET(id, ch) \ argument
152 #define UNIPHIER_MIO_RESET_USB2(id, ch) \ argument
155 #define UNIPHIER_MIO_RESET_USB2_BRIDGE(id, ch) \ argument
158 #define UNIPHIER_MIO_RESET_DMAC(id) \ argument
187 #define UNIPHIER_PERI_RESET_UART(id, ch) \ argument
190 #define UNIPHIER_PERI_RESET_I2C(id, ch) \ argument
193 #define UNIPHIER_PERI_RESET_FI2C(id, ch) \ argument
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| D | reset-imx7.c | 49 unsigned long id, unsigned int value) in imx7_reset_update()
92 unsigned long id, bool assert) in imx7_reset_set()
117 unsigned long id) in imx7_reset_assert()
123 unsigned long id) in imx7_reset_deassert()
220 unsigned long id, bool assert) in imx8mq_reset_set()
253 unsigned long id) in imx8mq_reset_assert()
259 unsigned long id) in imx8mq_reset_deassert()
315 unsigned long id, bool assert) in imx8mp_reset_set()
341 unsigned long id) in imx8mp_reset_assert()
347 unsigned long id) in imx8mp_reset_deassert()
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| /drivers/gpu/host1x/hw/ |
| D | hw_host1x04_sync.h | 44 static inline u32 host1x_sync_syncpt_r(unsigned int id) in host1x_sync_syncpt_r()
48 #define HOST1X_SYNC_SYNCPT(id) \ argument
50 static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(unsigned int id) in host1x_sync_syncpt_thresh_cpu0_int_status_r()
54 #define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id) \ argument
56 static inline u32 host1x_sync_syncpt_thresh_int_disable_r(unsigned int id) in host1x_sync_syncpt_thresh_int_disable_r()
60 #define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id) \ argument
62 static inline u32 host1x_sync_syncpt_thresh_int_enable_cpu0_r(unsigned int id) in host1x_sync_syncpt_thresh_int_enable_cpu0_r()
66 #define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id) \ argument
116 static inline u32 host1x_sync_mlock_owner_r(unsigned int id) in host1x_sync_mlock_owner_r()
120 #define HOST1X_SYNC_MLOCK_OWNER(id) \ argument
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| D | hw_host1x05_sync.h | 44 static inline u32 host1x_sync_syncpt_r(unsigned int id) in host1x_sync_syncpt_r()
48 #define HOST1X_SYNC_SYNCPT(id) \ argument
50 static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(unsigned int id) in host1x_sync_syncpt_thresh_cpu0_int_status_r()
54 #define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id) \ argument
56 static inline u32 host1x_sync_syncpt_thresh_int_disable_r(unsigned int id) in host1x_sync_syncpt_thresh_int_disable_r()
60 #define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id) \ argument
62 static inline u32 host1x_sync_syncpt_thresh_int_enable_cpu0_r(unsigned int id) in host1x_sync_syncpt_thresh_int_enable_cpu0_r()
66 #define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id) \ argument
116 static inline u32 host1x_sync_mlock_owner_r(unsigned int id) in host1x_sync_mlock_owner_r()
120 #define HOST1X_SYNC_MLOCK_OWNER(id) \ argument
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| D | hw_host1x02_sync.h | 44 static inline u32 host1x_sync_syncpt_r(unsigned int id) in host1x_sync_syncpt_r()
48 #define HOST1X_SYNC_SYNCPT(id) \ argument
50 static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(unsigned int id) in host1x_sync_syncpt_thresh_cpu0_int_status_r()
54 #define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id) \ argument
56 static inline u32 host1x_sync_syncpt_thresh_int_disable_r(unsigned int id) in host1x_sync_syncpt_thresh_int_disable_r()
60 #define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id) \ argument
62 static inline u32 host1x_sync_syncpt_thresh_int_enable_cpu0_r(unsigned int id) in host1x_sync_syncpt_thresh_int_enable_cpu0_r()
66 #define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id) \ argument
116 static inline u32 host1x_sync_mlock_owner_r(unsigned int id) in host1x_sync_mlock_owner_r()
120 #define HOST1X_SYNC_MLOCK_OWNER(id) \ argument
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| D | hw_host1x01_sync.h | 44 static inline u32 host1x_sync_syncpt_r(unsigned int id) in host1x_sync_syncpt_r()
48 #define HOST1X_SYNC_SYNCPT(id) \ argument
50 static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(unsigned int id) in host1x_sync_syncpt_thresh_cpu0_int_status_r()
54 #define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id) \ argument
56 static inline u32 host1x_sync_syncpt_thresh_int_disable_r(unsigned int id) in host1x_sync_syncpt_thresh_int_disable_r()
60 #define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id) \ argument
62 static inline u32 host1x_sync_syncpt_thresh_int_enable_cpu0_r(unsigned int id) in host1x_sync_syncpt_thresh_int_enable_cpu0_r()
66 #define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id) \ argument
116 static inline u32 host1x_sync_mlock_owner_r(unsigned int id) in host1x_sync_mlock_owner_r()
120 #define HOST1X_SYNC_MLOCK_OWNER(id) \ argument
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| /drivers/net/ethernet/intel/fm10k/ |
| D | fm10k_tlv.h | 62 unsigned int id; member
67 #define FM10K_TLV_ATTR_NULL_STRING(id, len) { id, FM10K_TLV_NULL_STRING, len } argument
68 #define FM10K_TLV_ATTR_MAC_ADDR(id) { id, FM10K_TLV_MAC_ADDR, 6 } argument
69 #define FM10K_TLV_ATTR_BOOL(id) { id, FM10K_TLV_BOOL, 0 } argument
70 #define FM10K_TLV_ATTR_U8(id) { id, FM10K_TLV_UNSIGNED, 1 } argument
71 #define FM10K_TLV_ATTR_U16(id) { id, FM10K_TLV_UNSIGNED, 2 } argument
72 #define FM10K_TLV_ATTR_U32(id) { id, FM10K_TLV_UNSIGNED, 4 } argument
73 #define FM10K_TLV_ATTR_U64(id) { id, FM10K_TLV_UNSIGNED, 8 } argument
74 #define FM10K_TLV_ATTR_S8(id) { id, FM10K_TLV_SIGNED, 1 } argument
75 #define FM10K_TLV_ATTR_S16(id) { id, FM10K_TLV_SIGNED, 2 } argument
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| /drivers/gpu/drm/amd/display/dc/dcn303/ |
| D | dcn303_resource.c | 297 #define SRI(reg_name, block, id)\ argument
300 #define SRI2(reg_name, block, id)\ argument
303 #define SRII(reg_name, block, id)\ argument
307 #define DCCG_SRII(reg_name, block, id)\ argument
311 #define VUPDATE_SRII(reg_name, block, id)\ argument
315 #define SRII_DWB(reg_name, temp_name, block, id)\ argument
319 #define SRII_MPC_RMU(reg_name, block, id)\ argument
335 #define vmid_regs(id)\ argument
389 #define vpg_regs(id)\ argument
418 #define afmt_regs(id)\ argument
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| /drivers/gpu/drm/amd/display/dc/gpio/ |
| D | gpio_service.c | 133 enum gpio_id id; in dal_gpio_service_create_irq() local
149 enum gpio_id id; in dal_gpio_service_create_generic_mux() local
180 enum gpio_id id, in dal_gpio_get_generic_pin_info()
241 enum gpio_id id, in is_pin_busy()
249 enum gpio_id id, in set_pin_busy()
257 enum gpio_id id, in set_pin_free()
265 enum gpio_id id, in dal_gpio_service_lock()
279 enum gpio_id id, in dal_gpio_service_unlock()
295 enum gpio_id id = gpio->id; in dal_gpio_service_open() local
379 enum gpio_id id = dal_gpio_get_id(irq); in dal_irq_get_source() local
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| D | ddc_regs.h | 34 #define DDC_GPIO_REG_LIST_ENTRY(type,cd,id) \ argument
39 #define DDC_GPIO_REG_LIST(cd,id) \ argument
47 #define DDC_REG_LIST(cd,id) \ argument
51 #define DDC_REG_LIST_DCN2(cd, id) \ argument
144 #define ddc_data_regs(id) \ argument
149 #define ddc_clk_regs(id) \ argument
173 #define ddc_data_regs_dcn2(id) \ argument
178 #define ddc_clk_regs_dcn2(id) \ argument
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| /drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_resource.c | 272 #define SRI(reg_name, block, id)\ argument
276 #define SRI2(reg_name, block, id)\ argument
280 #define SRIR(var_name, reg_name, block, id)\ argument
284 #define SRII(reg_name, block, id)\ argument
288 #define SRII_MPC_RMU(reg_name, block, id)\ argument
292 #define SRII_DWB(reg_name, temp_name, block, id)\ argument
296 #define DCCG_SRII(reg_name, block, id)\ argument
300 #define VUPDATE_SRII(reg_name, block, id)\ argument
372 #define abm_regs(id)\ argument
392 #define audio_regs(id)\ argument
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| /drivers/gpu/drm/amd/display/dc/dcn301/ |
| D | dcn301_resource.c | 295 #define SRI(reg_name, block, id)\ argument
299 #define SRI2(reg_name, block, id)\ argument
303 #define SRIR(var_name, reg_name, block, id)\ argument
307 #define SRII(reg_name, block, id)\ argument
311 #define SRII2(reg_name_pre, reg_name_post, id)\ argument
316 #define SRII_MPC_RMU(reg_name, block, id)\ argument
320 #define SRII_DWB(reg_name, temp_name, block, id)\ argument
324 #define DCCG_SRII(reg_name, block, id)\ argument
328 #define VUPDATE_SRII(reg_name, block, id)\ argument
390 #define abm_regs(id)\ argument
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| /drivers/gpu/drm/amd/display/dc/dcn302/ |
| D | dcn302_resource.c | 320 #define SRI(reg_name, block, id)\ argument
323 #define SRI2(reg_name, block, id)\ argument
326 #define SRII(reg_name, block, id)\ argument
330 #define DCCG_SRII(reg_name, block, id)\ argument
334 #define VUPDATE_SRII(reg_name, block, id)\ argument
338 #define SRII_DWB(reg_name, temp_name, block, id)\ argument
342 #define SRII_MPC_RMU(reg_name, block, id)\ argument
358 #define vmid_regs(id)\ argument
412 #define vpg_regs(id)\ argument
444 #define afmt_regs(id)\ argument
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| /drivers/macintosh/ |
| D | adbhid.c | 212 int id; member
268 int id = (data[0] >> 4) & 0x0f; in adbhid_keyboard_input() local
285 adbhid_input_keycode(int id, int scancode, int repeat) in adbhid_input_keycode()
407 int id = (data[0] >> 4) & 0x0f; in adbhid_mouse_input() local
505 int id = (data[0] >> 4) & 0x0f; in adbhid_buttons_input() local
753 adbhid_input_register(int id, int default_id, int original_handler_id, in adbhid_input_register()
917 static void adbhid_input_unregister(int id) in adbhid_input_unregister()
927 adbhid_input_reregister(int id, int default_id, int org_handler_id, in adbhid_input_reregister()
964 int id = keyboard_ids.id[i]; in adbhid_probe() local
988 int id = buttons_ids.id[i]; in adbhid_probe() local
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| /drivers/gpu/drm/amd/display/dc/bios/dce112/ |
| D | command_table_helper_dce112.c | 95 enum clock_source_id id) in clock_source_id_to_atom_phy_clk_src_id()
120 static uint8_t hpd_sel_to_atom(enum hpd_source_id id) in hpd_sel_to_atom()
151 static uint8_t dig_encoder_sel_to_atom(enum engine_id id) in dig_encoder_sel_to_atom()
162 enum clock_source_id id, in clock_source_id_to_atom()
212 static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id) in engine_bp_to_atom()
306 enum bp_dce_clock_type id, in dc_clock_type_to_atom()
330 static uint8_t transmitter_color_depth_to_atom(enum transmitter_color_depth id) in transmitter_color_depth_to_atom()
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| D | command_table_helper2_dce112.c | 95 enum clock_source_id id) in clock_source_id_to_atom_phy_clk_src_id()
120 static uint8_t hpd_sel_to_atom(enum hpd_source_id id) in hpd_sel_to_atom()
151 static uint8_t dig_encoder_sel_to_atom(enum engine_id id) in dig_encoder_sel_to_atom()
162 enum clock_source_id id, in clock_source_id_to_atom()
212 static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id) in engine_bp_to_atom()
306 enum bp_dce_clock_type id, in dc_clock_type_to_atom()
330 static uint8_t transmitter_color_depth_to_atom(enum transmitter_color_depth id) in transmitter_color_depth_to_atom()
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| /drivers/gpu/drm/i915/ |
| D | i915_syncmap.c | 112 __sync_branch_idx(const struct i915_syncmap *p, u64 id) in __sync_branch_idx()
118 __sync_leaf_idx(const struct i915_syncmap *p, u64 id) in __sync_leaf_idx()
124 static inline u64 __sync_branch_prefix(const struct i915_syncmap *p, u64 id) in __sync_branch_prefix()
129 static inline u64 __sync_leaf_prefix(const struct i915_syncmap *p, u64 id) in __sync_leaf_prefix()
154 bool i915_syncmap_is_later(struct i915_syncmap **root, u64 id, u32 seqno) in i915_syncmap_is_later()
199 __sync_alloc_leaf(struct i915_syncmap *parent, u64 id) in __sync_alloc_leaf()
214 static inline void __sync_set_seqno(struct i915_syncmap *p, u64 id, u32 seqno) in __sync_set_seqno()
230 static noinline int __sync_set(struct i915_syncmap **root, u64 id, u32 seqno) in __sync_set()
353 int i915_syncmap_set(struct i915_syncmap **root, u64 id, u32 seqno) in i915_syncmap_set()
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| /drivers/i2c/busses/ |
| D | i2c-cadence.c | 228 static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id) in cdns_i2c_clear_bus_hold()
235 static inline bool cdns_is_holdquirk(struct cdns_i2c *id, bool hold_wrkaround) in cdns_is_holdquirk()
242 static void cdns_i2c_set_mode(enum cdns_i2c_mode mode, struct cdns_i2c *id) in cdns_i2c_set_mode()
285 static void cdns_i2c_slave_rcv_data(struct cdns_i2c *id) in cdns_i2c_slave_rcv_data()
306 static void cdns_i2c_slave_send_data(struct cdns_i2c *id) in cdns_i2c_slave_send_data()
333 struct cdns_i2c *id = ptr; in cdns_i2c_slave_isr() local
394 struct cdns_i2c *id = ptr; in cdns_i2c_master_isr() local
547 struct cdns_i2c *id = ptr; in cdns_i2c_isr() local
559 static void cdns_i2c_mrecv(struct cdns_i2c *id) in cdns_i2c_mrecv()
657 static void cdns_i2c_msend(struct cdns_i2c *id) in cdns_i2c_msend()
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| /drivers/pinctrl/samsung/ |
| D | pinctrl-exynos.h | 51 #define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \ argument
60 #define EXYNOS_PIN_BANK_EINTG(pins, reg, id, offs) \ argument
70 #define EXYNOS_PIN_BANK_EINTW(pins, reg, id, offs) \ argument
80 #define EXYNOS5433_PIN_BANK_EINTG(pins, reg, id, offs) \ argument
90 #define EXYNOS5433_PIN_BANK_EINTW(pins, reg, id, offs) \ argument
100 #define EXYNOS5433_PIN_BANK_EINTW_EXT(pins, reg, id, offs, pctl_idx) \ argument
111 #define EXYNOS850_PIN_BANK_EINTN(pins, reg, id) \ argument
120 #define EXYNOS850_PIN_BANK_EINTG(pins, reg, id, offs) \ argument
130 #define EXYNOS850_PIN_BANK_EINTW(pins, reg, id, offs) \ argument
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| /drivers/thermal/ti-soc-thermal/ |
| D | ti-bandgap.c | 78 #define RMW_BITS(bgp, id, reg, mask, val) \ argument
158 static u32 ti_bandgap_read_temp(struct ti_bandgap *bgp, int id) in ti_bandgap_read_temp()
315 static inline int ti_bandgap_validate(struct ti_bandgap *bgp, int id) in ti_bandgap_validate()
337 static void ti_bandgap_read_counter(struct ti_bandgap *bgp, int id, in ti_bandgap_read_counter()
357 static void ti_bandgap_read_counter_delay(struct ti_bandgap *bgp, int id, in ti_bandgap_read_counter_delay()
401 int ti_bandgap_read_update_interval(struct ti_bandgap *bgp, int id, in ti_bandgap_read_update_interval()
434 static int ti_bandgap_write_counter_delay(struct ti_bandgap *bgp, int id, in ti_bandgap_write_counter_delay()
476 static void ti_bandgap_write_counter(struct ti_bandgap *bgp, int id, in ti_bandgap_write_counter()
494 int id, u32 interval) in ti_bandgap_write_update_interval()
524 int ti_bandgap_read_temperature(struct ti_bandgap *bgp, int id, in ti_bandgap_read_temperature()
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_link_encoder.h | 39 #define AUX_REG_LIST(id)\ argument
44 #define HPD_REG_LIST(id)\ argument
47 #define LE_COMMON_REG_LIST_BASE(id) \ argument
73 #define LE_COMMON_REG_LIST(id)\ argument
80 #define LE_DCE60_REG_LIST(id)\ argument
107 #define LE_DCE80_REG_LIST(id)\ argument
111 #define LE_DCE100_REG_LIST(id)\ argument
117 #define LE_DCE110_REG_LIST(id)\ argument
124 #define LE_DCE120_REG_LIST(id)\ argument
130 #define LE_DCN10_REG_LIST(id)\ argument
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| /drivers/regulator/ |
| D | max77620-regulator.c | 100 int id) in max77620_regulator_get_fps_src()
117 int fps_src, int id) in max77620_regulator_set_fps_src()
164 int id, bool is_suspend) in max77620_regulator_set_fps_slots()
208 int power_mode, int id) in max77620_regulator_set_power_mode()
237 int id) in max77620_regulator_get_power_mode()
264 static int max77620_read_slew_rate(struct max77620_regulator *pmic, int id) in max77620_read_slew_rate()
314 static int max77620_set_slew_rate(struct max77620_regulator *pmic, int id, in max77620_set_slew_rate()
351 static int max77620_config_power_ok(struct max77620_regulator *pmic, int id) in max77620_config_power_ok()
386 static int max77620_init_pmic(struct max77620_regulator *pmic, int id) in max77620_init_pmic()
445 int id = rdev_get_id(rdev); in max77620_regulator_enable() local
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| D | tps65910-regulator.c | 275 #define EXT_CONTROL_REG_BITS(id, regs_offs, bits) (((regs_offs) << 8) | (bits)) argument
320 static int tps65910_get_ctrl_register(int id) in tps65910_get_ctrl_register()
356 static int tps65911_get_ctrl_register(int id) in tps65911_get_ctrl_register()
394 int reg, id = rdev_get_id(dev); in tps65910_set_mode() local
419 int ret, reg, value, id = rdev_get_id(dev); in tps65910_get_mode() local
440 int ret, id = rdev_get_id(dev); in tps65910_get_voltage_dcdc_sel() local
517 int ret, reg, value, id = rdev_get_id(dev); in tps65910_get_voltage_sel() local
560 int ret, id = rdev_get_id(dev); in tps65911_get_voltage_sel() local
599 int id = rdev_get_id(dev), vsel; in tps65910_set_voltage_dcdc_sel() local
637 int reg, id = rdev_get_id(dev); in tps65910_set_voltage_sel() local
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