Home
last modified time | relevance | path

Searched refs:M (Results 1 – 25 of 228) sorted by relevance

12345678910

/arch/mips/mm/
Duasm-mips.c32 #define M(a, b, c, d, e, f) \ macro
51 [insn_addiu] = {M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
52 [insn_addu] = {M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD},
53 [insn_and] = {M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD},
54 [insn_andi] = {M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM},
55 [insn_bbit0] = {M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
56 [insn_bbit1] = {M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
57 [insn_beq] = {M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
58 [insn_beql] = {M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
59 [insn_bgez] = {M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM},
[all …]
Duasm-micromips.c32 #define M(a, b, c, d, e, f) \ macro
43 [insn_addu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD},
44 [insn_addiu] = {M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
45 [insn_and] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD},
46 [insn_andi] = {M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM},
47 [insn_beq] = {M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
49 [insn_bgez] = {M(mm_pool32i_op, mm_bgez_op, 0, 0, 0, 0), RS | BIMM},
51 [insn_bltz] = {M(mm_pool32i_op, mm_bltz_op, 0, 0, 0, 0), RS | BIMM},
53 [insn_bne] = {M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM},
54 [insn_cache] = {M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM},
[all …]
/arch/sparc/kernel/
Dtraps_64.c1098 #define M 147 macro
1100 /*00*/NONE, C0, C1, M2, C2, M2, M3, 47, C3, M2, M2, 53, M2, 41, 29, M,
1101 /*01*/C4, M, M, 50, M2, 38, 25, M2, M2, 33, 24, M2, 11, M, M2, 16,
1102 /*02*/C5, M, M, 46, M2, 37, 19, M2, M, 31, 32, M, 7, M2, M2, 10,
1103 /*03*/M2, 40, 13, M2, 59, M, M2, 66, M, M2, M2, 0, M2, 67, 71, M,
1104 /*04*/C6, M, M, 43, M, 36, 18, M, M2, 49, 15, M, 63, M2, M2, 6,
1105 /*05*/M2, 44, 28, M2, M, M2, M2, 52, 68, M2, M2, 62, M2, M3, M3, M4,
1106 /*06*/M2, 26, 106, M2, 64, M, M2, 2, 120, M, M2, M3, M, M3, M3, M4,
1107 /*07*/116, M2, M2, M3, M2, M3, M, M4, M2, 58, 54, M2, M, M4, M4, M3,
1108 /*08*/C7, M2, M, 42, M, 35, 17, M2, M, 45, 14, M2, 21, M2, M2, 5,
[all …]
/arch/m68k/fpsp040/
Dstwotox.S31 | N = 64(M + M') + j, j = 0,1,2,...,63.
34 | 2**X = 2**(M') * 2**(M) * 2**(j/64) * exp(r).
44 | N = 64(M + M') + j, j = 0,1,2,...,63.
50 | 10**X = 2**(M') * 2**(M) * 2**(j/64) * exp(r).
57 | Fact1 := 2**(M) * Fact1
58 | Fact2 := 2**(M) * Fact2
59 | Thus Fact1 + Fact2 = 2**(M) * 2**(j/64).
64 | 4. Let AdjFact := 2**(M'). Return
243 asrl #1,%d0 | ...D0 IS M
244 subl %d0,%d2 | ...d2 IS M', N = 64(M+M') + J
[all …]
Dsetox.S83 | 2.4 Calculate M = (N - J)/64; so N = 64M + J.
85 | 2.6 Create the value Scale = 2^M.
153 | exp(X) = 2^M * 2^(J/64) * exp(R).
159 | |M| <= 16380, and Scale = 2^M. Moreover, exp(X) will
162 | X = (M1+M)log2 + Jlog2/64 + R, |M1+M| >= 16380.
165 | approximately M. Thus 6.2 will never cause over/underflow.
190 | 8.4 K := (N-J)/64, M1 := truncate(K/2), M = K-M1, AdjFlag := 1.
192 | 8.6 Create the values Scale = 2^M, AdjScale = 2^M1.
496 asrl #6,%d0 | ...D0 is M
497 addiw #0x3FFF,%d0 | ...biased expo. of 2^(M)
[all …]
/arch/arm/boot/dts/
Dste-nomadik-stn8815.dtsi198 mxtal: mxtal@19.2M {
210 timclk: timclk@2.4M {
248 clk216: clk216@216M {
255 clk108: clk108@108M {
262 clk72: clk72@72M {
270 clk48: clk48@48M {
278 clk27: clk27@27M {
287 ulpiclk: ulpiclk@60M {
298 hclkdma0: hclkdma0@48M {
304 hclksmc: hclksmc@48M {
[all …]
Dintegratorcp.dts50 xtal_codec: xtal24.576@24.576M {
57 aaci_bitclk: aaci_bitclk@12.288M {
66 xtal25mhz: xtal25mhz@25M {
73 uartclk: uartclk@14.74M {
88 cm24mhz: cm24mhz@24M {
95 cmcore: cmosc@24M {
104 cmmem: cmosc@24M {
113 auxosc: auxosc@24M {
122 kmiclk: kmiclk@1M {
131 timclk: timclk@1M {
/arch/mips/include/asm/
Dmips-r2-to-r6-emul.h46 #define MIPS_R2_STATS(M) \ argument
52 __this_cpu_inc(mipsr2emustats.M); \
56 __this_cpu_inc(mipsr2bdemustats.M); \
61 #define MIPS_R2BR_STATS(M) \ argument
64 __this_cpu_inc(mipsr2bremustats.M); \
70 #define MIPS_R2_STATS(M) do { } while (0) argument
71 #define MIPS_R2BR_STATS(M) do { } while (0) argument
Dfpu_emulator.h157 #define MIPS_FPU_EMU_INC_STATS(M) \ argument
160 __this_cpu_inc(fpuemustats.M); \
165 #define MIPS_FPU_EMU_INC_STATS(M) do { } while (0) argument
/arch/ia64/kernel/
Dkprobes.c30 enum instruction_type {A, I, M, F, B, L, X, u}; enumerator
32 { M, I, I }, /* 00 */
33 { M, I, I }, /* 01 */
34 { M, I, I }, /* 02 */
35 { M, I, I }, /* 03 */
36 { M, L, X }, /* 04 */
37 { M, L, X }, /* 05 */
40 { M, M, I }, /* 08 */
41 { M, M, I }, /* 09 */
42 { M, M, I }, /* 0A */
[all …]
/arch/mips/sgi-ip27/
DKconfig8 bool "IP27 M-Mode"
11 in either N-Modes which allows for more nodes or M-Mode which allows
13 M-Mode, so choose M-mode here.
19 in either N-Modes which allows for more nodes or M-Mode which allows
21 M-Mode, so choose M-mode here.
/arch/mips/boot/dts/netlogic/
Dxlp_gvp.dts47 reg = <0x0 0x100000>; /* 1M */
53 reg = <0x100000 0x100000>; /* 1M */
58 reg = <0x200000 0x500000>; /* 5M */
63 reg = <0x700000 0x800000>; /* 8M */
68 reg = <0xf00000 0x100000>; /* 1M */
Dxlp_rvp.dts47 reg = <0x0 0x100000>; /* 1M */
53 reg = <0x100000 0x100000>; /* 1M */
58 reg = <0x200000 0x500000>; /* 5M */
63 reg = <0x700000 0x800000>; /* 8M */
68 reg = <0xf00000 0x100000>; /* 1M */
Dxlp_svp.dts89 reg = <0x0 0x100000>; /* 1M */
95 reg = <0x100000 0x100000>; /* 1M */
100 reg = <0x200000 0x500000>; /* 5M */
105 reg = <0x700000 0x800000>; /* 8M */
110 reg = <0xf00000 0x100000>; /* 1M */
Dxlp_evp.dts89 reg = <0x0 0x100000>; /* 1M */
95 reg = <0x100000 0x100000>; /* 1M */
100 reg = <0x200000 0x500000>; /* 5M */
105 reg = <0x700000 0x800000>; /* 8M */
110 reg = <0xf00000 0x100000>; /* 1M */
Dxlp_fvp.dts89 reg = <0x0 0x100000>; /* 1M */
95 reg = <0x100000 0x100000>; /* 1M */
100 reg = <0x200000 0x500000>; /* 5M */
105 reg = <0x700000 0x800000>; /* 8M */
110 reg = <0xf00000 0x100000>; /* 1M */
/arch/arm/include/asm/
Dhw_breakpoint.h109 #define ARM_DBG_READ(N, M, OP2, VAL) do {\ argument
110 asm volatile("mrc p14, 0, %0, " #N "," #M ", " #OP2 : "=r" (VAL));\
113 #define ARM_DBG_WRITE(N, M, OP2, VAL) do {\ argument
114 asm volatile("mcr p14, 0, %0, " #N "," #M ", " #OP2 : : "r" (VAL));\
/arch/arm64/boot/dts/amlogic/
Dmeson-g12b-s922x-khadas-vim3.dts21 * an USB3.0 Type A connector and a M.2 Key M slot.
26 * to the M.2 Key M slot, uncomment the following block to disable
Dmeson-g12b-a311d-khadas-vim3.dts21 * an USB3.0 Type A connector and a M.2 Key M slot.
26 * to the M.2 Key M slot, uncomment the following block to disable
Dmeson-sm1-khadas-vim3l.dts89 * an USB3.0 Type A connector and a M.2 Key M slot.
94 * to the M.2 Key M slot, uncomment the following block to disable
/arch/arm/configs/
Dneponset_defconfig17 …parts=sa1100:512K(boot),1M(kernel),2560K(initrd),4M(root) load_ramdisk=1 prompt_ramdisk=0 mem=32M …
Dpleb_defconfig13 CONFIG_CMDLINE="console=ttySA0,9600 mem=16M@0xc0000000 mem=16M@0xc8000000 root=/dev/ram initrd=0xc0…
Dassabet_defconfig13 CONFIG_CMDLINE="mem=32M console=ttySA0,38400n8 initrd=0xc0800000,3M root=/dev/ram"
/arch/arm64/boot/dts/freescale/
Dimx8mm-evk.dts26 opp-25M {
30 opp-100M {
34 opp-750M {
/arch/powerpc/platforms/ps3/
DKconfig76 general, all users will say Y or M.
87 general, all users will say Y or M.
122 In general, all users will say Y or M.
132 In general, all users will say Y or M.
133 Also make sure to say Y or M to "SCSI CDROM support" later.
144 In general, PS3 OtherOS users will say Y or M.
168 oprofile and perfmon2, then say Y or M, otherwise say N.

12345678910