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Searched refs:bus_clk (Results 1 – 14 of 14) sorted by relevance

/arch/mips/ar7/
Dclock.c92 static struct clk_rate bus_clk = { variable
211 int base_clock = bus_clk.rate; in tnetd7300_set_clock()
215 base_clock = bus_clk.rate; in tnetd7300_set_clock()
248 bus_clk.rate = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT, in tnetd7300_init_clocks()
255 cpu_clk.rate = bus_clk.rate; in tnetd7300_init_clocks()
351 bus_clk.rate = in tnetd7200_init_clocks()
355 bus_clk.rate); in tnetd7200_init_clocks()
382 bus_clk.rate = cpu_clk.rate / 2; in tnetd7200_init_clocks()
385 dsp_mul * 2, bus_clk.rate); in tnetd7200_init_clocks()
392 bus_clk.rate = ((dsp_base / dsp_prediv) * dsp_mul) in tnetd7200_init_clocks()
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Dplatform.c553 struct clk *bus_clk; in ar7_register_uarts() local
558 bus_clk = clk_get(NULL, "bus"); in ar7_register_uarts()
559 if (IS_ERR(bus_clk)) in ar7_register_uarts()
563 uart_port.uartclk = clk_get_rate(bus_clk) / 2; in ar7_register_uarts()
/arch/sh/kernel/cpu/
Dclock-cpg.c19 static struct clk bus_clk = { variable
35 &bus_clk,
43 CLKDEV_CON_ID("bus_clk", &bus_clk),
/arch/mips/pci/
Dpci-lantiq.c96 const __be32 *req_mask, *bus_clk; in ltq_pci_startup() local
114 bus_clk = of_get_property(node, "lantiq,bus-clock", NULL); in ltq_pci_startup()
115 if (bus_clk) in ltq_pci_startup()
116 clk_set_rate(clk_pci, *bus_clk); in ltq_pci_startup()
/arch/arm/boot/dts/
Dexynos3250.dtsi351 clock-names = "bus_clk", "pll_clk";
Dexynos4.dtsi199 clock-names = "bus_clk", "sclk_mipi";
Dexynos5250.dtsi845 clock-names = "bus_clk", "sclk_mipi";
Dexynos5420.dtsi617 clock-names = "bus_clk", "pll_clk";
Dqcom-apq8064.dtsi1471 "bus_clk",
/arch/arm64/boot/dts/mediatek/
Dmt2712e.dtsi765 clock-names = "source", "hclk", "bus_clk", "source_cg";
/arch/arm64/boot/dts/rockchip/
Drk3399.dtsi373 "bus_clk", "aclk_usb3_rksoc_axi_perf",
409 "bus_clk", "aclk_usb3_rksoc_axi_perf",
Drk3328.dtsi990 "bus_clk";
/arch/arm64/boot/dts/exynos/
Dexynos5433.dtsi1035 clock-names = "bus_clk",
/arch/arm64/boot/dts/qcom/
Dmsm8996.dtsi1736 "bus_clk",