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1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
3 */
4
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/clock/qcom,gcc-msm8996.h>
7#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
8#include <dt-bindings/clock/qcom,rpmcc.h>
9#include <dt-bindings/power/qcom-rpmpd.h>
10#include <dt-bindings/soc/qcom,apr.h>
11#include <dt-bindings/thermal/thermal.h>
12
13/ {
14	interrupt-parent = <&intc>;
15
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	chosen { };
20
21	clocks {
22		xo_board: xo-board {
23			compatible = "fixed-clock";
24			#clock-cells = <0>;
25			clock-frequency = <19200000>;
26			clock-output-names = "xo_board";
27		};
28
29		sleep_clk: sleep-clk {
30			compatible = "fixed-clock";
31			#clock-cells = <0>;
32			clock-frequency = <32764>;
33			clock-output-names = "sleep_clk";
34		};
35	};
36
37	cpus {
38		#address-cells = <2>;
39		#size-cells = <0>;
40
41		CPU0: cpu@0 {
42			device_type = "cpu";
43			compatible = "qcom,kryo";
44			reg = <0x0 0x0>;
45			enable-method = "psci";
46			cpu-idle-states = <&CPU_SLEEP_0>;
47			capacity-dmips-mhz = <1024>;
48			clocks = <&kryocc 0>;
49			operating-points-v2 = <&cluster0_opp>;
50			#cooling-cells = <2>;
51			next-level-cache = <&L2_0>;
52			L2_0: l2-cache {
53			      compatible = "cache";
54			      cache-level = <2>;
55			};
56		};
57
58		CPU1: cpu@1 {
59			device_type = "cpu";
60			compatible = "qcom,kryo";
61			reg = <0x0 0x1>;
62			enable-method = "psci";
63			cpu-idle-states = <&CPU_SLEEP_0>;
64			capacity-dmips-mhz = <1024>;
65			clocks = <&kryocc 0>;
66			operating-points-v2 = <&cluster0_opp>;
67			#cooling-cells = <2>;
68			next-level-cache = <&L2_0>;
69		};
70
71		CPU2: cpu@100 {
72			device_type = "cpu";
73			compatible = "qcom,kryo";
74			reg = <0x0 0x100>;
75			enable-method = "psci";
76			cpu-idle-states = <&CPU_SLEEP_0>;
77			capacity-dmips-mhz = <1024>;
78			clocks = <&kryocc 1>;
79			operating-points-v2 = <&cluster1_opp>;
80			#cooling-cells = <2>;
81			next-level-cache = <&L2_1>;
82			L2_1: l2-cache {
83			      compatible = "cache";
84			      cache-level = <2>;
85			};
86		};
87
88		CPU3: cpu@101 {
89			device_type = "cpu";
90			compatible = "qcom,kryo";
91			reg = <0x0 0x101>;
92			enable-method = "psci";
93			cpu-idle-states = <&CPU_SLEEP_0>;
94			capacity-dmips-mhz = <1024>;
95			clocks = <&kryocc 1>;
96			operating-points-v2 = <&cluster1_opp>;
97			#cooling-cells = <2>;
98			next-level-cache = <&L2_1>;
99		};
100
101		cpu-map {
102			cluster0 {
103				core0 {
104					cpu = <&CPU0>;
105				};
106
107				core1 {
108					cpu = <&CPU1>;
109				};
110			};
111
112			cluster1 {
113				core0 {
114					cpu = <&CPU2>;
115				};
116
117				core1 {
118					cpu = <&CPU3>;
119				};
120			};
121		};
122
123		idle-states {
124			entry-method = "psci";
125
126			CPU_SLEEP_0: cpu-sleep-0 {
127				compatible = "arm,idle-state";
128				idle-state-name = "standalone-power-collapse";
129				arm,psci-suspend-param = <0x00000004>;
130				entry-latency-us = <130>;
131				exit-latency-us = <80>;
132				min-residency-us = <300>;
133			};
134		};
135	};
136
137	cluster0_opp: opp_table0 {
138		compatible = "operating-points-v2-kryo-cpu";
139		nvmem-cells = <&speedbin_efuse>;
140		opp-shared;
141
142		/* Nominal fmax for now */
143		opp-307200000 {
144			opp-hz = /bits/ 64 <307200000>;
145			opp-supported-hw = <0x7>;
146			clock-latency-ns = <200000>;
147		};
148		opp-422400000 {
149			opp-hz = /bits/ 64 <422400000>;
150			opp-supported-hw = <0x7>;
151			clock-latency-ns = <200000>;
152		};
153		opp-480000000 {
154			opp-hz = /bits/ 64 <480000000>;
155			opp-supported-hw = <0x7>;
156			clock-latency-ns = <200000>;
157		};
158		opp-556800000 {
159			opp-hz = /bits/ 64 <556800000>;
160			opp-supported-hw = <0x7>;
161			clock-latency-ns = <200000>;
162		};
163		opp-652800000 {
164			opp-hz = /bits/ 64 <652800000>;
165			opp-supported-hw = <0x7>;
166			clock-latency-ns = <200000>;
167		};
168		opp-729600000 {
169			opp-hz = /bits/ 64 <729600000>;
170			opp-supported-hw = <0x7>;
171			clock-latency-ns = <200000>;
172		};
173		opp-844800000 {
174			opp-hz = /bits/ 64 <844800000>;
175			opp-supported-hw = <0x7>;
176			clock-latency-ns = <200000>;
177		};
178		opp-960000000 {
179			opp-hz = /bits/ 64 <960000000>;
180			opp-supported-hw = <0x7>;
181			clock-latency-ns = <200000>;
182		};
183		opp-1036800000 {
184			opp-hz = /bits/ 64 <1036800000>;
185			opp-supported-hw = <0x7>;
186			clock-latency-ns = <200000>;
187		};
188		opp-1113600000 {
189			opp-hz = /bits/ 64 <1113600000>;
190			opp-supported-hw = <0x7>;
191			clock-latency-ns = <200000>;
192		};
193		opp-1190400000 {
194			opp-hz = /bits/ 64 <1190400000>;
195			opp-supported-hw = <0x7>;
196			clock-latency-ns = <200000>;
197		};
198		opp-1228800000 {
199			opp-hz = /bits/ 64 <1228800000>;
200			opp-supported-hw = <0x7>;
201			clock-latency-ns = <200000>;
202		};
203		opp-1324800000 {
204			opp-hz = /bits/ 64 <1324800000>;
205			opp-supported-hw = <0x5>;
206			clock-latency-ns = <200000>;
207		};
208		opp-1363200000 {
209			opp-hz = /bits/ 64 <1363200000>;
210			opp-supported-hw = <0x2>;
211			clock-latency-ns = <200000>;
212		};
213		opp-1401600000 {
214			opp-hz = /bits/ 64 <1401600000>;
215			opp-supported-hw = <0x5>;
216			clock-latency-ns = <200000>;
217		};
218		opp-1478400000 {
219			opp-hz = /bits/ 64 <1478400000>;
220			opp-supported-hw = <0x1>;
221			clock-latency-ns = <200000>;
222		};
223		opp-1497600000 {
224			opp-hz = /bits/ 64 <1497600000>;
225			opp-supported-hw = <0x04>;
226			clock-latency-ns = <200000>;
227		};
228		opp-1593600000 {
229			opp-hz = /bits/ 64 <1593600000>;
230			opp-supported-hw = <0x1>;
231			clock-latency-ns = <200000>;
232		};
233	};
234
235	cluster1_opp: opp_table1 {
236		compatible = "operating-points-v2-kryo-cpu";
237		nvmem-cells = <&speedbin_efuse>;
238		opp-shared;
239
240		/* Nominal fmax for now */
241		opp-307200000 {
242			opp-hz = /bits/ 64 <307200000>;
243			opp-supported-hw = <0x7>;
244			clock-latency-ns = <200000>;
245		};
246		opp-403200000 {
247			opp-hz = /bits/ 64 <403200000>;
248			opp-supported-hw = <0x7>;
249			clock-latency-ns = <200000>;
250		};
251		opp-480000000 {
252			opp-hz = /bits/ 64 <480000000>;
253			opp-supported-hw = <0x7>;
254			clock-latency-ns = <200000>;
255		};
256		opp-556800000 {
257			opp-hz = /bits/ 64 <556800000>;
258			opp-supported-hw = <0x7>;
259			clock-latency-ns = <200000>;
260		};
261		opp-652800000 {
262			opp-hz = /bits/ 64 <652800000>;
263			opp-supported-hw = <0x7>;
264			clock-latency-ns = <200000>;
265		};
266		opp-729600000 {
267			opp-hz = /bits/ 64 <729600000>;
268			opp-supported-hw = <0x7>;
269			clock-latency-ns = <200000>;
270		};
271		opp-806400000 {
272			opp-hz = /bits/ 64 <806400000>;
273			opp-supported-hw = <0x7>;
274			clock-latency-ns = <200000>;
275		};
276		opp-883200000 {
277			opp-hz = /bits/ 64 <883200000>;
278			opp-supported-hw = <0x7>;
279			clock-latency-ns = <200000>;
280		};
281		opp-940800000 {
282			opp-hz = /bits/ 64 <940800000>;
283			opp-supported-hw = <0x7>;
284			clock-latency-ns = <200000>;
285		};
286		opp-1036800000 {
287			opp-hz = /bits/ 64 <1036800000>;
288			opp-supported-hw = <0x7>;
289			clock-latency-ns = <200000>;
290		};
291		opp-1113600000 {
292			opp-hz = /bits/ 64 <1113600000>;
293			opp-supported-hw = <0x7>;
294			clock-latency-ns = <200000>;
295		};
296		opp-1190400000 {
297			opp-hz = /bits/ 64 <1190400000>;
298			opp-supported-hw = <0x7>;
299			clock-latency-ns = <200000>;
300		};
301		opp-1248000000 {
302			opp-hz = /bits/ 64 <1248000000>;
303			opp-supported-hw = <0x7>;
304			clock-latency-ns = <200000>;
305		};
306		opp-1324800000 {
307			opp-hz = /bits/ 64 <1324800000>;
308			opp-supported-hw = <0x7>;
309			clock-latency-ns = <200000>;
310		};
311		opp-1401600000 {
312			opp-hz = /bits/ 64 <1401600000>;
313			opp-supported-hw = <0x7>;
314			clock-latency-ns = <200000>;
315		};
316		opp-1478400000 {
317			opp-hz = /bits/ 64 <1478400000>;
318			opp-supported-hw = <0x7>;
319			clock-latency-ns = <200000>;
320		};
321		opp-1555200000 {
322			opp-hz = /bits/ 64 <1555200000>;
323			opp-supported-hw = <0x7>;
324			clock-latency-ns = <200000>;
325		};
326		opp-1632000000 {
327			opp-hz = /bits/ 64 <1632000000>;
328			opp-supported-hw = <0x7>;
329			clock-latency-ns = <200000>;
330		};
331		opp-1708800000 {
332			opp-hz = /bits/ 64 <1708800000>;
333			opp-supported-hw = <0x7>;
334			clock-latency-ns = <200000>;
335		};
336		opp-1785600000 {
337			opp-hz = /bits/ 64 <1785600000>;
338			opp-supported-hw = <0x7>;
339			clock-latency-ns = <200000>;
340		};
341		opp-1804800000 {
342			opp-hz = /bits/ 64 <1804800000>;
343			opp-supported-hw = <0x6>;
344			clock-latency-ns = <200000>;
345		};
346		opp-1824000000 {
347			opp-hz = /bits/ 64 <1824000000>;
348			opp-supported-hw = <0x1>;
349			clock-latency-ns = <200000>;
350		};
351		opp-1900800000 {
352			opp-hz = /bits/ 64 <1900800000>;
353			opp-supported-hw = <0x4>;
354			clock-latency-ns = <200000>;
355		};
356		opp-1920000000 {
357			opp-hz = /bits/ 64 <1920000000>;
358			opp-supported-hw = <0x1>;
359			clock-latency-ns = <200000>;
360		};
361		opp-1996800000 {
362			opp-hz = /bits/ 64 <1996800000>;
363			opp-supported-hw = <0x1>;
364			clock-latency-ns = <200000>;
365		};
366		opp-2073600000 {
367			opp-hz = /bits/ 64 <2073600000>;
368			opp-supported-hw = <0x1>;
369			clock-latency-ns = <200000>;
370		};
371		opp-2150400000 {
372			opp-hz = /bits/ 64 <2150400000>;
373			opp-supported-hw = <0x1>;
374			clock-latency-ns = <200000>;
375		};
376	};
377
378	firmware {
379		scm {
380			compatible = "qcom,scm-msm8996";
381			qcom,dload-mode = <&tcsr 0x13000>;
382		};
383	};
384
385	tcsr_mutex: hwlock {
386		compatible = "qcom,tcsr-mutex";
387		syscon = <&tcsr_mutex_regs 0 0x1000>;
388		#hwlock-cells = <1>;
389	};
390
391	memory@80000000 {
392		device_type = "memory";
393		/* We expect the bootloader to fill in the reg */
394		reg = <0x0 0x80000000 0x0 0x0>;
395	};
396
397	etm {
398		compatible = "qcom,coresight-remote-etm";
399
400		out-ports {
401			port {
402				modem_etm_out_funnel_in2: endpoint {
403					remote-endpoint =
404					  <&funnel_in2_in_modem_etm>;
405				};
406			};
407		};
408	};
409
410	psci {
411		compatible = "arm,psci-1.0";
412		method = "smc";
413	};
414
415	reserved-memory {
416		#address-cells = <2>;
417		#size-cells = <2>;
418		ranges;
419
420		mba_region: mba@91500000 {
421			reg = <0x0 0x91500000 0x0 0x200000>;
422			no-map;
423		};
424
425		slpi_region: slpi@90b00000 {
426			reg = <0x0 0x90b00000 0x0 0xa00000>;
427			no-map;
428		};
429
430		venus_region: venus@90400000 {
431			reg = <0x0 0x90400000 0x0 0x700000>;
432			no-map;
433		};
434
435		adsp_region: adsp@8ea00000 {
436			reg = <0x0 0x8ea00000 0x0 0x1a00000>;
437			no-map;
438		};
439
440		mpss_region: mpss@88800000 {
441			reg = <0x0 0x88800000 0x0 0x6200000>;
442			no-map;
443		};
444
445		smem_mem: smem-mem@86000000 {
446			reg = <0x0 0x86000000 0x0 0x200000>;
447			no-map;
448		};
449
450		memory@85800000 {
451			reg = <0x0 0x85800000 0x0 0x800000>;
452			no-map;
453		};
454
455		memory@86200000 {
456			reg = <0x0 0x86200000 0x0 0x2600000>;
457			no-map;
458		};
459
460		rmtfs@86700000 {
461			compatible = "qcom,rmtfs-mem";
462
463			size = <0x0 0x200000>;
464			alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
465			no-map;
466
467			qcom,client-id = <1>;
468			qcom,vmid = <15>;
469		};
470
471		zap_shader_region: gpu@8f200000 {
472			compatible = "shared-dma-pool";
473			reg = <0x0 0x90b00000 0x0 0xa00000>;
474			no-map;
475		};
476	};
477
478	rpm-glink {
479		compatible = "qcom,glink-rpm";
480
481		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
482
483		qcom,rpm-msg-ram = <&rpm_msg_ram>;
484
485		mboxes = <&apcs_glb 0>;
486
487		rpm_requests: rpm-requests {
488			compatible = "qcom,rpm-msm8996";
489			qcom,glink-channels = "rpm_requests";
490
491			rpmcc: qcom,rpmcc {
492				compatible = "qcom,rpmcc-msm8996";
493				#clock-cells = <1>;
494			};
495
496			rpmpd: power-controller {
497				compatible = "qcom,msm8996-rpmpd";
498				#power-domain-cells = <1>;
499				operating-points-v2 = <&rpmpd_opp_table>;
500
501				rpmpd_opp_table: opp-table {
502					compatible = "operating-points-v2";
503
504					rpmpd_opp1: opp1 {
505						opp-level = <1>;
506					};
507
508					rpmpd_opp2: opp2 {
509						opp-level = <2>;
510					};
511
512					rpmpd_opp3: opp3 {
513						opp-level = <3>;
514					};
515
516					rpmpd_opp4: opp4 {
517						opp-level = <4>;
518					};
519
520					rpmpd_opp5: opp5 {
521						opp-level = <5>;
522					};
523
524					rpmpd_opp6: opp6 {
525						opp-level = <6>;
526					};
527				};
528			};
529		};
530	};
531
532	smem {
533		compatible = "qcom,smem";
534		memory-region = <&smem_mem>;
535		hwlocks = <&tcsr_mutex 3>;
536	};
537
538	smp2p-adsp {
539		compatible = "qcom,smp2p";
540		qcom,smem = <443>, <429>;
541
542		interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
543
544		mboxes = <&apcs_glb 10>;
545
546		qcom,local-pid = <0>;
547		qcom,remote-pid = <2>;
548
549		smp2p_adsp_out: master-kernel {
550			qcom,entry-name = "master-kernel";
551			#qcom,smem-state-cells = <1>;
552		};
553
554		smp2p_adsp_in: slave-kernel {
555			qcom,entry-name = "slave-kernel";
556
557			interrupt-controller;
558			#interrupt-cells = <2>;
559		};
560	};
561
562	smp2p-modem {
563		compatible = "qcom,smp2p";
564		qcom,smem = <435>, <428>;
565
566		interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
567
568		mboxes = <&apcs_glb 14>;
569
570		qcom,local-pid = <0>;
571		qcom,remote-pid = <1>;
572
573		modem_smp2p_out: master-kernel {
574			qcom,entry-name = "master-kernel";
575			#qcom,smem-state-cells = <1>;
576		};
577
578		modem_smp2p_in: slave-kernel {
579			qcom,entry-name = "slave-kernel";
580
581			interrupt-controller;
582			#interrupt-cells = <2>;
583		};
584	};
585
586	smp2p-slpi {
587		compatible = "qcom,smp2p";
588		qcom,smem = <481>, <430>;
589
590		interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
591
592		mboxes = <&apcs_glb 26>;
593
594		qcom,local-pid = <0>;
595		qcom,remote-pid = <3>;
596
597		smp2p_slpi_in: slave-kernel {
598			qcom,entry-name = "slave-kernel";
599			interrupt-controller;
600			#interrupt-cells = <2>;
601		};
602
603		smp2p_slpi_out: master-kernel {
604			qcom,entry-name = "master-kernel";
605			#qcom,smem-state-cells = <1>;
606		};
607	};
608
609	soc: soc {
610		#address-cells = <1>;
611		#size-cells = <1>;
612		ranges = <0 0 0 0xffffffff>;
613		compatible = "simple-bus";
614
615		pcie_phy: phy@34000 {
616			compatible = "qcom,msm8996-qmp-pcie-phy";
617			reg = <0x00034000 0x488>;
618			#clock-cells = <1>;
619			#address-cells = <1>;
620			#size-cells = <1>;
621			ranges;
622
623			clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
624				<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
625				<&gcc GCC_PCIE_CLKREF_CLK>;
626			clock-names = "aux", "cfg_ahb", "ref";
627
628			resets = <&gcc GCC_PCIE_PHY_BCR>,
629				<&gcc GCC_PCIE_PHY_COM_BCR>,
630				<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
631			reset-names = "phy", "common", "cfg";
632			status = "disabled";
633
634			pciephy_0: phy@35000 {
635				reg = <0x00035000 0x130>,
636				      <0x00035200 0x200>,
637				      <0x00035400 0x1dc>;
638				#phy-cells = <0>;
639
640				clock-output-names = "pcie_0_pipe_clk_src";
641				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
642				clock-names = "pipe0";
643				resets = <&gcc GCC_PCIE_0_PHY_BCR>;
644				reset-names = "lane0";
645			};
646
647			pciephy_1: phy@36000 {
648				reg = <0x00036000 0x130>,
649				      <0x00036200 0x200>,
650				      <0x00036400 0x1dc>;
651				#phy-cells = <0>;
652
653				clock-output-names = "pcie_1_pipe_clk_src";
654				clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
655				clock-names = "pipe1";
656				resets = <&gcc GCC_PCIE_1_PHY_BCR>;
657				reset-names = "lane1";
658			};
659
660			pciephy_2: phy@37000 {
661				reg = <0x00037000 0x130>,
662				      <0x00037200 0x200>,
663				      <0x00037400 0x1dc>;
664				#phy-cells = <0>;
665
666				clock-output-names = "pcie_2_pipe_clk_src";
667				clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
668				clock-names = "pipe2";
669				resets = <&gcc GCC_PCIE_2_PHY_BCR>;
670				reset-names = "lane2";
671			};
672		};
673
674		rpm_msg_ram: sram@68000 {
675			compatible = "qcom,rpm-msg-ram";
676			reg = <0x00068000 0x6000>;
677		};
678
679		qfprom@74000 {
680			compatible = "qcom,qfprom";
681			reg = <0x00074000 0x8ff>;
682			#address-cells = <1>;
683			#size-cells = <1>;
684
685			qusb2p_hstx_trim: hstx_trim@24e {
686				reg = <0x24e 0x2>;
687				bits = <5 4>;
688			};
689
690			qusb2s_hstx_trim: hstx_trim@24f {
691				reg = <0x24f 0x1>;
692				bits = <1 4>;
693			};
694
695			speedbin_efuse: speedbin@133 {
696				reg = <0x133 0x1>;
697				bits = <5 3>;
698			};
699		};
700
701		rng: rng@83000 {
702			compatible = "qcom,prng-ee";
703			reg = <0x00083000 0x1000>;
704			clocks = <&gcc GCC_PRNG_AHB_CLK>;
705			clock-names = "core";
706		};
707
708		gcc: clock-controller@300000 {
709			compatible = "qcom,gcc-msm8996";
710			#clock-cells = <1>;
711			#reset-cells = <1>;
712			#power-domain-cells = <1>;
713			reg = <0x00300000 0x90000>;
714
715			clocks = <&rpmcc RPM_SMD_LN_BB_CLK>;
716			clock-names = "cxo2";
717		};
718
719		tsens0: thermal-sensor@4a9000 {
720			compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
721			reg = <0x004a9000 0x1000>, /* TM */
722			      <0x004a8000 0x1000>; /* SROT */
723			#qcom,sensors = <13>;
724			interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
725				     <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
726			interrupt-names = "uplow", "critical";
727			#thermal-sensor-cells = <1>;
728		};
729
730		tsens1: thermal-sensor@4ad000 {
731			compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
732			reg = <0x004ad000 0x1000>, /* TM */
733			      <0x004ac000 0x1000>; /* SROT */
734			#qcom,sensors = <8>;
735			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
736				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
737			interrupt-names = "uplow", "critical";
738			#thermal-sensor-cells = <1>;
739		};
740
741		tcsr_mutex_regs: syscon@740000 {
742			compatible = "syscon";
743			reg = <0x00740000 0x40000>;
744		};
745
746		tcsr: syscon@7a0000 {
747			compatible = "qcom,tcsr-msm8996", "syscon";
748			reg = <0x007a0000 0x18000>;
749		};
750
751		mmcc: clock-controller@8c0000 {
752			compatible = "qcom,mmcc-msm8996";
753			#clock-cells = <1>;
754			#reset-cells = <1>;
755			#power-domain-cells = <1>;
756			reg = <0x008c0000 0x40000>;
757			assigned-clocks = <&mmcc MMPLL9_PLL>,
758					  <&mmcc MMPLL1_PLL>,
759					  <&mmcc MMPLL3_PLL>,
760					  <&mmcc MMPLL4_PLL>,
761					  <&mmcc MMPLL5_PLL>;
762			assigned-clock-rates = <624000000>,
763					       <810000000>,
764					       <980000000>,
765					       <960000000>,
766					       <825000000>;
767		};
768
769		mdss: mdss@900000 {
770			compatible = "qcom,mdss";
771
772			reg = <0x00900000 0x1000>,
773			      <0x009b0000 0x1040>,
774			      <0x009b8000 0x1040>;
775			reg-names = "mdss_phys",
776				    "vbif_phys",
777				    "vbif_nrt_phys";
778
779			power-domains = <&mmcc MDSS_GDSC>;
780			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
781
782			interrupt-controller;
783			#interrupt-cells = <1>;
784
785			clocks = <&mmcc MDSS_AHB_CLK>;
786			clock-names = "iface";
787
788			#address-cells = <1>;
789			#size-cells = <1>;
790			ranges;
791
792			status = "disabled";
793
794			mdp: mdp@901000 {
795				compatible = "qcom,mdp5";
796				reg = <0x00901000 0x90000>;
797				reg-names = "mdp_phys";
798
799				interrupt-parent = <&mdss>;
800				interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
801
802				clocks = <&mmcc MDSS_AHB_CLK>,
803					 <&mmcc MDSS_AXI_CLK>,
804					 <&mmcc MDSS_MDP_CLK>,
805					 <&mmcc SMMU_MDP_AXI_CLK>,
806					 <&mmcc MDSS_VSYNC_CLK>;
807				clock-names = "iface",
808					      "bus",
809					      "core",
810					      "iommu",
811					      "vsync";
812
813				iommus = <&mdp_smmu 0>;
814
815				assigned-clocks = <&mmcc MDSS_MDP_CLK>,
816					 <&mmcc MDSS_VSYNC_CLK>;
817				assigned-clock-rates = <300000000>,
818					 <19200000>;
819
820				ports {
821					#address-cells = <1>;
822					#size-cells = <0>;
823
824					port@0 {
825						reg = <0>;
826						mdp5_intf3_out: endpoint {
827							remote-endpoint = <&hdmi_in>;
828						};
829					};
830
831					port@1 {
832						reg = <1>;
833						mdp5_intf1_out: endpoint {
834							remote-endpoint = <&dsi0_in>;
835						};
836					};
837				};
838			};
839
840			dsi0: dsi@994000 {
841				compatible = "qcom,mdss-dsi-ctrl";
842				reg = <0x00994000 0x400>;
843				reg-names = "dsi_ctrl";
844
845				interrupt-parent = <&mdss>;
846				interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
847
848				clocks = <&mmcc MDSS_MDP_CLK>,
849					 <&mmcc MDSS_BYTE0_CLK>,
850					 <&mmcc MDSS_AHB_CLK>,
851					 <&mmcc MDSS_AXI_CLK>,
852					 <&mmcc MMSS_MISC_AHB_CLK>,
853					 <&mmcc MDSS_PCLK0_CLK>,
854					 <&mmcc MDSS_ESC0_CLK>;
855				clock-names = "mdp_core",
856					      "byte",
857					      "iface",
858					      "bus",
859					      "core_mmss",
860					      "pixel",
861					      "core";
862
863				phys = <&dsi0_phy>;
864				phy-names = "dsi";
865				status = "disabled";
866
867				#address-cells = <1>;
868				#size-cells = <0>;
869
870				ports {
871					#address-cells = <1>;
872					#size-cells = <0>;
873
874					port@0 {
875						reg = <0>;
876						dsi0_in: endpoint {
877							remote-endpoint = <&mdp5_intf1_out>;
878						};
879					};
880
881					port@1 {
882						reg = <1>;
883						dsi0_out: endpoint {
884						};
885					};
886				};
887			};
888
889			dsi0_phy: dsi-phy@994400 {
890				compatible = "qcom,dsi-phy-14nm";
891				reg = <0x00994400 0x100>,
892				      <0x00994500 0x300>,
893				      <0x00994800 0x188>;
894				reg-names = "dsi_phy",
895					    "dsi_phy_lane",
896					    "dsi_pll";
897
898				#clock-cells = <1>;
899				#phy-cells = <0>;
900
901				clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
902				clock-names = "iface", "ref";
903				status = "disabled";
904			};
905
906			hdmi: hdmi-tx@9a0000 {
907				compatible = "qcom,hdmi-tx-8996";
908				reg =	<0x009a0000 0x50c>,
909					<0x00070000 0x6158>,
910					<0x009e0000 0xfff>;
911				reg-names = "core_physical",
912					    "qfprom_physical",
913					    "hdcp_physical";
914
915				interrupt-parent = <&mdss>;
916				interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
917
918				clocks = <&mmcc MDSS_MDP_CLK>,
919					 <&mmcc MDSS_AHB_CLK>,
920					 <&mmcc MDSS_HDMI_CLK>,
921					 <&mmcc MDSS_HDMI_AHB_CLK>,
922					 <&mmcc MDSS_EXTPCLK_CLK>;
923				clock-names =
924					"mdp_core",
925					"iface",
926					"core",
927					"alt_iface",
928					"extp";
929
930				phys = <&hdmi_phy>;
931				phy-names = "hdmi_phy";
932				#sound-dai-cells = <1>;
933
934				status = "disabled";
935
936				ports {
937					#address-cells = <1>;
938					#size-cells = <0>;
939
940					port@0 {
941						reg = <0>;
942						hdmi_in: endpoint {
943							remote-endpoint = <&mdp5_intf3_out>;
944						};
945					};
946				};
947			};
948
949			hdmi_phy: hdmi-phy@9a0600 {
950				#phy-cells = <0>;
951				compatible = "qcom,hdmi-phy-8996";
952				reg = <0x009a0600 0x1c4>,
953				      <0x009a0a00 0x124>,
954				      <0x009a0c00 0x124>,
955				      <0x009a0e00 0x124>,
956				      <0x009a1000 0x124>,
957				      <0x009a1200 0x0c8>;
958				reg-names = "hdmi_pll",
959					    "hdmi_tx_l0",
960					    "hdmi_tx_l1",
961					    "hdmi_tx_l2",
962					    "hdmi_tx_l3",
963					    "hdmi_phy";
964
965				clocks = <&mmcc MDSS_AHB_CLK>,
966					 <&gcc GCC_HDMI_CLKREF_CLK>;
967				clock-names = "iface",
968					      "ref";
969
970				status = "disabled";
971			};
972		};
973
974		gpu: gpu@b00000 {
975			compatible = "qcom,adreno-530.2", "qcom,adreno";
976			#stream-id-cells = <16>;
977
978			reg = <0x00b00000 0x3f000>;
979			reg-names = "kgsl_3d0_reg_memory";
980
981			interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
982
983			clocks = <&mmcc GPU_GX_GFX3D_CLK>,
984				<&mmcc GPU_AHB_CLK>,
985				<&mmcc GPU_GX_RBBMTIMER_CLK>,
986				<&gcc GCC_BIMC_GFX_CLK>,
987				<&gcc GCC_MMSS_BIMC_GFX_CLK>;
988
989			clock-names = "core",
990				"iface",
991				"rbbmtimer",
992				"mem",
993				"mem_iface";
994
995			power-domains = <&mmcc GPU_GX_GDSC>;
996			iommus = <&adreno_smmu 0>;
997
998			nvmem-cells = <&speedbin_efuse>;
999			nvmem-cell-names = "speed_bin";
1000
1001			operating-points-v2 = <&gpu_opp_table>;
1002
1003			status = "disabled";
1004
1005			#cooling-cells = <2>;
1006
1007			gpu_opp_table: opp-table {
1008				compatible  ="operating-points-v2";
1009
1010				/*
1011				 * 624Mhz is only available on speed bins 0 and 3.
1012				 * 560Mhz is only available on speed bins 0, 2 and 3.
1013				 * All the rest are available on all bins of the hardware.
1014				 */
1015				opp-624000000 {
1016					opp-hz = /bits/ 64 <624000000>;
1017					opp-supported-hw = <0x09>;
1018				};
1019				opp-560000000 {
1020					opp-hz = /bits/ 64 <560000000>;
1021					opp-supported-hw = <0x0d>;
1022				};
1023				opp-510000000 {
1024					opp-hz = /bits/ 64 <510000000>;
1025					opp-supported-hw = <0xFF>;
1026				};
1027				opp-401800000 {
1028					opp-hz = /bits/ 64 <401800000>;
1029					opp-supported-hw = <0xFF>;
1030				};
1031				opp-315000000 {
1032					opp-hz = /bits/ 64 <315000000>;
1033					opp-supported-hw = <0xFF>;
1034				};
1035				opp-214000000 {
1036					opp-hz = /bits/ 64 <214000000>;
1037					opp-supported-hw = <0xFF>;
1038				};
1039				opp-133000000 {
1040					opp-hz = /bits/ 64 <133000000>;
1041					opp-supported-hw = <0xFF>;
1042				};
1043			};
1044
1045			zap-shader {
1046				memory-region = <&zap_shader_region>;
1047			};
1048		};
1049
1050		tlmm: pinctrl@1010000 {
1051			compatible = "qcom,msm8996-pinctrl";
1052			reg = <0x01010000 0x300000>;
1053			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1054			gpio-controller;
1055			gpio-ranges = <&tlmm 0 0 150>;
1056			#gpio-cells = <2>;
1057			interrupt-controller;
1058			#interrupt-cells = <2>;
1059
1060			blsp1_spi1_default: blsp1-spi1-default {
1061				spi {
1062					pins = "gpio0", "gpio1", "gpio3";
1063					function = "blsp_spi1";
1064					drive-strength = <12>;
1065					bias-disable;
1066				};
1067
1068				cs {
1069					pins = "gpio2";
1070					function = "gpio";
1071					drive-strength = <16>;
1072					bias-disable;
1073					output-high;
1074				};
1075			};
1076
1077			blsp1_spi1_sleep: blsp1-spi1-sleep {
1078				pins = "gpio0", "gpio1", "gpio2", "gpio3";
1079				function = "gpio";
1080				drive-strength = <2>;
1081				bias-pull-down;
1082			};
1083
1084			blsp2_uart2_2pins_default: blsp2-uart1-2pins {
1085				pins = "gpio4", "gpio5";
1086				function = "blsp_uart8";
1087				drive-strength = <16>;
1088				bias-disable;
1089			};
1090
1091			blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep {
1092				pins = "gpio4", "gpio5";
1093				function = "gpio";
1094				drive-strength = <2>;
1095				bias-disable;
1096			};
1097
1098			blsp2_i2c2_default: blsp2-i2c2 {
1099				pins = "gpio6", "gpio7";
1100				function = "blsp_i2c8";
1101				drive-strength = <16>;
1102				bias-disable;
1103			};
1104
1105			blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1106				pins = "gpio6", "gpio7";
1107				function = "gpio";
1108				drive-strength = <2>;
1109				bias-disable;
1110			};
1111
1112			cci0_default: cci0-default {
1113				pins = "gpio17", "gpio18";
1114				function = "cci_i2c";
1115				drive-strength = <16>;
1116				bias-disable;
1117			};
1118
1119			camera0_state_on:
1120			camera_rear_default: camera-rear-default {
1121				camera0_mclk: mclk0 {
1122					pins = "gpio13";
1123					function = "cam_mclk";
1124					drive-strength = <16>;
1125					bias-disable;
1126				};
1127
1128				camera0_rst: rst {
1129					pins = "gpio25";
1130					function = "gpio";
1131					drive-strength = <16>;
1132					bias-disable;
1133				};
1134
1135				camera0_pwdn: pwdn {
1136					pins = "gpio26";
1137					function = "gpio";
1138					drive-strength = <16>;
1139					bias-disable;
1140				};
1141			};
1142
1143			cci1_default: cci1-default {
1144				pins = "gpio19", "gpio20";
1145				function = "cci_i2c";
1146				drive-strength = <16>;
1147				bias-disable;
1148			};
1149
1150			camera1_state_on:
1151			camera_board_default: camera-board-default {
1152				mclk1 {
1153					pins = "gpio14";
1154					function = "cam_mclk";
1155					drive-strength = <16>;
1156					bias-disable;
1157				};
1158
1159				pwdn {
1160					pins = "gpio98";
1161					function = "gpio";
1162					drive-strength = <16>;
1163					bias-disable;
1164				};
1165
1166				rst {
1167					pins = "gpio104";
1168					function = "gpio";
1169					drive-strength = <16>;
1170					bias-disable;
1171				};
1172			};
1173
1174			camera2_state_on:
1175			camera_front_default: camera-front-default {
1176				camera2_mclk: mclk2 {
1177					pins = "gpio15";
1178					function = "cam_mclk";
1179					drive-strength = <16>;
1180					bias-disable;
1181				};
1182
1183				camera2_rst: rst {
1184					pins = "gpio23";
1185					function = "gpio";
1186					drive-strength = <16>;
1187					bias-disable;
1188				};
1189
1190				pwdn {
1191					pins = "gpio133";
1192					function = "gpio";
1193					drive-strength = <16>;
1194					bias-disable;
1195				};
1196			};
1197
1198			pcie0_state_on: pcie0-state-on {
1199				perst {
1200					pins = "gpio35";
1201					function = "gpio";
1202					drive-strength = <2>;
1203					bias-pull-down;
1204				};
1205
1206				clkreq {
1207					pins = "gpio36";
1208					function = "pci_e0";
1209					drive-strength = <2>;
1210					bias-pull-up;
1211				};
1212
1213				wake {
1214					pins = "gpio37";
1215					function = "gpio";
1216					drive-strength = <2>;
1217					bias-pull-up;
1218				};
1219			};
1220
1221			pcie0_state_off: pcie0-state-off {
1222				perst {
1223					pins = "gpio35";
1224					function = "gpio";
1225					drive-strength = <2>;
1226					bias-pull-down;
1227				};
1228
1229				clkreq {
1230					pins = "gpio36";
1231					function = "gpio";
1232					drive-strength = <2>;
1233					bias-disable;
1234				};
1235
1236				wake {
1237					pins = "gpio37";
1238					function = "gpio";
1239					drive-strength = <2>;
1240					bias-disable;
1241				};
1242			};
1243
1244			blsp1_uart2_default: blsp1-uart2-default {
1245				pins = "gpio41", "gpio42", "gpio43", "gpio44";
1246				function = "blsp_uart2";
1247				drive-strength = <16>;
1248				bias-disable;
1249			};
1250
1251			blsp1_uart2_sleep: blsp1-uart2-sleep {
1252				pins = "gpio41", "gpio42", "gpio43", "gpio44";
1253				function = "gpio";
1254				drive-strength = <2>;
1255				bias-disable;
1256			};
1257
1258			blsp1_i2c3_default: blsp1-i2c2-default {
1259				pins = "gpio47", "gpio48";
1260				function = "blsp_i2c3";
1261				drive-strength = <16>;
1262				bias-disable = <0>;
1263			};
1264
1265			blsp1_i2c3_sleep: blsp1-i2c2-sleep {
1266				pins = "gpio47", "gpio48";
1267				function = "gpio";
1268				drive-strength = <2>;
1269				bias-disable = <0>;
1270			};
1271
1272			blsp2_uart3_4pins_default: blsp2-uart2-4pins {
1273				pins = "gpio49", "gpio50", "gpio51", "gpio52";
1274				function = "blsp_uart9";
1275				drive-strength = <16>;
1276				bias-disable;
1277			};
1278
1279			blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep {
1280				pins = "gpio49", "gpio50", "gpio51", "gpio52";
1281				function = "blsp_uart9";
1282				drive-strength = <2>;
1283				bias-disable;
1284			};
1285
1286			wcd_intr_default: wcd-intr-default{
1287				pins = "gpio54";
1288				function = "gpio";
1289				drive-strength = <2>;
1290				bias-pull-down;
1291				input-enable;
1292			};
1293
1294			blsp2_i2c1_default: blsp2-i2c1 {
1295				pins = "gpio55", "gpio56";
1296				function = "blsp_i2c7";
1297				drive-strength = <16>;
1298				bias-disable;
1299			};
1300
1301			blsp2_i2c1_sleep: blsp2-i2c0-sleep {
1302				pins = "gpio55", "gpio56";
1303				function = "gpio";
1304				drive-strength = <2>;
1305				bias-disable;
1306			};
1307
1308			blsp2_i2c5_default: blsp2-i2c5 {
1309				pins = "gpio60", "gpio61";
1310				function = "blsp_i2c11";
1311				drive-strength = <2>;
1312				bias-disable;
1313			};
1314
1315			/* Sleep state for BLSP2_I2C5 is missing.. */
1316
1317			cdc_reset_active: cdc-reset-active {
1318				pins = "gpio64";
1319				function = "gpio";
1320				drive-strength = <16>;
1321				bias-pull-down;
1322				output-high;
1323			};
1324
1325			cdc_reset_sleep: cdc-reset-sleep {
1326				pins = "gpio64";
1327				function = "gpio";
1328				drive-strength = <16>;
1329				bias-disable;
1330				output-low;
1331			};
1332
1333			blsp2_spi6_default: blsp2-spi5-default {
1334				spi {
1335					pins = "gpio85", "gpio86", "gpio88";
1336					function = "blsp_spi12";
1337					drive-strength = <12>;
1338					bias-disable;
1339				};
1340
1341				cs {
1342					pins = "gpio87";
1343					function = "gpio";
1344					drive-strength = <16>;
1345					bias-disable;
1346					output-high;
1347				};
1348			};
1349
1350			blsp2_spi6_sleep: blsp2-spi5-sleep {
1351				pins = "gpio85", "gpio86", "gpio87", "gpio88";
1352				function = "gpio";
1353				drive-strength = <2>;
1354				bias-pull-down;
1355			};
1356
1357			blsp2_i2c6_default: blsp2-i2c6 {
1358				pins = "gpio87", "gpio88";
1359				function = "blsp_i2c12";
1360				drive-strength = <16>;
1361				bias-disable;
1362			};
1363
1364			blsp2_i2c6_sleep: blsp2-i2c6-sleep {
1365				pins = "gpio87", "gpio88";
1366				function = "gpio";
1367				drive-strength = <2>;
1368				bias-disable;
1369			};
1370
1371			pcie1_state_on: pcie1-state-on {
1372				perst {
1373					pins = "gpio130";
1374					function = "gpio";
1375					drive-strength = <2>;
1376					bias-pull-down;
1377				};
1378
1379				clkreq {
1380					pins = "gpio131";
1381					function = "pci_e1";
1382					drive-strength = <2>;
1383					bias-pull-up;
1384				};
1385
1386				wake {
1387					pins = "gpio132";
1388					function = "gpio";
1389					drive-strength = <2>;
1390					bias-pull-down;
1391				};
1392			};
1393
1394			pcie1_state_off: pcie1-state-off {
1395				/* Perst is missing? */
1396				clkreq {
1397					pins = "gpio131";
1398					function = "gpio";
1399					drive-strength = <2>;
1400					bias-disable;
1401				};
1402
1403				wake {
1404					pins = "gpio132";
1405					function = "gpio";
1406					drive-strength = <2>;
1407					bias-disable;
1408				};
1409			};
1410
1411			pcie2_state_on: pcie2-state-on {
1412				perst {
1413					pins = "gpio114";
1414					function = "gpio";
1415					drive-strength = <2>;
1416					bias-pull-down;
1417				};
1418
1419				clkreq {
1420					pins = "gpio115";
1421					function = "pci_e2";
1422					drive-strength = <2>;
1423					bias-pull-up;
1424				};
1425
1426				wake {
1427					pins = "gpio116";
1428					function = "gpio";
1429					drive-strength = <2>;
1430					bias-pull-down;
1431				};
1432			};
1433
1434			pcie2_state_off: pcie2-state-off {
1435				/* Perst is missing? */
1436				clkreq {
1437					pins = "gpio115";
1438					function = "gpio";
1439					drive-strength = <2>;
1440					bias-disable;
1441				};
1442
1443				wake {
1444					pins = "gpio116";
1445					function = "gpio";
1446					drive-strength = <2>;
1447					bias-disable;
1448				};
1449			};
1450
1451			sdc1_state_on: sdc1-state-on {
1452				clk {
1453					pins = "sdc1_clk";
1454					bias-disable;
1455					drive-strength = <16>;
1456				};
1457
1458				cmd {
1459					pins = "sdc1_cmd";
1460					bias-pull-up;
1461					drive-strength = <10>;
1462				};
1463
1464				data {
1465					pins = "sdc1_data";
1466					bias-pull-up;
1467					drive-strength = <10>;
1468				};
1469
1470				rclk {
1471					pins = "sdc1_rclk";
1472					bias-pull-down;
1473				};
1474			};
1475
1476			sdc1_state_off: sdc1-state-off {
1477				clk {
1478					pins = "sdc1_clk";
1479					bias-disable;
1480					drive-strength = <2>;
1481				};
1482
1483				cmd {
1484					pins = "sdc1_cmd";
1485					bias-pull-up;
1486					drive-strength = <2>;
1487				};
1488
1489				data {
1490					pins = "sdc1_data";
1491					bias-pull-up;
1492					drive-strength = <2>;
1493				};
1494
1495				rclk {
1496					pins = "sdc1_rclk";
1497					bias-pull-down;
1498				};
1499			};
1500
1501			sdc2_state_on: sdc2-clk-on {
1502				clk {
1503					pins = "sdc2_clk";
1504					bias-disable;
1505					drive-strength = <16>;
1506				};
1507
1508				cmd {
1509					pins = "sdc2_cmd";
1510					bias-pull-up;
1511					drive-strength = <10>;
1512				};
1513
1514				data {
1515					pins = "sdc2_data";
1516					bias-pull-up;
1517					drive-strength = <10>;
1518				};
1519			};
1520
1521			sdc2_state_off: sdc2-clk-off {
1522				clk {
1523					pins = "sdc2_clk";
1524					bias-disable;
1525					drive-strength = <2>;
1526				};
1527
1528				cmd {
1529					pins = "sdc2_cmd";
1530					bias-pull-up;
1531					drive-strength = <2>;
1532				};
1533
1534				data {
1535					pins = "sdc2_data";
1536					bias-pull-up;
1537					drive-strength = <2>;
1538				};
1539			};
1540		};
1541
1542		spmi_bus: qcom,spmi@400f000 {
1543			compatible = "qcom,spmi-pmic-arb";
1544			reg = <0x0400f000 0x1000>,
1545			      <0x04400000 0x800000>,
1546			      <0x04c00000 0x800000>,
1547			      <0x05800000 0x200000>,
1548			      <0x0400a000 0x002100>;
1549			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1550			interrupt-names = "periph_irq";
1551			interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1552			qcom,ee = <0>;
1553			qcom,channel = <0>;
1554			#address-cells = <2>;
1555			#size-cells = <0>;
1556			interrupt-controller;
1557			#interrupt-cells = <4>;
1558		};
1559
1560		agnoc@0 {
1561			power-domains = <&gcc AGGRE0_NOC_GDSC>;
1562			compatible = "simple-pm-bus";
1563			#address-cells = <1>;
1564			#size-cells = <1>;
1565			ranges;
1566
1567			pcie0: pcie@600000 {
1568				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1569				status = "disabled";
1570				power-domains = <&gcc PCIE0_GDSC>;
1571				bus-range = <0x00 0xff>;
1572				num-lanes = <1>;
1573
1574				reg = <0x00600000 0x2000>,
1575				      <0x0c000000 0xf1d>,
1576				      <0x0c000f20 0xa8>,
1577				      <0x0c100000 0x100000>;
1578				reg-names = "parf", "dbi", "elbi","config";
1579
1580				phys = <&pciephy_0>;
1581				phy-names = "pciephy";
1582
1583				#address-cells = <3>;
1584				#size-cells = <2>;
1585				ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>,
1586					 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1587
1588				device_type = "pci";
1589
1590				interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
1591				interrupt-names = "msi";
1592				#interrupt-cells = <1>;
1593				interrupt-map-mask = <0 0 0 0x7>;
1594				interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1595						<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1596						<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1597						<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1598
1599				pinctrl-names = "default", "sleep";
1600				pinctrl-0 = <&pcie0_state_on>;
1601				pinctrl-1 = <&pcie0_state_off>;
1602
1603				linux,pci-domain = <0>;
1604
1605				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1606					<&gcc GCC_PCIE_0_AUX_CLK>,
1607					<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1608					<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1609					<&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1610
1611				clock-names =  "pipe",
1612						"aux",
1613						"cfg",
1614						"bus_master",
1615						"bus_slave";
1616
1617			};
1618
1619			pcie1: pcie@608000 {
1620				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1621				power-domains = <&gcc PCIE1_GDSC>;
1622				bus-range = <0x00 0xff>;
1623				num-lanes = <1>;
1624
1625				status  = "disabled";
1626
1627				reg = <0x00608000 0x2000>,
1628				      <0x0d000000 0xf1d>,
1629				      <0x0d000f20 0xa8>,
1630				      <0x0d100000 0x100000>;
1631
1632				reg-names = "parf", "dbi", "elbi","config";
1633
1634				phys = <&pciephy_1>;
1635				phy-names = "pciephy";
1636
1637				#address-cells = <3>;
1638				#size-cells = <2>;
1639				ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>,
1640					 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1641
1642				device_type = "pci";
1643
1644				interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1645				interrupt-names = "msi";
1646				#interrupt-cells = <1>;
1647				interrupt-map-mask = <0 0 0 0x7>;
1648				interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1649						<0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1650						<0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1651						<0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1652
1653				pinctrl-names = "default", "sleep";
1654				pinctrl-0 = <&pcie1_state_on>;
1655				pinctrl-1 = <&pcie1_state_off>;
1656
1657				linux,pci-domain = <1>;
1658
1659				clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1660					<&gcc GCC_PCIE_1_AUX_CLK>,
1661					<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1662					<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1663					<&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1664
1665				clock-names =  "pipe",
1666						"aux",
1667						"cfg",
1668						"bus_master",
1669						"bus_slave";
1670			};
1671
1672			pcie2: pcie@610000 {
1673				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1674				power-domains = <&gcc PCIE2_GDSC>;
1675				bus-range = <0x00 0xff>;
1676				num-lanes = <1>;
1677				status = "disabled";
1678				reg = <0x00610000 0x2000>,
1679				      <0x0e000000 0xf1d>,
1680				      <0x0e000f20 0xa8>,
1681				      <0x0e100000 0x100000>;
1682
1683				reg-names = "parf", "dbi", "elbi","config";
1684
1685				phys = <&pciephy_2>;
1686				phy-names = "pciephy";
1687
1688				#address-cells = <3>;
1689				#size-cells = <2>;
1690				ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>,
1691					 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
1692
1693				device_type = "pci";
1694
1695				interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1696				interrupt-names = "msi";
1697				#interrupt-cells = <1>;
1698				interrupt-map-mask = <0 0 0 0x7>;
1699				interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1700						<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1701						<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1702						<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1703
1704				pinctrl-names = "default", "sleep";
1705				pinctrl-0 = <&pcie2_state_on>;
1706				pinctrl-1 = <&pcie2_state_off>;
1707
1708				linux,pci-domain = <2>;
1709				clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1710					<&gcc GCC_PCIE_2_AUX_CLK>,
1711					<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1712					<&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
1713					<&gcc GCC_PCIE_2_SLV_AXI_CLK>;
1714
1715				clock-names =  "pipe",
1716						"aux",
1717						"cfg",
1718						"bus_master",
1719						"bus_slave";
1720			};
1721		};
1722
1723		ufshc: ufshc@624000 {
1724			compatible = "qcom,ufshc";
1725			reg = <0x00624000 0x2500>;
1726			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1727
1728			phys = <&ufsphy_lane>;
1729			phy-names = "ufsphy";
1730
1731			power-domains = <&gcc UFS_GDSC>;
1732
1733			clock-names =
1734				"core_clk_src",
1735				"core_clk",
1736				"bus_clk",
1737				"bus_aggr_clk",
1738				"iface_clk",
1739				"core_clk_unipro_src",
1740				"core_clk_unipro",
1741				"core_clk_ice",
1742				"ref_clk",
1743				"tx_lane0_sync_clk",
1744				"rx_lane0_sync_clk";
1745			clocks =
1746				<&gcc UFS_AXI_CLK_SRC>,
1747				<&gcc GCC_UFS_AXI_CLK>,
1748				<&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
1749				<&gcc GCC_AGGRE2_UFS_AXI_CLK>,
1750				<&gcc GCC_UFS_AHB_CLK>,
1751				<&gcc UFS_ICE_CORE_CLK_SRC>,
1752				<&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1753				<&gcc GCC_UFS_ICE_CORE_CLK>,
1754				<&rpmcc RPM_SMD_LN_BB_CLK>,
1755				<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1756				<&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
1757			freq-table-hz =
1758				<100000000 200000000>,
1759				<0 0>,
1760				<0 0>,
1761				<0 0>,
1762				<0 0>,
1763				<150000000 300000000>,
1764				<0 0>,
1765				<0 0>,
1766				<0 0>,
1767				<0 0>,
1768				<0 0>;
1769
1770			lanes-per-direction = <1>;
1771			#reset-cells = <1>;
1772			status = "disabled";
1773
1774			ufs_variant {
1775				compatible = "qcom,ufs_variant";
1776			};
1777		};
1778
1779		ufsphy: phy@627000 {
1780			compatible = "qcom,msm8996-qmp-ufs-phy";
1781			reg = <0x00627000 0x1c4>;
1782			#address-cells = <1>;
1783			#size-cells = <1>;
1784			ranges;
1785
1786			clocks = <&gcc GCC_UFS_CLKREF_CLK>;
1787			clock-names = "ref";
1788
1789			resets = <&ufshc 0>;
1790			reset-names = "ufsphy";
1791			status = "disabled";
1792
1793			ufsphy_lane: phy@627400 {
1794				reg = <0x627400 0x12c>,
1795				      <0x627600 0x200>,
1796				      <0x627c00 0x1b4>;
1797				#phy-cells = <0>;
1798			};
1799		};
1800
1801		camss: camss@a34000 {
1802			compatible = "qcom,msm8996-camss";
1803			reg = <0x00a34000 0x1000>,
1804			      <0x00a00030 0x4>,
1805			      <0x00a35000 0x1000>,
1806			      <0x00a00038 0x4>,
1807			      <0x00a36000 0x1000>,
1808			      <0x00a00040 0x4>,
1809			      <0x00a30000 0x100>,
1810			      <0x00a30400 0x100>,
1811			      <0x00a30800 0x100>,
1812			      <0x00a30c00 0x100>,
1813			      <0x00a31000 0x500>,
1814			      <0x00a00020 0x10>,
1815			      <0x00a10000 0x1000>,
1816			      <0x00a14000 0x1000>;
1817			reg-names = "csiphy0",
1818				"csiphy0_clk_mux",
1819				"csiphy1",
1820				"csiphy1_clk_mux",
1821				"csiphy2",
1822				"csiphy2_clk_mux",
1823				"csid0",
1824				"csid1",
1825				"csid2",
1826				"csid3",
1827				"ispif",
1828				"csi_clk_mux",
1829				"vfe0",
1830				"vfe1";
1831			interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1832				<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1833				<GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
1834				<GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
1835				<GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
1836				<GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
1837				<GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
1838				<GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
1839				<GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
1840				<GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
1841			interrupt-names = "csiphy0",
1842				"csiphy1",
1843				"csiphy2",
1844				"csid0",
1845				"csid1",
1846				"csid2",
1847				"csid3",
1848				"ispif",
1849				"vfe0",
1850				"vfe1";
1851			power-domains = <&mmcc VFE0_GDSC>,
1852					<&mmcc VFE1_GDSC>;
1853			clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1854				<&mmcc CAMSS_ISPIF_AHB_CLK>,
1855				<&mmcc CAMSS_CSI0PHYTIMER_CLK>,
1856				<&mmcc CAMSS_CSI1PHYTIMER_CLK>,
1857				<&mmcc CAMSS_CSI2PHYTIMER_CLK>,
1858				<&mmcc CAMSS_CSI0_AHB_CLK>,
1859				<&mmcc CAMSS_CSI0_CLK>,
1860				<&mmcc CAMSS_CSI0PHY_CLK>,
1861				<&mmcc CAMSS_CSI0PIX_CLK>,
1862				<&mmcc CAMSS_CSI0RDI_CLK>,
1863				<&mmcc CAMSS_CSI1_AHB_CLK>,
1864				<&mmcc CAMSS_CSI1_CLK>,
1865				<&mmcc CAMSS_CSI1PHY_CLK>,
1866				<&mmcc CAMSS_CSI1PIX_CLK>,
1867				<&mmcc CAMSS_CSI1RDI_CLK>,
1868				<&mmcc CAMSS_CSI2_AHB_CLK>,
1869				<&mmcc CAMSS_CSI2_CLK>,
1870				<&mmcc CAMSS_CSI2PHY_CLK>,
1871				<&mmcc CAMSS_CSI2PIX_CLK>,
1872				<&mmcc CAMSS_CSI2RDI_CLK>,
1873				<&mmcc CAMSS_CSI3_AHB_CLK>,
1874				<&mmcc CAMSS_CSI3_CLK>,
1875				<&mmcc CAMSS_CSI3PHY_CLK>,
1876				<&mmcc CAMSS_CSI3PIX_CLK>,
1877				<&mmcc CAMSS_CSI3RDI_CLK>,
1878				<&mmcc CAMSS_AHB_CLK>,
1879				<&mmcc CAMSS_VFE0_CLK>,
1880				<&mmcc CAMSS_CSI_VFE0_CLK>,
1881				<&mmcc CAMSS_VFE0_AHB_CLK>,
1882				<&mmcc CAMSS_VFE0_STREAM_CLK>,
1883				<&mmcc CAMSS_VFE1_CLK>,
1884				<&mmcc CAMSS_CSI_VFE1_CLK>,
1885				<&mmcc CAMSS_VFE1_AHB_CLK>,
1886				<&mmcc CAMSS_VFE1_STREAM_CLK>,
1887				<&mmcc CAMSS_VFE_AHB_CLK>,
1888				<&mmcc CAMSS_VFE_AXI_CLK>;
1889			clock-names = "top_ahb",
1890				"ispif_ahb",
1891				"csiphy0_timer",
1892				"csiphy1_timer",
1893				"csiphy2_timer",
1894				"csi0_ahb",
1895				"csi0",
1896				"csi0_phy",
1897				"csi0_pix",
1898				"csi0_rdi",
1899				"csi1_ahb",
1900				"csi1",
1901				"csi1_phy",
1902				"csi1_pix",
1903				"csi1_rdi",
1904				"csi2_ahb",
1905				"csi2",
1906				"csi2_phy",
1907				"csi2_pix",
1908				"csi2_rdi",
1909				"csi3_ahb",
1910				"csi3",
1911				"csi3_phy",
1912				"csi3_pix",
1913				"csi3_rdi",
1914				"ahb",
1915				"vfe0",
1916				"csi_vfe0",
1917				"vfe0_ahb",
1918				"vfe0_stream",
1919				"vfe1",
1920				"csi_vfe1",
1921				"vfe1_ahb",
1922				"vfe1_stream",
1923				"vfe_ahb",
1924				"vfe_axi";
1925			iommus = <&vfe_smmu 0>,
1926				 <&vfe_smmu 1>,
1927				 <&vfe_smmu 2>,
1928				 <&vfe_smmu 3>;
1929			status = "disabled";
1930			ports {
1931				#address-cells = <1>;
1932				#size-cells = <0>;
1933			};
1934		};
1935
1936		cci: cci@a0c000 {
1937			compatible = "qcom,msm8996-cci";
1938			#address-cells = <1>;
1939			#size-cells = <0>;
1940			reg = <0xa0c000 0x1000>;
1941			interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
1942			power-domains = <&mmcc CAMSS_GDSC>;
1943			clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1944				 <&mmcc CAMSS_CCI_AHB_CLK>,
1945				 <&mmcc CAMSS_CCI_CLK>,
1946				 <&mmcc CAMSS_AHB_CLK>;
1947			clock-names = "camss_top_ahb",
1948				      "cci_ahb",
1949				      "cci",
1950				      "camss_ahb";
1951			assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
1952					  <&mmcc CAMSS_CCI_CLK>;
1953			assigned-clock-rates = <80000000>, <37500000>;
1954			pinctrl-names = "default";
1955			pinctrl-0 = <&cci0_default &cci1_default>;
1956			status = "disabled";
1957
1958			cci_i2c0: i2c-bus@0 {
1959				reg = <0>;
1960				clock-frequency = <400000>;
1961				#address-cells = <1>;
1962				#size-cells = <0>;
1963			};
1964
1965			cci_i2c1: i2c-bus@1 {
1966				reg = <1>;
1967				clock-frequency = <400000>;
1968				#address-cells = <1>;
1969				#size-cells = <0>;
1970			};
1971		};
1972
1973		adreno_smmu: iommu@b40000 {
1974			compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
1975			reg = <0x00b40000 0x10000>;
1976
1977			#global-interrupts = <1>;
1978			interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1979				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1980				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1981			#iommu-cells = <1>;
1982
1983			clocks = <&mmcc GPU_AHB_CLK>,
1984				 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1985			clock-names = "iface", "bus";
1986
1987			power-domains = <&mmcc GPU_GDSC>;
1988		};
1989
1990		venus: video-codec@c00000 {
1991			compatible = "qcom,msm8996-venus";
1992			reg = <0x00c00000 0xff000>;
1993			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
1994			power-domains = <&mmcc VENUS_GDSC>;
1995			clocks = <&mmcc VIDEO_CORE_CLK>,
1996				 <&mmcc VIDEO_AHB_CLK>,
1997				 <&mmcc VIDEO_AXI_CLK>,
1998				 <&mmcc VIDEO_MAXI_CLK>;
1999			clock-names = "core", "iface", "bus", "mbus";
2000			iommus = <&venus_smmu 0x00>,
2001				 <&venus_smmu 0x01>,
2002				 <&venus_smmu 0x0a>,
2003				 <&venus_smmu 0x07>,
2004				 <&venus_smmu 0x0e>,
2005				 <&venus_smmu 0x0f>,
2006				 <&venus_smmu 0x08>,
2007				 <&venus_smmu 0x09>,
2008				 <&venus_smmu 0x0b>,
2009				 <&venus_smmu 0x0c>,
2010				 <&venus_smmu 0x0d>,
2011				 <&venus_smmu 0x10>,
2012				 <&venus_smmu 0x11>,
2013				 <&venus_smmu 0x21>,
2014				 <&venus_smmu 0x28>,
2015				 <&venus_smmu 0x29>,
2016				 <&venus_smmu 0x2b>,
2017				 <&venus_smmu 0x2c>,
2018				 <&venus_smmu 0x2d>,
2019				 <&venus_smmu 0x31>;
2020			memory-region = <&venus_region>;
2021			status = "disabled";
2022
2023			video-decoder {
2024				compatible = "venus-decoder";
2025				clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2026				clock-names = "core";
2027				power-domains = <&mmcc VENUS_CORE0_GDSC>;
2028			};
2029
2030			video-encoder {
2031				compatible = "venus-encoder";
2032				clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
2033				clock-names = "core";
2034				power-domains = <&mmcc VENUS_CORE1_GDSC>;
2035			};
2036		};
2037
2038		mdp_smmu: iommu@d00000 {
2039			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2040			reg = <0x00d00000 0x10000>;
2041
2042			#global-interrupts = <1>;
2043			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
2044				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2045				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
2046			#iommu-cells = <1>;
2047			clocks = <&mmcc SMMU_MDP_AHB_CLK>,
2048				 <&mmcc SMMU_MDP_AXI_CLK>;
2049			clock-names = "iface", "bus";
2050
2051			power-domains = <&mmcc MDSS_GDSC>;
2052		};
2053
2054		venus_smmu: iommu@d40000 {
2055			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2056			reg = <0x00d40000 0x20000>;
2057			#global-interrupts = <1>;
2058			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
2059				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2060				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2061				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2062				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2063				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2064				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2065				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
2066			power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2067			clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
2068				 <&mmcc SMMU_VIDEO_AXI_CLK>;
2069			clock-names = "iface", "bus";
2070			#iommu-cells = <1>;
2071			status = "okay";
2072		};
2073
2074		vfe_smmu: iommu@da0000 {
2075			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2076			reg = <0x00da0000 0x10000>;
2077
2078			#global-interrupts = <1>;
2079			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
2080				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2081				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
2082			power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2083			clocks = <&mmcc SMMU_VFE_AHB_CLK>,
2084				 <&mmcc SMMU_VFE_AXI_CLK>;
2085			clock-names = "iface",
2086				      "bus";
2087			#iommu-cells = <1>;
2088		};
2089
2090		lpass_q6_smmu: iommu@1600000 {
2091			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2092			reg = <0x01600000 0x20000>;
2093			#iommu-cells = <1>;
2094			power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2095
2096			#global-interrupts = <1>;
2097			interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2098		                <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
2099		                <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
2100		                <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
2101		                <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2102		                <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2103		                <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2104		                <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2105		                <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2106		                <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2107		                <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2108		                <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2109		                <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
2110
2111			clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
2112				 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
2113			clock-names = "iface", "bus";
2114		};
2115
2116		stm@3002000 {
2117			compatible = "arm,coresight-stm", "arm,primecell";
2118			reg = <0x3002000 0x1000>,
2119			      <0x8280000 0x180000>;
2120			reg-names = "stm-base", "stm-stimulus-base";
2121
2122			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2123			clock-names = "apb_pclk", "atclk";
2124
2125			out-ports {
2126				port {
2127					stm_out: endpoint {
2128						remote-endpoint =
2129						  <&funnel0_in>;
2130					};
2131				};
2132			};
2133		};
2134
2135		tpiu@3020000 {
2136			compatible = "arm,coresight-tpiu", "arm,primecell";
2137			reg = <0x3020000 0x1000>;
2138
2139			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2140			clock-names = "apb_pclk", "atclk";
2141
2142			in-ports {
2143				port {
2144					tpiu_in: endpoint {
2145						remote-endpoint =
2146						  <&replicator_out1>;
2147					};
2148				};
2149			};
2150		};
2151
2152		funnel@3021000 {
2153			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2154			reg = <0x3021000 0x1000>;
2155
2156			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2157			clock-names = "apb_pclk", "atclk";
2158
2159			in-ports {
2160				#address-cells = <1>;
2161				#size-cells = <0>;
2162
2163				port@7 {
2164					reg = <7>;
2165					funnel0_in: endpoint {
2166						remote-endpoint =
2167						  <&stm_out>;
2168					};
2169				};
2170			};
2171
2172			out-ports {
2173				port {
2174					funnel0_out: endpoint {
2175						remote-endpoint =
2176						  <&merge_funnel_in0>;
2177					};
2178				};
2179			};
2180		};
2181
2182		funnel@3022000 {
2183			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2184			reg = <0x3022000 0x1000>;
2185
2186			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2187			clock-names = "apb_pclk", "atclk";
2188
2189			in-ports {
2190				#address-cells = <1>;
2191				#size-cells = <0>;
2192
2193				port@6 {
2194					reg = <6>;
2195					funnel1_in: endpoint {
2196						remote-endpoint =
2197						  <&apss_merge_funnel_out>;
2198					};
2199				};
2200			};
2201
2202			out-ports {
2203				port {
2204					funnel1_out: endpoint {
2205						remote-endpoint =
2206						  <&merge_funnel_in1>;
2207					};
2208				};
2209			};
2210		};
2211
2212		funnel@3023000 {
2213			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2214			reg = <0x3023000 0x1000>;
2215
2216			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2217			clock-names = "apb_pclk", "atclk";
2218
2219			in-ports {
2220				port {
2221					funnel_in2_in_modem_etm: endpoint {
2222						remote-endpoint =
2223						  <&modem_etm_out_funnel_in2>;
2224					};
2225				};
2226			};
2227
2228			out-ports {
2229				port {
2230					funnel2_out: endpoint {
2231						remote-endpoint =
2232						  <&merge_funnel_in2>;
2233					};
2234				};
2235			};
2236		};
2237
2238		funnel@3025000 {
2239			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2240			reg = <0x3025000 0x1000>;
2241
2242			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2243			clock-names = "apb_pclk", "atclk";
2244
2245			in-ports {
2246				#address-cells = <1>;
2247				#size-cells = <0>;
2248
2249				port@0 {
2250					reg = <0>;
2251					merge_funnel_in0: endpoint {
2252						remote-endpoint =
2253						  <&funnel0_out>;
2254					};
2255				};
2256
2257				port@1 {
2258					reg = <1>;
2259					merge_funnel_in1: endpoint {
2260						remote-endpoint =
2261						  <&funnel1_out>;
2262					};
2263				};
2264
2265				port@2 {
2266					reg = <2>;
2267					merge_funnel_in2: endpoint {
2268						remote-endpoint =
2269						  <&funnel2_out>;
2270					};
2271				};
2272			};
2273
2274			out-ports {
2275				port {
2276					merge_funnel_out: endpoint {
2277						remote-endpoint =
2278						  <&etf_in>;
2279					};
2280				};
2281			};
2282		};
2283
2284		replicator@3026000 {
2285			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2286			reg = <0x3026000 0x1000>;
2287
2288			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2289			clock-names = "apb_pclk", "atclk";
2290
2291			in-ports {
2292				port {
2293					replicator_in: endpoint {
2294						remote-endpoint =
2295						  <&etf_out>;
2296					};
2297				};
2298			};
2299
2300			out-ports {
2301				#address-cells = <1>;
2302				#size-cells = <0>;
2303
2304				port@0 {
2305					reg = <0>;
2306					replicator_out0: endpoint {
2307						remote-endpoint =
2308						  <&etr_in>;
2309					};
2310				};
2311
2312				port@1 {
2313					reg = <1>;
2314					replicator_out1: endpoint {
2315						remote-endpoint =
2316						  <&tpiu_in>;
2317					};
2318				};
2319			};
2320		};
2321
2322		etf@3027000 {
2323			compatible = "arm,coresight-tmc", "arm,primecell";
2324			reg = <0x3027000 0x1000>;
2325
2326			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2327			clock-names = "apb_pclk", "atclk";
2328
2329			in-ports {
2330				port {
2331					etf_in: endpoint {
2332						remote-endpoint =
2333						  <&merge_funnel_out>;
2334					};
2335				};
2336			};
2337
2338			out-ports {
2339				port {
2340					etf_out: endpoint {
2341						remote-endpoint =
2342						  <&replicator_in>;
2343					};
2344				};
2345			};
2346		};
2347
2348		etr@3028000 {
2349			compatible = "arm,coresight-tmc", "arm,primecell";
2350			reg = <0x3028000 0x1000>;
2351
2352			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2353			clock-names = "apb_pclk", "atclk";
2354			arm,scatter-gather;
2355
2356			in-ports {
2357				port {
2358					etr_in: endpoint {
2359						remote-endpoint =
2360						  <&replicator_out0>;
2361					};
2362				};
2363			};
2364		};
2365
2366		debug@3810000 {
2367			compatible = "arm,coresight-cpu-debug", "arm,primecell";
2368			reg = <0x3810000 0x1000>;
2369
2370			clocks = <&rpmcc RPM_QDSS_CLK>;
2371			clock-names = "apb_pclk";
2372
2373			cpu = <&CPU0>;
2374		};
2375
2376		etm@3840000 {
2377			compatible = "arm,coresight-etm4x", "arm,primecell";
2378			reg = <0x3840000 0x1000>;
2379
2380			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2381			clock-names = "apb_pclk", "atclk";
2382
2383			cpu = <&CPU0>;
2384
2385			out-ports {
2386				port {
2387					etm0_out: endpoint {
2388						remote-endpoint =
2389						  <&apss_funnel0_in0>;
2390					};
2391				};
2392			};
2393		};
2394
2395		debug@3910000 {
2396			compatible = "arm,coresight-cpu-debug", "arm,primecell";
2397			reg = <0x3910000 0x1000>;
2398
2399			clocks = <&rpmcc RPM_QDSS_CLK>;
2400			clock-names = "apb_pclk";
2401
2402			cpu = <&CPU1>;
2403		};
2404
2405		etm@3940000 {
2406			compatible = "arm,coresight-etm4x", "arm,primecell";
2407			reg = <0x3940000 0x1000>;
2408
2409			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2410			clock-names = "apb_pclk", "atclk";
2411
2412			cpu = <&CPU1>;
2413
2414			out-ports {
2415				port {
2416					etm1_out: endpoint {
2417						remote-endpoint =
2418						  <&apss_funnel0_in1>;
2419					};
2420				};
2421			};
2422		};
2423
2424		funnel@39b0000 { /* APSS Funnel 0 */
2425			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2426			reg = <0x39b0000 0x1000>;
2427
2428			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2429			clock-names = "apb_pclk", "atclk";
2430
2431			in-ports {
2432				#address-cells = <1>;
2433				#size-cells = <0>;
2434
2435				port@0 {
2436					reg = <0>;
2437					apss_funnel0_in0: endpoint {
2438						remote-endpoint = <&etm0_out>;
2439					};
2440				};
2441
2442				port@1 {
2443					reg = <1>;
2444					apss_funnel0_in1: endpoint {
2445						remote-endpoint = <&etm1_out>;
2446					};
2447				};
2448			};
2449
2450			out-ports {
2451				port {
2452					apss_funnel0_out: endpoint {
2453						remote-endpoint =
2454						  <&apss_merge_funnel_in0>;
2455					};
2456				};
2457			};
2458		};
2459
2460		debug@3a10000 {
2461			compatible = "arm,coresight-cpu-debug", "arm,primecell";
2462			reg = <0x3a10000 0x1000>;
2463
2464			clocks = <&rpmcc RPM_QDSS_CLK>;
2465			clock-names = "apb_pclk";
2466
2467			cpu = <&CPU2>;
2468		};
2469
2470		etm@3a40000 {
2471			compatible = "arm,coresight-etm4x", "arm,primecell";
2472			reg = <0x3a40000 0x1000>;
2473
2474			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2475			clock-names = "apb_pclk", "atclk";
2476
2477			cpu = <&CPU2>;
2478
2479			out-ports {
2480				port {
2481					etm2_out: endpoint {
2482						remote-endpoint =
2483						  <&apss_funnel1_in0>;
2484					};
2485				};
2486			};
2487		};
2488
2489		debug@3b10000 {
2490			compatible = "arm,coresight-cpu-debug", "arm,primecell";
2491			reg = <0x3b10000 0x1000>;
2492
2493			clocks = <&rpmcc RPM_QDSS_CLK>;
2494			clock-names = "apb_pclk";
2495
2496			cpu = <&CPU3>;
2497		};
2498
2499		etm@3b40000 {
2500			compatible = "arm,coresight-etm4x", "arm,primecell";
2501			reg = <0x3b40000 0x1000>;
2502
2503			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2504			clock-names = "apb_pclk", "atclk";
2505
2506			cpu = <&CPU3>;
2507
2508			out-ports {
2509				port {
2510					etm3_out: endpoint {
2511						remote-endpoint =
2512						  <&apss_funnel1_in1>;
2513					};
2514				};
2515			};
2516		};
2517
2518		funnel@3bb0000 { /* APSS Funnel 1 */
2519			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2520			reg = <0x3bb0000 0x1000>;
2521
2522			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2523			clock-names = "apb_pclk", "atclk";
2524
2525			in-ports {
2526				#address-cells = <1>;
2527				#size-cells = <0>;
2528
2529				port@0 {
2530					reg = <0>;
2531					apss_funnel1_in0: endpoint {
2532						remote-endpoint = <&etm2_out>;
2533					};
2534				};
2535
2536				port@1 {
2537					reg = <1>;
2538					apss_funnel1_in1: endpoint {
2539						remote-endpoint = <&etm3_out>;
2540					};
2541				};
2542			};
2543
2544			out-ports {
2545				port {
2546					apss_funnel1_out: endpoint {
2547						remote-endpoint =
2548						  <&apss_merge_funnel_in1>;
2549					};
2550				};
2551			};
2552		};
2553
2554		funnel@3bc0000 {
2555			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2556			reg = <0x3bc0000 0x1000>;
2557
2558			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2559			clock-names = "apb_pclk", "atclk";
2560
2561			in-ports {
2562				#address-cells = <1>;
2563				#size-cells = <0>;
2564
2565				port@0 {
2566					reg = <0>;
2567					apss_merge_funnel_in0: endpoint {
2568						remote-endpoint =
2569						  <&apss_funnel0_out>;
2570					};
2571				};
2572
2573				port@1 {
2574					reg = <1>;
2575					apss_merge_funnel_in1: endpoint {
2576						remote-endpoint =
2577						  <&apss_funnel1_out>;
2578					};
2579				};
2580			};
2581
2582			out-ports {
2583				port {
2584					apss_merge_funnel_out: endpoint {
2585						remote-endpoint =
2586						  <&funnel1_in>;
2587					};
2588				};
2589			};
2590		};
2591
2592		kryocc: clock-controller@6400000 {
2593			compatible = "qcom,msm8996-apcc";
2594			reg = <0x06400000 0x90000>;
2595
2596			clock-names = "xo";
2597			clocks = <&xo_board>;
2598
2599			#clock-cells = <1>;
2600		};
2601
2602		usb3: usb@6af8800 {
2603			compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
2604			reg = <0x06af8800 0x400>;
2605			#address-cells = <1>;
2606			#size-cells = <1>;
2607			ranges;
2608
2609			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2610				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2611			interrupt-names = "hs_phy_irq", "ss_phy_irq";
2612
2613			clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
2614				<&gcc GCC_USB30_MASTER_CLK>,
2615				<&gcc GCC_AGGRE2_USB3_AXI_CLK>,
2616				<&gcc GCC_USB30_MOCK_UTMI_CLK>,
2617				<&gcc GCC_USB30_SLEEP_CLK>,
2618				<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
2619
2620			assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2621					  <&gcc GCC_USB30_MASTER_CLK>;
2622			assigned-clock-rates = <19200000>, <120000000>;
2623
2624			power-domains = <&gcc USB30_GDSC>;
2625			status = "disabled";
2626
2627			usb3_dwc3: dwc3@6a00000 {
2628				compatible = "snps,dwc3";
2629				reg = <0x06a00000 0xcc00>;
2630				interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
2631				phys = <&hsusb_phy1>, <&ssusb_phy_0>;
2632				phy-names = "usb2-phy", "usb3-phy";
2633				snps,hird-threshold = /bits/ 8 <0>;
2634				snps,dis_u2_susphy_quirk;
2635				snps,dis_enblslpm_quirk;
2636				snps,is-utmi-l1-suspend;
2637				tx-fifo-resize;
2638			};
2639		};
2640
2641		usb3phy: phy@7410000 {
2642			compatible = "qcom,msm8996-qmp-usb3-phy";
2643			reg = <0x07410000 0x1c4>;
2644			#clock-cells = <1>;
2645			#address-cells = <1>;
2646			#size-cells = <1>;
2647			ranges;
2648
2649			clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2650				<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2651				<&gcc GCC_USB3_CLKREF_CLK>;
2652			clock-names = "aux", "cfg_ahb", "ref";
2653
2654			resets = <&gcc GCC_USB3_PHY_BCR>,
2655				<&gcc GCC_USB3PHY_PHY_BCR>;
2656			reset-names = "phy", "common";
2657			status = "disabled";
2658
2659			ssusb_phy_0: phy@7410200 {
2660				reg = <0x07410200 0x200>,
2661				      <0x07410400 0x130>,
2662				      <0x07410600 0x1a8>;
2663				#phy-cells = <0>;
2664
2665				clock-output-names = "usb3_phy_pipe_clk_src";
2666				clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
2667				clock-names = "pipe0";
2668			};
2669		};
2670
2671		hsusb_phy1: phy@7411000 {
2672			compatible = "qcom,msm8996-qusb2-phy";
2673			reg = <0x07411000 0x180>;
2674			#phy-cells = <0>;
2675
2676			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2677				<&gcc GCC_RX1_USB2_CLKREF_CLK>;
2678			clock-names = "cfg_ahb", "ref";
2679
2680			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2681			nvmem-cells = <&qusb2p_hstx_trim>;
2682			status = "disabled";
2683		};
2684
2685		hsusb_phy2: phy@7412000 {
2686			compatible = "qcom,msm8996-qusb2-phy";
2687			reg = <0x07412000 0x180>;
2688			#phy-cells = <0>;
2689
2690			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2691				<&gcc GCC_RX2_USB2_CLKREF_CLK>;
2692			clock-names = "cfg_ahb", "ref";
2693
2694			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2695			nvmem-cells = <&qusb2s_hstx_trim>;
2696			status = "disabled";
2697		};
2698
2699		sdhc1: sdhci@7464900 {
2700			compatible = "qcom,sdhci-msm-v4";
2701			reg = <0x07464900 0x11c>, <0x07464000 0x800>;
2702			reg-names = "hc_mem", "core_mem";
2703
2704			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2705					<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
2706			interrupt-names = "hc_irq", "pwr_irq";
2707
2708			clock-names = "iface", "core", "xo";
2709			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
2710				<&gcc GCC_SDCC1_APPS_CLK>,
2711				<&xo_board>;
2712
2713			pinctrl-names = "default", "sleep";
2714			pinctrl-0 = <&sdc1_state_on>;
2715			pinctrl-1 = <&sdc1_state_off>;
2716
2717			bus-width = <8>;
2718			non-removable;
2719			status = "disabled";
2720		};
2721
2722		sdhc2: sdhci@74a4900 {
2723			compatible = "qcom,sdhci-msm-v4";
2724			reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
2725			reg-names = "hc_mem", "core_mem";
2726
2727			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2728				      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2729			interrupt-names = "hc_irq", "pwr_irq";
2730
2731			clock-names = "iface", "core", "xo";
2732			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2733				<&gcc GCC_SDCC2_APPS_CLK>,
2734				<&xo_board>;
2735
2736			pinctrl-names = "default", "sleep";
2737			pinctrl-0 = <&sdc2_state_on>;
2738			pinctrl-1 = <&sdc2_state_off>;
2739
2740			bus-width = <4>;
2741			status = "disabled";
2742		 };
2743
2744		blsp1_dma: dma@7544000 {
2745			compatible = "qcom,bam-v1.7.0";
2746			reg = <0x07544000 0x2b000>;
2747			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2748			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2749			clock-names = "bam_clk";
2750			qcom,controlled-remotely;
2751			#dma-cells = <1>;
2752			qcom,ee = <0>;
2753		};
2754
2755		blsp1_uart2: serial@7570000 {
2756			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2757			reg = <0x07570000 0x1000>;
2758			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2759			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
2760				 <&gcc GCC_BLSP1_AHB_CLK>;
2761			clock-names = "core", "iface";
2762			pinctrl-names = "default", "sleep";
2763			pinctrl-0 = <&blsp1_uart2_default>;
2764			pinctrl-1 = <&blsp1_uart2_sleep>;
2765			dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
2766			dma-names = "tx", "rx";
2767			status = "disabled";
2768		};
2769
2770		blsp1_spi1: spi@7575000 {
2771			compatible = "qcom,spi-qup-v2.2.1";
2772			reg = <0x07575000 0x600>;
2773			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2774			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2775				 <&gcc GCC_BLSP1_AHB_CLK>;
2776			clock-names = "core", "iface";
2777			pinctrl-names = "default", "sleep";
2778			pinctrl-0 = <&blsp1_spi1_default>;
2779			pinctrl-1 = <&blsp1_spi1_sleep>;
2780			dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2781			dma-names = "tx", "rx";
2782			#address-cells = <1>;
2783			#size-cells = <0>;
2784			status = "disabled";
2785		};
2786
2787		blsp1_i2c3: i2c@7577000 {
2788			compatible = "qcom,i2c-qup-v2.2.1";
2789			reg = <0x07577000 0x1000>;
2790			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2791			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
2792				<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
2793			clock-names = "iface", "core";
2794			pinctrl-names = "default", "sleep";
2795			pinctrl-0 = <&blsp1_i2c3_default>;
2796			pinctrl-1 = <&blsp1_i2c3_sleep>;
2797			dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2798			dma-names = "tx", "rx";
2799			#address-cells = <1>;
2800			#size-cells = <0>;
2801			status = "disabled";
2802		};
2803
2804		blsp2_dma: dma@7584000 {
2805			compatible = "qcom,bam-v1.7.0";
2806			reg = <0x07584000 0x2b000>;
2807			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2808			clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2809			clock-names = "bam_clk";
2810			qcom,controlled-remotely;
2811			#dma-cells = <1>;
2812			qcom,ee = <0>;
2813		};
2814
2815		blsp2_uart2: serial@75b0000 {
2816			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2817			reg = <0x075b0000 0x1000>;
2818			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2819			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2820				 <&gcc GCC_BLSP2_AHB_CLK>;
2821			clock-names = "core", "iface";
2822			status = "disabled";
2823		};
2824
2825		blsp2_uart3: serial@75b1000 {
2826			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2827			reg = <0x075b1000 0x1000>;
2828			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
2829			clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
2830				 <&gcc GCC_BLSP2_AHB_CLK>;
2831			clock-names = "core", "iface";
2832			status = "disabled";
2833		};
2834
2835		blsp2_i2c1: i2c@75b5000 {
2836			compatible = "qcom,i2c-qup-v2.2.1";
2837			reg = <0x075b5000 0x1000>;
2838			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2839			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2840				<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
2841			clock-names = "iface", "core";
2842			pinctrl-names = "default", "sleep";
2843			pinctrl-0 = <&blsp2_i2c1_default>;
2844			pinctrl-1 = <&blsp2_i2c1_sleep>;
2845			dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2846			dma-names = "tx", "rx";
2847			#address-cells = <1>;
2848			#size-cells = <0>;
2849			status = "disabled";
2850		};
2851
2852		blsp2_i2c2: i2c@75b6000 {
2853			compatible = "qcom,i2c-qup-v2.2.1";
2854			reg = <0x075b6000 0x1000>;
2855			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2856			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2857				<&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
2858			clock-names = "iface", "core";
2859			pinctrl-names = "default", "sleep";
2860			pinctrl-0 = <&blsp2_i2c2_default>;
2861			pinctrl-1 = <&blsp2_i2c2_sleep>;
2862			dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2863			dma-names = "tx", "rx";
2864			#address-cells = <1>;
2865			#size-cells = <0>;
2866			status = "disabled";
2867		};
2868
2869		blsp2_i2c5: i2c@75b9000 {
2870			compatible = "qcom,i2c-qup-v2.2.1";
2871			reg = <0x75b9000 0x1000>;
2872			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2873			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2874				<&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
2875			clock-names = "iface", "core";
2876			pinctrl-names = "default";
2877			pinctrl-0 = <&blsp2_i2c5_default>;
2878			dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
2879			dma-names = "tx", "rx";
2880			#address-cells = <1>;
2881			#size-cells = <0>;
2882			status = "disabled";
2883		};
2884
2885		blsp2_i2c6: i2c@75ba000 {
2886			compatible = "qcom,i2c-qup-v2.2.1";
2887			reg = <0x75ba000 0x1000>;
2888			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2889			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2890				<&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>;
2891			clock-names = "iface", "core";
2892			pinctrl-names = "default", "sleep";
2893			pinctrl-0 = <&blsp2_i2c6_default>;
2894			pinctrl-1 = <&blsp2_i2c6_sleep>;
2895			dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
2896			dma-names = "tx", "rx";
2897			#address-cells = <1>;
2898			#size-cells = <0>;
2899			status = "disabled";
2900		};
2901
2902		blsp2_spi6: spi@75ba000{
2903			compatible = "qcom,spi-qup-v2.2.1";
2904			reg = <0x075ba000 0x600>;
2905			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2906			clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
2907				 <&gcc GCC_BLSP2_AHB_CLK>;
2908			clock-names = "core", "iface";
2909			pinctrl-names = "default", "sleep";
2910			pinctrl-0 = <&blsp2_spi6_default>;
2911			pinctrl-1 = <&blsp2_spi6_sleep>;
2912			dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
2913			dma-names = "tx", "rx";
2914			#address-cells = <1>;
2915			#size-cells = <0>;
2916			status = "disabled";
2917		};
2918
2919		usb2: usb@76f8800 {
2920			compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
2921			reg = <0x076f8800 0x400>;
2922			#address-cells = <1>;
2923			#size-cells = <1>;
2924			ranges;
2925
2926			interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
2927			interrupt-names = "hs_phy_irq";
2928
2929			clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
2930				<&gcc GCC_USB20_MASTER_CLK>,
2931				<&gcc GCC_USB20_MOCK_UTMI_CLK>,
2932				<&gcc GCC_USB20_SLEEP_CLK>,
2933				<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
2934
2935			assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
2936					  <&gcc GCC_USB20_MASTER_CLK>;
2937			assigned-clock-rates = <19200000>, <60000000>;
2938
2939			power-domains = <&gcc USB30_GDSC>;
2940			qcom,select-utmi-as-pipe-clk;
2941			status = "disabled";
2942
2943			dwc3@7600000 {
2944				compatible = "snps,dwc3";
2945				reg = <0x07600000 0xcc00>;
2946				interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
2947				phys = <&hsusb_phy2>;
2948				phy-names = "usb2-phy";
2949				maximum-speed = "high-speed";
2950				snps,dis_u2_susphy_quirk;
2951				snps,dis_enblslpm_quirk;
2952			};
2953		};
2954
2955		slimbam: dma-controller@9184000 {
2956			compatible = "qcom,bam-v1.7.0";
2957			qcom,controlled-remotely;
2958			reg = <0x09184000 0x32000>;
2959			num-channels  = <31>;
2960			interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
2961			#dma-cells = <1>;
2962			qcom,ee = <1>;
2963			qcom,num-ees = <2>;
2964		};
2965
2966		slim_msm: slim@91c0000 {
2967			compatible = "qcom,slim-ngd-v1.5.0";
2968			reg = <0x091c0000 0x2C000>;
2969			reg-names = "ctrl";
2970			interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
2971			dmas =	<&slimbam 3>, <&slimbam 4>,
2972				<&slimbam 5>, <&slimbam 6>;
2973			dma-names = "rx", "tx", "tx2", "rx2";
2974			#address-cells = <1>;
2975			#size-cells = <0>;
2976			ngd@1 {
2977				reg = <1>;
2978				#address-cells = <1>;
2979				#size-cells = <1>;
2980
2981				tasha_ifd: tas-ifd {
2982					compatible = "slim217,1a0";
2983					reg  = <0 0>;
2984				};
2985
2986				wcd9335: codec@1{
2987					pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
2988					pinctrl-names = "default";
2989
2990					compatible = "slim217,1a0";
2991					reg  = <1 0>;
2992
2993					interrupt-parent = <&tlmm>;
2994					interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
2995						     <53 IRQ_TYPE_LEVEL_HIGH>;
2996					interrupt-names  = "intr1", "intr2";
2997					interrupt-controller;
2998					#interrupt-cells = <1>;
2999					reset-gpios = <&tlmm 64 0>;
3000
3001					slim-ifc-dev  = <&tasha_ifd>;
3002
3003					#sound-dai-cells = <1>;
3004				};
3005			};
3006		};
3007
3008		adsp_pil: remoteproc@9300000 {
3009			compatible = "qcom,msm8996-adsp-pil";
3010			reg = <0x09300000 0x80000>;
3011
3012			interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3013					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3014					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
3015					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
3016					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
3017			interrupt-names = "wdog", "fatal", "ready",
3018					  "handover", "stop-ack";
3019
3020			clocks = <&xo_board>;
3021			clock-names = "xo";
3022
3023			memory-region = <&adsp_region>;
3024
3025			qcom,smem-states = <&smp2p_adsp_out 0>;
3026			qcom,smem-state-names = "stop";
3027
3028			power-domains = <&rpmpd MSM8996_VDDCX>;
3029			power-domain-names = "cx";
3030
3031			status = "disabled";
3032
3033			smd-edge {
3034				interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3035
3036				label = "lpass";
3037				mboxes = <&apcs_glb 8>;
3038				qcom,smd-edge = <1>;
3039				qcom,remote-pid = <2>;
3040				#address-cells = <1>;
3041				#size-cells = <0>;
3042				apr {
3043					power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
3044					compatible = "qcom,apr-v2";
3045					qcom,smd-channels = "apr_audio_svc";
3046					qcom,apr-domain = <APR_DOMAIN_ADSP>;
3047					#address-cells = <1>;
3048					#size-cells = <0>;
3049
3050					q6core {
3051						reg = <APR_SVC_ADSP_CORE>;
3052						compatible = "qcom,q6core";
3053					};
3054
3055					q6afe: q6afe {
3056						compatible = "qcom,q6afe";
3057						reg = <APR_SVC_AFE>;
3058						q6afedai: dais {
3059							compatible = "qcom,q6afe-dais";
3060							#address-cells = <1>;
3061							#size-cells = <0>;
3062							#sound-dai-cells = <1>;
3063							hdmi@1 {
3064								reg = <1>;
3065							};
3066						};
3067					};
3068
3069					q6asm: q6asm {
3070						compatible = "qcom,q6asm";
3071						reg = <APR_SVC_ASM>;
3072						q6asmdai: dais {
3073							compatible = "qcom,q6asm-dais";
3074							#address-cells = <1>;
3075							#size-cells = <0>;
3076							#sound-dai-cells = <1>;
3077							iommus = <&lpass_q6_smmu 1>;
3078						};
3079					};
3080
3081					q6adm: q6adm {
3082						compatible = "qcom,q6adm";
3083						reg = <APR_SVC_ADM>;
3084						q6routing: routing {
3085							compatible = "qcom,q6adm-routing";
3086							#sound-dai-cells = <0>;
3087						};
3088					};
3089				};
3090
3091			};
3092		};
3093
3094		apcs_glb: mailbox@9820000 {
3095			compatible = "qcom,msm8996-apcs-hmss-global";
3096			reg = <0x09820000 0x1000>;
3097
3098			#mbox-cells = <1>;
3099		};
3100
3101		timer@9840000 {
3102			#address-cells = <1>;
3103			#size-cells = <1>;
3104			ranges;
3105			compatible = "arm,armv7-timer-mem";
3106			reg = <0x09840000 0x1000>;
3107			clock-frequency = <19200000>;
3108
3109			frame@9850000 {
3110				frame-number = <0>;
3111				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3112					     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
3113				reg = <0x09850000 0x1000>,
3114				      <0x09860000 0x1000>;
3115			};
3116
3117			frame@9870000 {
3118				frame-number = <1>;
3119				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3120				reg = <0x09870000 0x1000>;
3121				status = "disabled";
3122			};
3123
3124			frame@9880000 {
3125				frame-number = <2>;
3126				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3127				reg = <0x09880000 0x1000>;
3128				status = "disabled";
3129			};
3130
3131			frame@9890000 {
3132				frame-number = <3>;
3133				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
3134				reg = <0x09890000 0x1000>;
3135				status = "disabled";
3136			};
3137
3138			frame@98a0000 {
3139				frame-number = <4>;
3140				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
3141				reg = <0x098a0000 0x1000>;
3142				status = "disabled";
3143			};
3144
3145			frame@98b0000 {
3146				frame-number = <5>;
3147				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3148				reg = <0x098b0000 0x1000>;
3149				status = "disabled";
3150			};
3151
3152			frame@98c0000 {
3153				frame-number = <6>;
3154				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3155				reg = <0x098c0000 0x1000>;
3156				status = "disabled";
3157			};
3158		};
3159
3160		saw3: syscon@9a10000 {
3161			compatible = "syscon";
3162			reg = <0x09a10000 0x1000>;
3163		};
3164
3165		intc: interrupt-controller@9bc0000 {
3166			compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3167			#interrupt-cells = <3>;
3168			interrupt-controller;
3169			#redistributor-regions = <1>;
3170			redistributor-stride = <0x0 0x40000>;
3171			reg = <0x09bc0000 0x10000>,
3172			      <0x09c00000 0x100000>;
3173			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3174		};
3175	};
3176
3177	sound: sound {
3178	};
3179
3180	thermal-zones {
3181		cpu0-thermal {
3182			polling-delay-passive = <250>;
3183			polling-delay = <1000>;
3184
3185			thermal-sensors = <&tsens0 3>;
3186
3187			trips {
3188				cpu0_alert0: trip-point0 {
3189					temperature = <75000>;
3190					hysteresis = <2000>;
3191					type = "passive";
3192				};
3193
3194				cpu0_crit: cpu_crit {
3195					temperature = <110000>;
3196					hysteresis = <2000>;
3197					type = "critical";
3198				};
3199			};
3200		};
3201
3202		cpu1-thermal {
3203			polling-delay-passive = <250>;
3204			polling-delay = <1000>;
3205
3206			thermal-sensors = <&tsens0 5>;
3207
3208			trips {
3209				cpu1_alert0: trip-point0 {
3210					temperature = <75000>;
3211					hysteresis = <2000>;
3212					type = "passive";
3213				};
3214
3215				cpu1_crit: cpu_crit {
3216					temperature = <110000>;
3217					hysteresis = <2000>;
3218					type = "critical";
3219				};
3220			};
3221		};
3222
3223		cpu2-thermal {
3224			polling-delay-passive = <250>;
3225			polling-delay = <1000>;
3226
3227			thermal-sensors = <&tsens0 8>;
3228
3229			trips {
3230				cpu2_alert0: trip-point0 {
3231					temperature = <75000>;
3232					hysteresis = <2000>;
3233					type = "passive";
3234				};
3235
3236				cpu2_crit: cpu_crit {
3237					temperature = <110000>;
3238					hysteresis = <2000>;
3239					type = "critical";
3240				};
3241			};
3242		};
3243
3244		cpu3-thermal {
3245			polling-delay-passive = <250>;
3246			polling-delay = <1000>;
3247
3248			thermal-sensors = <&tsens0 10>;
3249
3250			trips {
3251				cpu3_alert0: trip-point0 {
3252					temperature = <75000>;
3253					hysteresis = <2000>;
3254					type = "passive";
3255				};
3256
3257				cpu3_crit: cpu_crit {
3258					temperature = <110000>;
3259					hysteresis = <2000>;
3260					type = "critical";
3261				};
3262			};
3263		};
3264
3265		gpu-thermal-top {
3266			polling-delay-passive = <250>;
3267			polling-delay = <1000>;
3268
3269			thermal-sensors = <&tsens1 6>;
3270
3271			trips {
3272				gpu1_alert0: trip-point0 {
3273					temperature = <90000>;
3274					hysteresis = <2000>;
3275					type = "passive";
3276				};
3277			};
3278
3279			cooling-maps {
3280				map0 {
3281					trip = <&gpu1_alert0>;
3282					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3283				};
3284			};
3285		};
3286
3287		gpu-thermal-bottom {
3288			polling-delay-passive = <250>;
3289			polling-delay = <1000>;
3290
3291			thermal-sensors = <&tsens1 7>;
3292
3293			trips {
3294				gpu2_alert0: trip-point0 {
3295					temperature = <90000>;
3296					hysteresis = <2000>;
3297					type = "passive";
3298				};
3299			};
3300
3301			cooling-maps {
3302				map0 {
3303					trip = <&gpu2_alert0>;
3304					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3305				};
3306			};
3307		};
3308
3309		m4m-thermal {
3310			polling-delay-passive = <250>;
3311			polling-delay = <1000>;
3312
3313			thermal-sensors = <&tsens0 1>;
3314
3315			trips {
3316				m4m_alert0: trip-point0 {
3317					temperature = <90000>;
3318					hysteresis = <2000>;
3319					type = "hot";
3320				};
3321			};
3322		};
3323
3324		l3-or-venus-thermal {
3325			polling-delay-passive = <250>;
3326			polling-delay = <1000>;
3327
3328			thermal-sensors = <&tsens0 2>;
3329
3330			trips {
3331				l3_or_venus_alert0: trip-point0 {
3332					temperature = <90000>;
3333					hysteresis = <2000>;
3334					type = "hot";
3335				};
3336			};
3337		};
3338
3339		cluster0-l2-thermal {
3340			polling-delay-passive = <250>;
3341			polling-delay = <1000>;
3342
3343			thermal-sensors = <&tsens0 7>;
3344
3345			trips {
3346				cluster0_l2_alert0: trip-point0 {
3347					temperature = <90000>;
3348					hysteresis = <2000>;
3349					type = "hot";
3350				};
3351			};
3352		};
3353
3354		cluster1-l2-thermal {
3355			polling-delay-passive = <250>;
3356			polling-delay = <1000>;
3357
3358			thermal-sensors = <&tsens0 12>;
3359
3360			trips {
3361				cluster1_l2_alert0: trip-point0 {
3362					temperature = <90000>;
3363					hysteresis = <2000>;
3364					type = "hot";
3365				};
3366			};
3367		};
3368
3369		camera-thermal {
3370			polling-delay-passive = <250>;
3371			polling-delay = <1000>;
3372
3373			thermal-sensors = <&tsens1 1>;
3374
3375			trips {
3376				camera_alert0: trip-point0 {
3377					temperature = <90000>;
3378					hysteresis = <2000>;
3379					type = "hot";
3380				};
3381			};
3382		};
3383
3384		q6-dsp-thermal {
3385			polling-delay-passive = <250>;
3386			polling-delay = <1000>;
3387
3388			thermal-sensors = <&tsens1 2>;
3389
3390			trips {
3391				q6_dsp_alert0: trip-point0 {
3392					temperature = <90000>;
3393					hysteresis = <2000>;
3394					type = "hot";
3395				};
3396			};
3397		};
3398
3399		mem-thermal {
3400			polling-delay-passive = <250>;
3401			polling-delay = <1000>;
3402
3403			thermal-sensors = <&tsens1 3>;
3404
3405			trips {
3406				mem_alert0: trip-point0 {
3407					temperature = <90000>;
3408					hysteresis = <2000>;
3409					type = "hot";
3410				};
3411			};
3412		};
3413
3414		modemtx-thermal {
3415			polling-delay-passive = <250>;
3416			polling-delay = <1000>;
3417
3418			thermal-sensors = <&tsens1 4>;
3419
3420			trips {
3421				modemtx_alert0: trip-point0 {
3422					temperature = <90000>;
3423					hysteresis = <2000>;
3424					type = "hot";
3425				};
3426			};
3427		};
3428	};
3429
3430	timer {
3431		compatible = "arm,armv8-timer";
3432		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
3433			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
3434			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
3435			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
3436	};
3437};
3438