Searched refs:interrupt (Results 1 – 25 of 1719) sorted by relevance
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| /arch/mips/boot/dts/loongson/ |
| D | ls7a-pch.dtsi | 13 pic: interrupt-controller@10000000 {
16 interrupt-controller;
17 interrupt-parent = <&htvec>;
19 #interrupt-cells = <2>;
26 interrupt-parent = <&pic>;
36 interrupt-parent = <&pic>;
46 interrupt-parent = <&pic>;
56 interrupt-parent = <&pic>;
66 #interrupt-cells = <2>;
83 interrupt-parent = <&pic>;
[all …]
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| D | loongson64-2k1000.dtsi | 5 #include <dt-bindings/interrupt-controller/irq.h>
40 cpuintc: interrupt-controller {
42 #interrupt-cells = <1>;
43 interrupt-controller;
44 compatible = "mti,cpu-interrupt-controller";
55 liointc0: interrupt-controller@1fe11400 {
62 interrupt-controller;
63 #interrupt-cells = <2>;
65 interrupt-parent = <&cpuintc>;
67 interrupt-names = "int0";
[all …]
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| D | loongson64g-package.dtsi | 3 #include <dt-bindings/interrupt-controller/irq.h>
9 cpuintc: interrupt-controller {
11 #interrupt-cells = <1>;
12 interrupt-controller;
13 compatible = "mti,cpu-interrupt-controller";
24 liointc: interrupt-controller@3ff01400 {
28 interrupt-controller;
29 #interrupt-cells = <2>;
31 interrupt-parent = <&cpuintc>;
33 interrupt-names = "int0", "int1";
[all …]
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| D | loongson64c-package.dtsi | 3 #include <dt-bindings/interrupt-controller/irq.h>
9 cpuintc: interrupt-controller {
11 #interrupt-cells = <1>;
12 interrupt-controller;
13 compatible = "mti,cpu-interrupt-controller";
27 liointc: interrupt-controller@3ff01400 {
31 interrupt-controller;
32 #interrupt-cells = <2>;
34 interrupt-parent = <&cpuintc>;
36 interrupt-names = "int0", "int1";
[all …]
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| /arch/powerpc/boot/dts/ |
| D | fsp2.dts | 64 #interrupt-cells = <2>;
66 interrupt-controller;
76 #interrupt-cells = <2>;
79 interrupt-controller;
82 interrupt-parent = <&UIC0>;
90 #interrupt-cells = <2>;
93 interrupt-controller;
96 interrupt-parent = <&UIC0>;
104 #interrupt-cells = <2>;
107 interrupt-controller;
[all …]
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| /arch/mips/boot/dts/brcm/ |
| D | bcm7358.dtsi | 24 cpu_intc: interrupt-controller {
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
29 #interrupt-cells = <1>;
53 periph_intc: interrupt-controller@411400 {
57 interrupt-controller;
58 #interrupt-cells = <1>;
60 interrupt-parent = <&cpu_intc>;
64 sun_l2_intc: interrupt-controller@403000 {
67 interrupt-controller;
[all …]
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| D | bcm7125.dtsi | 30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@441400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@401800 {
73 interrupt-controller;
[all …]
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| D | bcm7346.dtsi | 30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@411400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@403000 {
73 interrupt-controller;
[all …]
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| D | bcm7360.dtsi | 24 cpu_intc: interrupt-controller {
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
29 #interrupt-cells = <1>;
53 periph_intc: interrupt-controller@411400 {
57 interrupt-controller;
58 #interrupt-cells = <1>;
60 interrupt-parent = <&cpu_intc>;
64 sun_l2_intc: interrupt-controller@403000 {
67 interrupt-controller;
[all …]
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| D | bcm7420.dtsi | 30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@441400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@401800 {
73 interrupt-controller;
[all …]
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| D | bcm7362.dtsi | 30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@411400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@403000 {
73 interrupt-controller;
[all …]
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| D | bcm7435.dtsi | 42 cpu_intc: interrupt-controller {
44 compatible = "mti,cpu-interrupt-controller";
46 interrupt-controller;
47 #interrupt-cells = <1>;
71 periph_intc: interrupt-controller@41b500 {
76 interrupt-controller;
77 #interrupt-cells = <1>;
79 interrupt-parent = <&cpu_intc>;
83 sun_l2_intc: interrupt-controller@403000 {
86 interrupt-controller;
[all …]
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| D | bcm7425.dtsi | 30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@41a400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@403000 {
73 interrupt-controller;
[all …]
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| /arch/arm/boot/dts/ |
| D | exynos5410-pinctrl.dtsi | 16 interrupt-controller;
17 #interrupt-cells = <2>;
24 interrupt-controller;
25 #interrupt-cells = <2>;
32 interrupt-controller;
33 #interrupt-cells = <2>;
40 interrupt-controller;
41 #interrupt-cells = <2>;
48 interrupt-controller;
49 #interrupt-cells = <2>;
[all …]
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| D | arm-realview-pba8.dts | 45 interrupt-parent = <&intc>;
47 interrupt-affinity = <&cpu0>;
50 /* Primary GIC PL390 interrupt controller in the test chip */
51 intc: interrupt-controller@1e000000 {
53 #interrupt-cells = <3>;
55 interrupt-controller;
62 interrupt-parent = <&intc>;
67 interrupt-parent = <&intc>;
80 interrupt-parent = <&intc>;
85 interrupt-parent = <&intc>;
[all …]
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| D | arm-realview-eb-mp.dtsi | 23 #include <dt-bindings/interrupt-controller/irq.h>
40 /* Primary interrupt controller in the test chip */
41 intc: interrupt-controller@1f000100 {
43 #interrupt-cells = <3>;
45 interrupt-controller;
50 /* Secondary interrupt controller on the FPGA */
51 intc_second: interrupt-controller@10040000 {
53 #interrupt-cells = <3>;
55 interrupt-controller;
58 interrupt-parent = <&intc>;
[all …]
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| D | arm-realview-pbx-a9.dts | 89 interrupt-parent = <&intc>;
96 interrupt-parent = <&intc>;
102 interrupt-parent = <&intc>;
105 interrupt-affinity = <&CPU0>, <&CPU1>;
108 /* Primary GIC PL390 interrupt controller in the test chip */
109 intc: interrupt-controller@1f000000 {
111 #interrupt-cells = <3>;
113 interrupt-controller;
120 interrupt-parent = <&intc>;
125 interrupt-parent = <&intc>;
[all …]
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| D | arm-realview-eb.dts | 24 #include <dt-bindings/interrupt-controller/irq.h>
51 intc: interrupt-controller@10040000 {
53 #interrupt-cells = <3>;
55 interrupt-controller;
63 * This adapts all the peripherals to the interrupt routing
68 interrupt-parent = <&intc>;
73 interrupt-parent = <&intc>;
78 interrupt-parent = <&intc>;
83 interrupt-parent = <&intc>;
89 interrupt-parent = <&intc>;
[all …]
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| /arch/mips/boot/dts/img/ |
| D | boston.dts | 6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/mips-gic.h>
46 #interrupt-cells = <1>;
48 interrupt-parent = <&gic>;
56 interrupt-map-mask = <0 0 0 7>;
57 interrupt-map = <0 0 0 1 &pci0_intc 1>,
62 pci0_intc: interrupt-controller {
63 interrupt-controller;
65 #interrupt-cells = <1>;
76 #interrupt-cells = <1>;
[all …]
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| /arch/arm64/boot/dts/exynos/ |
| D | exynos7-pinctrl.dtsi | 19 interrupt-controller;
20 interrupt-parent = <&gic>;
21 #interrupt-cells = <2>;
36 interrupt-controller;
37 interrupt-parent = <&gic>;
38 #interrupt-cells = <2>;
53 interrupt-controller;
54 #interrupt-cells = <2>;
61 interrupt-controller;
62 #interrupt-cells = <2>;
[all …]
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| D | exynos5433-pinctrl.dtsi | 27 interrupt-controller;
28 interrupt-parent = <&gic>;
37 #interrupt-cells = <2>;
44 interrupt-controller;
45 interrupt-parent = <&gic>;
54 #interrupt-cells = <2>;
61 interrupt-controller;
62 #interrupt-cells = <2>;
69 interrupt-controller;
70 #interrupt-cells = <2>;
[all …]
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| /arch/mips/boot/dts/mti/ |
| D | malta.dts | 4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/mips-gic.h>
16 cpu_intc: interrupt-controller {
17 compatible = "mti,cpu-interrupt-controller";
19 interrupt-controller;
20 #interrupt-cells = <1>;
23 gic: interrupt-controller@1bdc0000 {
27 interrupt-controller;
28 #interrupt-cells = <3>;
31 * Declare the interrupt-parent even though the mti,gic
[all …]
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| /arch/mips/boot/dts/ingenic/ |
| D | jz4770.dtsi | 24 cpuintc: interrupt-controller {
26 #interrupt-cells = <1>;
27 interrupt-controller;
28 compatible = "mti,cpu-interrupt-controller";
31 intc: interrupt-controller@10001000 {
35 interrupt-controller;
36 #interrupt-cells = <1>;
38 interrupt-parent = <&cpuintc>;
89 interrupt-controller;
90 #interrupt-cells = <1>;
[all …]
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| D | x1000.dtsi | 25 cpuintc: interrupt-controller {
27 #interrupt-cells = <1>;
28 interrupt-controller;
29 compatible = "mti,cpu-interrupt-controller";
32 intc: interrupt-controller@10001000 {
36 interrupt-controller;
37 #interrupt-cells = <1>;
39 interrupt-parent = <&cpuintc>;
99 interrupt-parent = <&cpuintc>;
117 interrupt-controller;
[all …]
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| D | jz4740.dtsi | 24 cpuintc: interrupt-controller {
26 #interrupt-cells = <1>;
27 interrupt-controller;
28 compatible = "mti,cpu-interrupt-controller";
31 intc: interrupt-controller@10001000 {
35 interrupt-controller;
36 #interrupt-cells = <1>;
38 interrupt-parent = <&cpuintc>;
78 interrupt-controller;
79 #interrupt-cells = <1>;
[all …]
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