1// SPDX-License-Identifier: GPL-2.0 2 3/ { 4 pch: bus@10000000 { 5 compatible = "simple-bus"; 6 #address-cells = <2>; 7 #size-cells = <2>; 8 ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */ 9 0 0x20000000 0 0x20000000 0 0x10000000 10 0 0x40000000 0 0x40000000 0 0x40000000 /* PCI MEM */ 11 0xe00 0x00000000 0xe00 0x00000000 0x100 0x0000000>; 12 13 pic: interrupt-controller@10000000 { 14 compatible = "loongson,pch-pic-1.0"; 15 reg = <0 0x10000000 0 0x400>; 16 interrupt-controller; 17 interrupt-parent = <&htvec>; 18 loongson,pic-base-vec = <0>; 19 #interrupt-cells = <2>; 20 }; 21 22 ls7a_uart0: serial@10080000 { 23 compatible = "ns16550a"; 24 reg = <0 0x10080000 0 0x100>; 25 clock-frequency = <50000000>; 26 interrupt-parent = <&pic>; 27 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 28 no-loopback-test; 29 }; 30 31 ls7a_uart1: serial@10080100 { 32 status = "disabled"; 33 compatible = "ns16550a"; 34 reg = <0 0x10080100 0 0x100>; 35 clock-frequency = <50000000>; 36 interrupt-parent = <&pic>; 37 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 38 no-loopback-test; 39 }; 40 41 ls7a_uart2: serial@10080200 { 42 status = "disabled"; 43 compatible = "ns16550a"; 44 reg = <0 0x10080200 0 0x100>; 45 clock-frequency = <50000000>; 46 interrupt-parent = <&pic>; 47 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 48 no-loopback-test; 49 }; 50 51 ls7a_uart3: serial@10080300 { 52 status = "disabled"; 53 compatible = "ns16550a"; 54 reg = <0 0x10080300 0 0x100>; 55 clock-frequency = <50000000>; 56 interrupt-parent = <&pic>; 57 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 58 no-loopback-test; 59 }; 60 61 pci@1a000000 { 62 compatible = "loongson,ls7a-pci"; 63 device_type = "pci"; 64 #address-cells = <3>; 65 #size-cells = <2>; 66 #interrupt-cells = <2>; 67 msi-parent = <&msi>; 68 69 reg = <0 0x1a000000 0 0x02000000>, 70 <0xefe 0x00000000 0 0x20000000>; 71 72 ranges = <0x01000000 0x0 0x00020000 0x0 0x18020000 0x0 0x00020000>, 73 <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>; 74 75 ohci@4,0 { 76 compatible = "pci0014,7a24.0", 77 "pci0014,7a24", 78 "pciclass0c0310", 79 "pciclass0c03"; 80 81 reg = <0x2000 0x0 0x0 0x0 0x0>; 82 interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; 83 interrupt-parent = <&pic>; 84 }; 85 86 ehci@4,1 { 87 compatible = "pci0014,7a14.0", 88 "pci0014,7a14", 89 "pciclass0c0320", 90 "pciclass0c03"; 91 92 reg = <0x2100 0x0 0x0 0x0 0x0>; 93 interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; 94 interrupt-parent = <&pic>; 95 }; 96 97 ohci@5,0 { 98 compatible = "pci0014,7a24.0", 99 "pci0014,7a24", 100 "pciclass0c0310", 101 "pciclass0c03"; 102 103 reg = <0x2800 0x0 0x0 0x0 0x0>; 104 interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; 105 interrupt-parent = <&pic>; 106 }; 107 108 ehci@5,1 { 109 compatible = "pci0014,7a14.0", 110 "pci0014,7a14", 111 "pciclass0c0320", 112 "pciclass0c03"; 113 114 reg = <0x2900 0x0 0x0 0x0 0x0>; 115 interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; 116 interrupt-parent = <&pic>; 117 }; 118 119 sata@8,0 { 120 compatible = "pci0014,7a08.0", 121 "pci0014,7a08", 122 "pciclass010601", 123 "pciclass0106"; 124 125 reg = <0x4000 0x0 0x0 0x0 0x0>; 126 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 127 interrupt-parent = <&pic>; 128 }; 129 130 sata@8,1 { 131 compatible = "pci0014,7a08.0", 132 "pci0014,7a08", 133 "pciclass010601", 134 "pciclass0106"; 135 136 reg = <0x4100 0x0 0x0 0x0 0x0>; 137 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; 138 interrupt-parent = <&pic>; 139 }; 140 141 sata@8,2 { 142 compatible = "pci0014,7a08.0", 143 "pci0014,7a08", 144 "pciclass010601", 145 "pciclass0106"; 146 147 reg = <0x4200 0x0 0x0 0x0 0x0>; 148 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; 149 interrupt-parent = <&pic>; 150 }; 151 152 gpu@6,0 { 153 compatible = "pci0014,7a15.0", 154 "pci0014,7a15", 155 "pciclass030200", 156 "pciclass0302"; 157 158 reg = <0x3000 0x0 0x0 0x0 0x0>; 159 interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; 160 interrupt-parent = <&pic>; 161 }; 162 163 dc@6,1 { 164 compatible = "pci0014,7a06.0", 165 "pci0014,7a06", 166 "pciclass030000", 167 "pciclass0300"; 168 169 reg = <0x3100 0x0 0x0 0x0 0x0>; 170 interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; 171 interrupt-parent = <&pic>; 172 }; 173 174 hda@7,0 { 175 compatible = "pci0014,7a07.0", 176 "pci0014,7a07", 177 "pciclass040300", 178 "pciclass0403"; 179 180 reg = <0x3800 0x0 0x0 0x0 0x0>; 181 interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; 182 interrupt-parent = <&pic>; 183 }; 184 185 gmac@3,0 { 186 compatible = "pci0014,7a03.0", 187 "pci0014,7a03", 188 "pciclass020000", 189 "pciclass0200"; 190 191 reg = <0x1800 0x0 0x0 0x0 0x0>; 192 interrupts = <12 IRQ_TYPE_LEVEL_HIGH>, 193 <13 IRQ_TYPE_LEVEL_HIGH>; 194 interrupt-names = "macirq", "eth_lpi"; 195 interrupt-parent = <&pic>; 196 phy-mode = "rgmii"; 197 mdio { 198 #address-cells = <1>; 199 #size-cells = <0>; 200 compatible = "snps,dwmac-mdio"; 201 phy0: ethernet-phy@0 { 202 reg = <0>; 203 }; 204 }; 205 }; 206 207 gmac@3,1 { 208 compatible = "pci0014,7a03.0", 209 "pci0014,7a03", 210 "pciclass020000", 211 "pciclass0200", 212 "loongson, pci-gmac"; 213 214 reg = <0x1900 0x0 0x0 0x0 0x0>; 215 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, 216 <15 IRQ_TYPE_LEVEL_HIGH>; 217 interrupt-names = "macirq", "eth_lpi"; 218 interrupt-parent = <&pic>; 219 phy-mode = "rgmii"; 220 mdio { 221 #address-cells = <1>; 222 #size-cells = <0>; 223 compatible = "snps,dwmac-mdio"; 224 phy1: ethernet-phy@1 { 225 reg = <0>; 226 }; 227 }; 228 }; 229 230 pci_bridge@9,0 { 231 compatible = "pci0014,7a19.1", 232 "pci0014,7a19", 233 "pciclass060400", 234 "pciclass0604"; 235 236 reg = <0x4800 0x0 0x0 0x0 0x0>; 237 interrupts = <32 IRQ_TYPE_LEVEL_HIGH>; 238 interrupt-parent = <&pic>; 239 240 #interrupt-cells = <1>; 241 interrupt-map-mask = <0 0 0 0>; 242 interrupt-map = <0 0 0 0 &pic 32 IRQ_TYPE_LEVEL_HIGH>; 243 }; 244 245 pci_bridge@a,0 { 246 compatible = "pci0014,7a09.1", 247 "pci0014,7a09", 248 "pciclass060400", 249 "pciclass0604"; 250 251 reg = <0x5000 0x0 0x0 0x0 0x0>; 252 interrupts = <33 IRQ_TYPE_LEVEL_HIGH>; 253 interrupt-parent = <&pic>; 254 255 #interrupt-cells = <1>; 256 interrupt-map-mask = <0 0 0 0>; 257 interrupt-map = <0 0 0 0 &pic 33 IRQ_TYPE_LEVEL_HIGH>; 258 }; 259 260 pci_bridge@b,0 { 261 compatible = "pci0014,7a09.1", 262 "pci0014,7a09", 263 "pciclass060400", 264 "pciclass0604"; 265 266 reg = <0x5800 0x0 0x0 0x0 0x0>; 267 interrupts = <34 IRQ_TYPE_LEVEL_HIGH>; 268 interrupt-parent = <&pic>; 269 270 #interrupt-cells = <1>; 271 interrupt-map-mask = <0 0 0 0>; 272 interrupt-map = <0 0 0 0 &pic 34 IRQ_TYPE_LEVEL_HIGH>; 273 }; 274 275 pci_bridge@c,0 { 276 compatible = "pci0014,7a09.1", 277 "pci0014,7a09", 278 "pciclass060400", 279 "pciclass0604"; 280 281 reg = <0x6000 0x0 0x0 0x0 0x0>; 282 interrupts = <35 IRQ_TYPE_LEVEL_HIGH>; 283 interrupt-parent = <&pic>; 284 285 #interrupt-cells = <1>; 286 interrupt-map-mask = <0 0 0 0>; 287 interrupt-map = <0 0 0 0 &pic 35 IRQ_TYPE_LEVEL_HIGH>; 288 }; 289 290 pci_bridge@d,0 { 291 compatible = "pci0014,7a19.1", 292 "pci0014,7a19", 293 "pciclass060400", 294 "pciclass0604"; 295 296 reg = <0x6800 0x0 0x0 0x0 0x0>; 297 interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; 298 interrupt-parent = <&pic>; 299 300 #interrupt-cells = <1>; 301 interrupt-map-mask = <0 0 0 0>; 302 interrupt-map = <0 0 0 0 &pic 36 IRQ_TYPE_LEVEL_HIGH>; 303 }; 304 305 pci_bridge@e,0 { 306 compatible = "pci0014,7a09.1", 307 "pci0014,7a09", 308 "pciclass060400", 309 "pciclass0604"; 310 311 reg = <0x7000 0x0 0x0 0x0 0x0>; 312 interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; 313 interrupt-parent = <&pic>; 314 315 #interrupt-cells = <1>; 316 interrupt-map-mask = <0 0 0 0>; 317 interrupt-map = <0 0 0 0 &pic 37 IRQ_TYPE_LEVEL_HIGH>; 318 }; 319 320 pci_bridge@f,0 { 321 compatible = "pci0014,7a29.1", 322 "pci0014,7a29", 323 "pciclass060400", 324 "pciclass0604"; 325 326 reg = <0x7800 0x0 0x0 0x0 0x0>; 327 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; 328 interrupt-parent = <&pic>; 329 330 #interrupt-cells = <1>; 331 interrupt-map-mask = <0 0 0 0>; 332 interrupt-map = <0 0 0 0 &pic 40 IRQ_TYPE_LEVEL_HIGH>; 333 }; 334 335 pci_bridge@10,0 { 336 compatible = "pci0014,7a19.1", 337 "pci0014,7a19", 338 "pciclass060400", 339 "pciclass0604"; 340 341 reg = <0x8000 0x0 0x0 0x0 0x0>; 342 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; 343 interrupt-parent = <&pic>; 344 345 #interrupt-cells = <1>; 346 interrupt-map-mask = <0 0 0 0>; 347 interrupt-map = <0 0 0 0 &pic 41 IRQ_TYPE_LEVEL_HIGH>; 348 }; 349 350 pci_bridge@11,0 { 351 compatible = "pci0014,7a29.1", 352 "pci0014,7a29", 353 "pciclass060400", 354 "pciclass0604"; 355 356 reg = <0x8800 0x0 0x0 0x0 0x0>; 357 interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; 358 interrupt-parent = <&pic>; 359 360 #interrupt-cells = <1>; 361 interrupt-map-mask = <0 0 0 0>; 362 interrupt-map = <0 0 0 0 &pic 42 IRQ_TYPE_LEVEL_HIGH>; 363 }; 364 365 pci_bridge@12,0 { 366 compatible = "pci0014,7a19.1", 367 "pci0014,7a19", 368 "pciclass060400", 369 "pciclass0604"; 370 371 reg = <0x9000 0x0 0x0 0x0 0x0>; 372 interrupts = <43 IRQ_TYPE_LEVEL_HIGH>; 373 interrupt-parent = <&pic>; 374 375 #interrupt-cells = <1>; 376 interrupt-map-mask = <0 0 0 0>; 377 interrupt-map = <0 0 0 0 &pic 43 IRQ_TYPE_LEVEL_HIGH>; 378 }; 379 380 pci_bridge@13,0 { 381 compatible = "pci0014,7a29.1", 382 "pci0014,7a29", 383 "pciclass060400", 384 "pciclass0604"; 385 386 reg = <0x9800 0x0 0x0 0x0 0x0>; 387 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; 388 interrupt-parent = <&pic>; 389 390 #interrupt-cells = <1>; 391 interrupt-map-mask = <0 0 0 0>; 392 interrupt-map = <0 0 0 0 &pic 38 IRQ_TYPE_LEVEL_HIGH>; 393 }; 394 395 pci_bridge@14,0 { 396 compatible = "pci0014,7a19.1", 397 "pci0014,7a19", 398 "pciclass060400", 399 "pciclass0604"; 400 401 reg = <0xa000 0x0 0x0 0x0 0x0>; 402 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; 403 interrupt-parent = <&pic>; 404 405 #interrupt-cells = <1>; 406 interrupt-map-mask = <0 0 0 0>; 407 interrupt-map = <0 0 0 0 &pic 39 IRQ_TYPE_LEVEL_HIGH>; 408 }; 409 }; 410 411 isa@18000000 { 412 compatible = "isa"; 413 #address-cells = <2>; 414 #size-cells = <1>; 415 ranges = <1 0 0 0x18000000 0x20000>; 416 }; 417 }; 418}; 419