Searched refs:wrmsr (Results 1 – 25 of 41) sorted by relevance
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/arch/x86/include/asm/ |
D | extable.h | 45 extern void ex_handler_msr_mce(struct pt_regs *regs, bool wrmsr); 47 static inline void ex_handler_msr_mce(struct pt_regs *regs, bool wrmsr) { } in ex_handler_msr_mce() argument
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D | resctrl.h | 80 wrmsr(IA32_PQR_ASSOC, rmid, closid); in __resctrl_sched_in()
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D | switch_to.h | 60 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); in refresh_sysenter_cs()
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/arch/x86/kernel/cpu/ |
D | centaur.c | 34 wrmsr(MSR_VIA_FCR, lo, hi); in init_c3() 42 wrmsr(MSR_VIA_RNG, lo, hi); in init_c3() 56 wrmsr(MSR_VIA_FCR, lo, hi); in init_c3() 190 wrmsr(MSR_IDT_FCR1, newlo, hi); in init_centaur()
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D | transmeta.c | 87 wrmsr(0x80860004, ~0, uk); in init_transmeta() 89 wrmsr(0x80860004, cap_mask, uk); in init_transmeta()
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D | zhaoxin.c | 33 wrmsr(MSR_ZHAOXIN_FCR57, lo, hi); in init_zhaoxin_cap() 42 wrmsr(MSR_ZHAOXIN_FCR57, lo, hi); in init_zhaoxin_cap()
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D | umwait.c | 36 wrmsr(MSR_IA32_UMWAIT_CONTROL, READ_ONCE(umwait_control_cached), 0); in umwait_update_control_msr() 74 wrmsr(MSR_IA32_UMWAIT_CONTROL, orig_umwait_control_cached, 0); in umwait_cpu_offline()
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D | amd.c | 249 wrmsr(MSR_K6_WHCR, l, h); in init_amd_k6() 270 wrmsr(MSR_K6_WHCR, l, h); in init_amd_k6() 315 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); in init_amd_k7() 1263 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0); in set_dr_addr_mask() 1268 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0); in set_dr_addr_mask()
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/arch/x86/mm/ |
D | extable.c | 87 struct pt_regs *regs, bool wrmsr, bool safe, int reg) in ex_handler_msr() argument 89 if (__ONCE_LITE_IF(!safe && wrmsr)) { in ex_handler_msr() 96 if (__ONCE_LITE_IF(!safe && !wrmsr)) { in ex_handler_msr() 102 if (!wrmsr) { in ex_handler_msr()
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D | mem_encrypt_boot.S | 121 wrmsr 152 wrmsr
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/arch/x86/entry/ |
D | entry.S | 16 wrmsr
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D | calling.h | 318 wrmsr 341 wrmsr
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/arch/x86/hyperv/ |
D | hv_apic.c | 79 wrmsr(HV_X64_MSR_EOI, val, 0); in hv_apic_write() 82 wrmsr(HV_X64_MSR_TPR, val, 0); in hv_apic_write() 96 wrmsr(HV_X64_MSR_EOI, val, 0); in hv_apic_eoi_write()
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/arch/x86/kernel/cpu/mce/ |
D | winchip.c | 40 wrmsr(MSR_IDT_FCR1, lo, hi); in winchip_mcheck_init()
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/arch/x86/platform/pvh/ |
D | head.S | 82 wrmsr 100 wrmsr
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/arch/x86/realmode/rm/ |
D | wakeup_asm.S | 104 wrmsr 124 wrmsr
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D | trampoline_64.S | 135 wrmsr 149 wrmsr
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D | reboot.S | 40 wrmsr
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/arch/x86/boot/compressed/ |
D | efi_thunk_64.S | 126 wrmsr 154 wrmsr
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D | mem_encrypt.S | 78 wrmsr 179 wrmsr
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/arch/x86/kernel/ |
D | verify_cpu.S | 97 wrmsr 128 wrmsr
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/arch/x86/kernel/cpu/mtrr/ |
D | amd.c | 92 wrmsr(MSR_K6_UWCCR, regs[0], regs[1]); in amd_set_mtrr()
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D | centaur.c | 96 wrmsr(MSR_IDT_MCR0 + reg, low, high); in centaur_set_mcr()
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/arch/x86/lib/ |
D | msr-reg.S | 92 op_safe_regs wrmsr
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/arch/x86/xen/ |
D | xen-head.S | 50 wrmsr
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