1 // SPDX-License-Identifier: GPL-2.0-only
2 #include <linux/export.h>
3 #include <linux/bitops.h>
4 #include <linux/elf.h>
5 #include <linux/mm.h>
6
7 #include <linux/io.h>
8 #include <linux/sched.h>
9 #include <linux/sched/clock.h>
10 #include <linux/random.h>
11 #include <linux/topology.h>
12 #include <asm/processor.h>
13 #include <asm/apic.h>
14 #include <asm/cacheinfo.h>
15 #include <asm/cpu.h>
16 #include <asm/spec-ctrl.h>
17 #include <asm/smp.h>
18 #include <asm/numa.h>
19 #include <asm/pci-direct.h>
20 #include <asm/delay.h>
21 #include <asm/debugreg.h>
22 #include <asm/resctrl.h>
23
24 #ifdef CONFIG_X86_64
25 # include <asm/mmconfig.h>
26 #endif
27
28 #include "cpu.h"
29
30 /*
31 * nodes_per_socket: Stores the number of nodes per socket.
32 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
33 * Node Identifiers[10:8]
34 */
35 static u32 nodes_per_socket = 1;
36
37 /*
38 * AMD errata checking
39 *
40 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
41 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
42 * have an OSVW id assigned, which it takes as first argument. Both take a
43 * variable number of family-specific model-stepping ranges created by
44 * AMD_MODEL_RANGE().
45 *
46 * Example:
47 *
48 * const int amd_erratum_319[] =
49 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
50 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
51 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
52 */
53
54 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
55 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
56 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
57 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
58 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
59 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
60 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
61
62 static const int amd_erratum_400[] =
63 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
64 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
65
66 static const int amd_erratum_383[] =
67 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
68
69 /* #1054: Instructions Retired Performance Counter May Be Inaccurate */
70 static const int amd_erratum_1054[] =
71 AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
72
73 static const int amd_zenbleed[] =
74 AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x30, 0x0, 0x4f, 0xf),
75 AMD_MODEL_RANGE(0x17, 0x60, 0x0, 0x7f, 0xf),
76 AMD_MODEL_RANGE(0x17, 0x90, 0x0, 0x91, 0xf),
77 AMD_MODEL_RANGE(0x17, 0xa0, 0x0, 0xaf, 0xf));
78
79 static const int amd_div0[] =
80 AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x00, 0x0, 0x2f, 0xf),
81 AMD_MODEL_RANGE(0x17, 0x50, 0x0, 0x5f, 0xf));
82
83 static const int amd_erratum_1485[] =
84 AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x19, 0x10, 0x0, 0x1f, 0xf),
85 AMD_MODEL_RANGE(0x19, 0x60, 0x0, 0xaf, 0xf));
86
cpu_has_amd_erratum(struct cpuinfo_x86 * cpu,const int * erratum)87 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
88 {
89 int osvw_id = *erratum++;
90 u32 range;
91 u32 ms;
92
93 if (osvw_id >= 0 && osvw_id < 65536 &&
94 cpu_has(cpu, X86_FEATURE_OSVW)) {
95 u64 osvw_len;
96
97 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
98 if (osvw_id < osvw_len) {
99 u64 osvw_bits;
100
101 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
102 osvw_bits);
103 return osvw_bits & (1ULL << (osvw_id & 0x3f));
104 }
105 }
106
107 /* OSVW unavailable or ID unknown, match family-model-stepping range */
108 ms = (cpu->x86_model << 4) | cpu->x86_stepping;
109 while ((range = *erratum++))
110 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
111 (ms >= AMD_MODEL_RANGE_START(range)) &&
112 (ms <= AMD_MODEL_RANGE_END(range)))
113 return true;
114
115 return false;
116 }
117
rdmsrl_amd_safe(unsigned msr,unsigned long long * p)118 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
119 {
120 u32 gprs[8] = { 0 };
121 int err;
122
123 WARN_ONCE((boot_cpu_data.x86 != 0xf),
124 "%s should only be used on K8!\n", __func__);
125
126 gprs[1] = msr;
127 gprs[7] = 0x9c5a203a;
128
129 err = rdmsr_safe_regs(gprs);
130
131 *p = gprs[0] | ((u64)gprs[2] << 32);
132
133 return err;
134 }
135
wrmsrl_amd_safe(unsigned msr,unsigned long long val)136 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
137 {
138 u32 gprs[8] = { 0 };
139
140 WARN_ONCE((boot_cpu_data.x86 != 0xf),
141 "%s should only be used on K8!\n", __func__);
142
143 gprs[0] = (u32)val;
144 gprs[1] = msr;
145 gprs[2] = val >> 32;
146 gprs[7] = 0x9c5a203a;
147
148 return wrmsr_safe_regs(gprs);
149 }
150
151 /*
152 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
153 * misexecution of code under Linux. Owners of such processors should
154 * contact AMD for precise details and a CPU swap.
155 *
156 * See http://www.multimania.com/poulot/k6bug.html
157 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
158 * (Publication # 21266 Issue Date: August 1998)
159 *
160 * The following test is erm.. interesting. AMD neglected to up
161 * the chip setting when fixing the bug but they also tweaked some
162 * performance at the same time..
163 */
164
165 #ifdef CONFIG_X86_32
166 extern __visible void vide(void);
167 __asm__(".text\n"
168 ".globl vide\n"
169 ".type vide, @function\n"
170 ".align 4\n"
171 "vide: ret\n");
172 #endif
173
init_amd_k5(struct cpuinfo_x86 * c)174 static void init_amd_k5(struct cpuinfo_x86 *c)
175 {
176 #ifdef CONFIG_X86_32
177 /*
178 * General Systems BIOSen alias the cpu frequency registers
179 * of the Elan at 0x000df000. Unfortunately, one of the Linux
180 * drivers subsequently pokes it, and changes the CPU speed.
181 * Workaround : Remove the unneeded alias.
182 */
183 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
184 #define CBAR_ENB (0x80000000)
185 #define CBAR_KEY (0X000000CB)
186 if (c->x86_model == 9 || c->x86_model == 10) {
187 if (inl(CBAR) & CBAR_ENB)
188 outl(0 | CBAR_KEY, CBAR);
189 }
190 #endif
191 }
192
init_amd_k6(struct cpuinfo_x86 * c)193 static void init_amd_k6(struct cpuinfo_x86 *c)
194 {
195 #ifdef CONFIG_X86_32
196 u32 l, h;
197 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
198
199 if (c->x86_model < 6) {
200 /* Based on AMD doc 20734R - June 2000 */
201 if (c->x86_model == 0) {
202 clear_cpu_cap(c, X86_FEATURE_APIC);
203 set_cpu_cap(c, X86_FEATURE_PGE);
204 }
205 return;
206 }
207
208 if (c->x86_model == 6 && c->x86_stepping == 1) {
209 const int K6_BUG_LOOP = 1000000;
210 int n;
211 void (*f_vide)(void);
212 u64 d, d2;
213
214 pr_info("AMD K6 stepping B detected - ");
215
216 /*
217 * It looks like AMD fixed the 2.6.2 bug and improved indirect
218 * calls at the same time.
219 */
220
221 n = K6_BUG_LOOP;
222 f_vide = vide;
223 OPTIMIZER_HIDE_VAR(f_vide);
224 d = rdtsc();
225 while (n--)
226 f_vide();
227 d2 = rdtsc();
228 d = d2-d;
229
230 if (d > 20*K6_BUG_LOOP)
231 pr_cont("system stability may be impaired when more than 32 MB are used.\n");
232 else
233 pr_cont("probably OK (after B9730xxxx).\n");
234 }
235
236 /* K6 with old style WHCR */
237 if (c->x86_model < 8 ||
238 (c->x86_model == 8 && c->x86_stepping < 8)) {
239 /* We can only write allocate on the low 508Mb */
240 if (mbytes > 508)
241 mbytes = 508;
242
243 rdmsr(MSR_K6_WHCR, l, h);
244 if ((l&0x0000FFFF) == 0) {
245 unsigned long flags;
246 l = (1<<0)|((mbytes/4)<<1);
247 local_irq_save(flags);
248 wbinvd();
249 wrmsr(MSR_K6_WHCR, l, h);
250 local_irq_restore(flags);
251 pr_info("Enabling old style K6 write allocation for %d Mb\n",
252 mbytes);
253 }
254 return;
255 }
256
257 if ((c->x86_model == 8 && c->x86_stepping > 7) ||
258 c->x86_model == 9 || c->x86_model == 13) {
259 /* The more serious chips .. */
260
261 if (mbytes > 4092)
262 mbytes = 4092;
263
264 rdmsr(MSR_K6_WHCR, l, h);
265 if ((l&0xFFFF0000) == 0) {
266 unsigned long flags;
267 l = ((mbytes>>2)<<22)|(1<<16);
268 local_irq_save(flags);
269 wbinvd();
270 wrmsr(MSR_K6_WHCR, l, h);
271 local_irq_restore(flags);
272 pr_info("Enabling new style K6 write allocation for %d Mb\n",
273 mbytes);
274 }
275
276 return;
277 }
278
279 if (c->x86_model == 10) {
280 /* AMD Geode LX is model 10 */
281 /* placeholder for any needed mods */
282 return;
283 }
284 #endif
285 }
286
init_amd_k7(struct cpuinfo_x86 * c)287 static void init_amd_k7(struct cpuinfo_x86 *c)
288 {
289 #ifdef CONFIG_X86_32
290 u32 l, h;
291
292 /*
293 * Bit 15 of Athlon specific MSR 15, needs to be 0
294 * to enable SSE on Palomino/Morgan/Barton CPU's.
295 * If the BIOS didn't enable it already, enable it here.
296 */
297 if (c->x86_model >= 6 && c->x86_model <= 10) {
298 if (!cpu_has(c, X86_FEATURE_XMM)) {
299 pr_info("Enabling disabled K7/SSE Support.\n");
300 msr_clear_bit(MSR_K7_HWCR, 15);
301 set_cpu_cap(c, X86_FEATURE_XMM);
302 }
303 }
304
305 /*
306 * It's been determined by AMD that Athlons since model 8 stepping 1
307 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
308 * As per AMD technical note 27212 0.2
309 */
310 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) {
311 rdmsr(MSR_K7_CLK_CTL, l, h);
312 if ((l & 0xfff00000) != 0x20000000) {
313 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
314 l, ((l & 0x000fffff)|0x20000000));
315 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
316 }
317 }
318
319 /* calling is from identify_secondary_cpu() ? */
320 if (!c->cpu_index)
321 return;
322
323 /*
324 * Certain Athlons might work (for various values of 'work') in SMP
325 * but they are not certified as MP capable.
326 */
327 /* Athlon 660/661 is valid. */
328 if ((c->x86_model == 6) && ((c->x86_stepping == 0) ||
329 (c->x86_stepping == 1)))
330 return;
331
332 /* Duron 670 is valid */
333 if ((c->x86_model == 7) && (c->x86_stepping == 0))
334 return;
335
336 /*
337 * Athlon 662, Duron 671, and Athlon >model 7 have capability
338 * bit. It's worth noting that the A5 stepping (662) of some
339 * Athlon XP's have the MP bit set.
340 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
341 * more.
342 */
343 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) ||
344 ((c->x86_model == 7) && (c->x86_stepping >= 1)) ||
345 (c->x86_model > 7))
346 if (cpu_has(c, X86_FEATURE_MP))
347 return;
348
349 /* If we get here, not a certified SMP capable AMD system. */
350
351 /*
352 * Don't taint if we are running SMP kernel on a single non-MP
353 * approved Athlon
354 */
355 WARN_ONCE(1, "WARNING: This combination of AMD"
356 " processors is not suitable for SMP.\n");
357 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
358 #endif
359 }
360
361 #ifdef CONFIG_NUMA
362 /*
363 * To workaround broken NUMA config. Read the comment in
364 * srat_detect_node().
365 */
nearby_node(int apicid)366 static int nearby_node(int apicid)
367 {
368 int i, node;
369
370 for (i = apicid - 1; i >= 0; i--) {
371 node = __apicid_to_node[i];
372 if (node != NUMA_NO_NODE && node_online(node))
373 return node;
374 }
375 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
376 node = __apicid_to_node[i];
377 if (node != NUMA_NO_NODE && node_online(node))
378 return node;
379 }
380 return first_node(node_online_map); /* Shouldn't happen */
381 }
382 #endif
383
384 /*
385 * Fix up cpu_core_id for pre-F17h systems to be in the
386 * [0 .. cores_per_node - 1] range. Not really needed but
387 * kept so as not to break existing setups.
388 */
legacy_fixup_core_id(struct cpuinfo_x86 * c)389 static void legacy_fixup_core_id(struct cpuinfo_x86 *c)
390 {
391 u32 cus_per_node;
392
393 if (c->x86 >= 0x17)
394 return;
395
396 cus_per_node = c->x86_max_cores / nodes_per_socket;
397 c->cpu_core_id %= cus_per_node;
398 }
399
400 /*
401 * Fixup core topology information for
402 * (1) AMD multi-node processors
403 * Assumption: Number of cores in each internal node is the same.
404 * (2) AMD processors supporting compute units
405 */
amd_get_topology(struct cpuinfo_x86 * c)406 static void amd_get_topology(struct cpuinfo_x86 *c)
407 {
408 int cpu = smp_processor_id();
409
410 /* get information required for multi-node processors */
411 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
412 int err;
413 u32 eax, ebx, ecx, edx;
414
415 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
416
417 c->cpu_die_id = ecx & 0xff;
418
419 if (c->x86 == 0x15)
420 c->cu_id = ebx & 0xff;
421
422 if (c->x86 >= 0x17) {
423 c->cpu_core_id = ebx & 0xff;
424
425 if (smp_num_siblings > 1)
426 c->x86_max_cores /= smp_num_siblings;
427 }
428
429 /*
430 * In case leaf B is available, use it to derive
431 * topology information.
432 */
433 err = detect_extended_topology(c);
434 if (!err)
435 c->x86_coreid_bits = get_count_order(c->x86_max_cores);
436
437 cacheinfo_amd_init_llc_id(c, cpu);
438
439 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
440 u64 value;
441
442 rdmsrl(MSR_FAM10H_NODE_ID, value);
443 c->cpu_die_id = value & 7;
444
445 per_cpu(cpu_llc_id, cpu) = c->cpu_die_id;
446 } else
447 return;
448
449 if (nodes_per_socket > 1) {
450 set_cpu_cap(c, X86_FEATURE_AMD_DCM);
451 legacy_fixup_core_id(c);
452 }
453 }
454
455 /*
456 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores.
457 * Assumes number of cores is a power of two.
458 */
amd_detect_cmp(struct cpuinfo_x86 * c)459 static void amd_detect_cmp(struct cpuinfo_x86 *c)
460 {
461 unsigned bits;
462 int cpu = smp_processor_id();
463
464 bits = c->x86_coreid_bits;
465 /* Low order bits define the core id (index of core in socket) */
466 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
467 /* Convert the initial APIC ID into the socket ID */
468 c->phys_proc_id = c->initial_apicid >> bits;
469 /* use socket ID also for last level cache */
470 per_cpu(cpu_llc_id, cpu) = c->cpu_die_id = c->phys_proc_id;
471 }
472
amd_detect_ppin(struct cpuinfo_x86 * c)473 static void amd_detect_ppin(struct cpuinfo_x86 *c)
474 {
475 unsigned long long val;
476
477 if (!cpu_has(c, X86_FEATURE_AMD_PPIN))
478 return;
479
480 /* When PPIN is defined in CPUID, still need to check PPIN_CTL MSR */
481 if (rdmsrl_safe(MSR_AMD_PPIN_CTL, &val))
482 goto clear_ppin;
483
484 /* PPIN is locked in disabled mode, clear feature bit */
485 if ((val & 3UL) == 1UL)
486 goto clear_ppin;
487
488 /* If PPIN is disabled, try to enable it */
489 if (!(val & 2UL)) {
490 wrmsrl_safe(MSR_AMD_PPIN_CTL, val | 2UL);
491 rdmsrl_safe(MSR_AMD_PPIN_CTL, &val);
492 }
493
494 /* If PPIN_EN bit is 1, return from here; otherwise fall through */
495 if (val & 2UL)
496 return;
497
498 clear_ppin:
499 clear_cpu_cap(c, X86_FEATURE_AMD_PPIN);
500 }
501
amd_get_nodes_per_socket(void)502 u32 amd_get_nodes_per_socket(void)
503 {
504 return nodes_per_socket;
505 }
506 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket);
507
srat_detect_node(struct cpuinfo_x86 * c)508 static void srat_detect_node(struct cpuinfo_x86 *c)
509 {
510 #ifdef CONFIG_NUMA
511 int cpu = smp_processor_id();
512 int node;
513 unsigned apicid = c->apicid;
514
515 node = numa_cpu_node(cpu);
516 if (node == NUMA_NO_NODE)
517 node = get_llc_id(cpu);
518
519 /*
520 * On multi-fabric platform (e.g. Numascale NumaChip) a
521 * platform-specific handler needs to be called to fixup some
522 * IDs of the CPU.
523 */
524 if (x86_cpuinit.fixup_cpu_id)
525 x86_cpuinit.fixup_cpu_id(c, node);
526
527 if (!node_online(node)) {
528 /*
529 * Two possibilities here:
530 *
531 * - The CPU is missing memory and no node was created. In
532 * that case try picking one from a nearby CPU.
533 *
534 * - The APIC IDs differ from the HyperTransport node IDs
535 * which the K8 northbridge parsing fills in. Assume
536 * they are all increased by a constant offset, but in
537 * the same order as the HT nodeids. If that doesn't
538 * result in a usable node fall back to the path for the
539 * previous case.
540 *
541 * This workaround operates directly on the mapping between
542 * APIC ID and NUMA node, assuming certain relationship
543 * between APIC ID, HT node ID and NUMA topology. As going
544 * through CPU mapping may alter the outcome, directly
545 * access __apicid_to_node[].
546 */
547 int ht_nodeid = c->initial_apicid;
548
549 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
550 node = __apicid_to_node[ht_nodeid];
551 /* Pick a nearby node */
552 if (!node_online(node))
553 node = nearby_node(apicid);
554 }
555 numa_set_node(cpu, node);
556 #endif
557 }
558
early_init_amd_mc(struct cpuinfo_x86 * c)559 static void early_init_amd_mc(struct cpuinfo_x86 *c)
560 {
561 #ifdef CONFIG_SMP
562 unsigned bits, ecx;
563
564 /* Multi core CPU? */
565 if (c->extended_cpuid_level < 0x80000008)
566 return;
567
568 ecx = cpuid_ecx(0x80000008);
569
570 c->x86_max_cores = (ecx & 0xff) + 1;
571
572 /* CPU telling us the core id bits shift? */
573 bits = (ecx >> 12) & 0xF;
574
575 /* Otherwise recompute */
576 if (bits == 0) {
577 while ((1 << bits) < c->x86_max_cores)
578 bits++;
579 }
580
581 c->x86_coreid_bits = bits;
582 #endif
583 }
584
bsp_init_amd(struct cpuinfo_x86 * c)585 static void bsp_init_amd(struct cpuinfo_x86 *c)
586 {
587 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
588
589 if (c->x86 > 0x10 ||
590 (c->x86 == 0x10 && c->x86_model >= 0x2)) {
591 u64 val;
592
593 rdmsrl(MSR_K7_HWCR, val);
594 if (!(val & BIT(24)))
595 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
596 }
597 }
598
599 if (c->x86 == 0x15) {
600 unsigned long upperbit;
601 u32 cpuid, assoc;
602
603 cpuid = cpuid_edx(0x80000005);
604 assoc = cpuid >> 16 & 0xff;
605 upperbit = ((cpuid >> 24) << 10) / assoc;
606
607 va_align.mask = (upperbit - 1) & PAGE_MASK;
608 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64;
609
610 /* A random value per boot for bit slice [12:upper_bit) */
611 va_align.bits = get_random_int() & va_align.mask;
612 }
613
614 if (cpu_has(c, X86_FEATURE_MWAITX))
615 use_mwaitx_delay();
616
617 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
618 u32 ecx;
619
620 ecx = cpuid_ecx(0x8000001e);
621 __max_die_per_package = nodes_per_socket = ((ecx >> 8) & 7) + 1;
622 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
623 u64 value;
624
625 rdmsrl(MSR_FAM10H_NODE_ID, value);
626 __max_die_per_package = nodes_per_socket = ((value >> 3) & 7) + 1;
627 }
628
629 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) &&
630 !boot_cpu_has(X86_FEATURE_VIRT_SSBD) &&
631 c->x86 >= 0x15 && c->x86 <= 0x17) {
632 unsigned int bit;
633
634 switch (c->x86) {
635 case 0x15: bit = 54; break;
636 case 0x16: bit = 33; break;
637 case 0x17: bit = 10; break;
638 default: return;
639 }
640 /*
641 * Try to cache the base value so further operations can
642 * avoid RMW. If that faults, do not enable SSBD.
643 */
644 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
645 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD);
646 setup_force_cpu_cap(X86_FEATURE_SSBD);
647 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit;
648 }
649 }
650
651 resctrl_cpu_detect(c);
652 }
653
early_detect_mem_encrypt(struct cpuinfo_x86 * c)654 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
655 {
656 u64 msr;
657
658 /*
659 * BIOS support is required for SME and SEV.
660 * For SME: If BIOS has enabled SME then adjust x86_phys_bits by
661 * the SME physical address space reduction value.
662 * If BIOS has not enabled SME then don't advertise the
663 * SME feature (set in scattered.c).
664 * For SEV: If BIOS has not enabled SEV then don't advertise the
665 * SEV and SEV_ES feature (set in scattered.c).
666 *
667 * In all cases, since support for SME and SEV requires long mode,
668 * don't advertise the feature under CONFIG_X86_32.
669 */
670 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) {
671 /* Check if memory encryption is enabled */
672 rdmsrl(MSR_AMD64_SYSCFG, msr);
673 if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
674 goto clear_all;
675
676 /*
677 * Always adjust physical address bits. Even though this
678 * will be a value above 32-bits this is still done for
679 * CONFIG_X86_32 so that accurate values are reported.
680 */
681 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f;
682
683 if (IS_ENABLED(CONFIG_X86_32))
684 goto clear_all;
685
686 rdmsrl(MSR_K7_HWCR, msr);
687 if (!(msr & MSR_K7_HWCR_SMMLOCK))
688 goto clear_sev;
689
690 return;
691
692 clear_all:
693 setup_clear_cpu_cap(X86_FEATURE_SME);
694 clear_sev:
695 setup_clear_cpu_cap(X86_FEATURE_SEV);
696 setup_clear_cpu_cap(X86_FEATURE_SEV_ES);
697 }
698 }
699
early_init_amd(struct cpuinfo_x86 * c)700 static void early_init_amd(struct cpuinfo_x86 *c)
701 {
702 u64 value;
703 u32 dummy;
704
705 early_init_amd_mc(c);
706
707 if (c->x86 >= 0xf)
708 set_cpu_cap(c, X86_FEATURE_K8);
709
710 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
711
712 /*
713 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
714 * with P/T states and does not stop in deep C-states
715 */
716 if (c->x86_power & (1 << 8)) {
717 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
718 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
719 }
720
721 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
722 if (c->x86_power & BIT(12))
723 set_cpu_cap(c, X86_FEATURE_ACC_POWER);
724
725 /* Bit 14 indicates the Runtime Average Power Limit interface. */
726 if (c->x86_power & BIT(14))
727 set_cpu_cap(c, X86_FEATURE_RAPL);
728
729 #ifdef CONFIG_X86_64
730 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
731 #else
732 /* Set MTRR capability flag if appropriate */
733 if (c->x86 == 5)
734 if (c->x86_model == 13 || c->x86_model == 9 ||
735 (c->x86_model == 8 && c->x86_stepping >= 8))
736 set_cpu_cap(c, X86_FEATURE_K6_MTRR);
737 #endif
738 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
739 /*
740 * ApicID can always be treated as an 8-bit value for AMD APIC versions
741 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we
742 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families
743 * after 16h.
744 */
745 if (boot_cpu_has(X86_FEATURE_APIC)) {
746 if (c->x86 > 0x16)
747 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
748 else if (c->x86 >= 0xf) {
749 /* check CPU config space for extended APIC ID */
750 unsigned int val;
751
752 val = read_pci_config(0, 24, 0, 0x68);
753 if ((val >> 17 & 0x3) == 0x3)
754 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
755 }
756 }
757 #endif
758
759 /*
760 * This is only needed to tell the kernel whether to use VMCALL
761 * and VMMCALL. VMMCALL is never executed except under virt, so
762 * we can set it unconditionally.
763 */
764 set_cpu_cap(c, X86_FEATURE_VMMCALL);
765
766 /* F16h erratum 793, CVE-2013-6885 */
767 if (c->x86 == 0x16 && c->x86_model <= 0xf)
768 msr_set_bit(MSR_AMD64_LS_CFG, 15);
769
770 /*
771 * Check whether the machine is affected by erratum 400. This is
772 * used to select the proper idle routine and to enable the check
773 * whether the machine is affected in arch_post_acpi_init(), which
774 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check.
775 */
776 if (cpu_has_amd_erratum(c, amd_erratum_400))
777 set_cpu_bug(c, X86_BUG_AMD_E400);
778
779 early_detect_mem_encrypt(c);
780
781 /* Re-enable TopologyExtensions if switched off by BIOS */
782 if (c->x86 == 0x15 &&
783 (c->x86_model >= 0x10 && c->x86_model <= 0x6f) &&
784 !cpu_has(c, X86_FEATURE_TOPOEXT)) {
785
786 if (msr_set_bit(0xc0011005, 54) > 0) {
787 rdmsrl(0xc0011005, value);
788 if (value & BIT_64(54)) {
789 set_cpu_cap(c, X86_FEATURE_TOPOEXT);
790 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
791 }
792 }
793 }
794
795 if (cpu_has(c, X86_FEATURE_TOPOEXT))
796 smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1;
797 }
798
init_amd_k8(struct cpuinfo_x86 * c)799 static void init_amd_k8(struct cpuinfo_x86 *c)
800 {
801 u32 level;
802 u64 value;
803
804 /* On C+ stepping K8 rep microcode works well for copy/memset */
805 level = cpuid_eax(1);
806 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
807 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
808
809 /*
810 * Some BIOSes incorrectly force this feature, but only K8 revision D
811 * (model = 0x14) and later actually support it.
812 * (AMD Erratum #110, docId: 25759).
813 */
814 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
815 clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
816 if (!rdmsrl_amd_safe(0xc001100d, &value)) {
817 value &= ~BIT_64(32);
818 wrmsrl_amd_safe(0xc001100d, value);
819 }
820 }
821
822 if (!c->x86_model_id[0])
823 strcpy(c->x86_model_id, "Hammer");
824
825 #ifdef CONFIG_SMP
826 /*
827 * Disable TLB flush filter by setting HWCR.FFDIS on K8
828 * bit 6 of msr C001_0015
829 *
830 * Errata 63 for SH-B3 steppings
831 * Errata 122 for all steppings (F+ have it disabled by default)
832 */
833 msr_set_bit(MSR_K7_HWCR, 6);
834 #endif
835 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE);
836 }
837
init_amd_gh(struct cpuinfo_x86 * c)838 static void init_amd_gh(struct cpuinfo_x86 *c)
839 {
840 #ifdef CONFIG_MMCONF_FAM10H
841 /* do this for boot cpu */
842 if (c == &boot_cpu_data)
843 check_enable_amd_mmconf_dmi();
844
845 fam10h_check_enable_mmcfg();
846 #endif
847
848 /*
849 * Disable GART TLB Walk Errors on Fam10h. We do this here because this
850 * is always needed when GART is enabled, even in a kernel which has no
851 * MCE support built in. BIOS should disable GartTlbWlk Errors already.
852 * If it doesn't, we do it here as suggested by the BKDG.
853 *
854 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
855 */
856 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
857
858 /*
859 * On family 10h BIOS may not have properly enabled WC+ support, causing
860 * it to be converted to CD memtype. This may result in performance
861 * degradation for certain nested-paging guests. Prevent this conversion
862 * by clearing bit 24 in MSR_AMD64_BU_CFG2.
863 *
864 * NOTE: we want to use the _safe accessors so as not to #GP kvm
865 * guests on older kvm hosts.
866 */
867 msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
868
869 if (cpu_has_amd_erratum(c, amd_erratum_383))
870 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
871 }
872
init_amd_ln(struct cpuinfo_x86 * c)873 static void init_amd_ln(struct cpuinfo_x86 *c)
874 {
875 /*
876 * Apply erratum 665 fix unconditionally so machines without a BIOS
877 * fix work.
878 */
879 msr_set_bit(MSR_AMD64_DE_CFG, 31);
880 }
881
882 static bool rdrand_force;
883
rdrand_cmdline(char * str)884 static int __init rdrand_cmdline(char *str)
885 {
886 if (!str)
887 return -EINVAL;
888
889 if (!strcmp(str, "force"))
890 rdrand_force = true;
891 else
892 return -EINVAL;
893
894 return 0;
895 }
896 early_param("rdrand", rdrand_cmdline);
897
clear_rdrand_cpuid_bit(struct cpuinfo_x86 * c)898 static void clear_rdrand_cpuid_bit(struct cpuinfo_x86 *c)
899 {
900 /*
901 * Saving of the MSR used to hide the RDRAND support during
902 * suspend/resume is done by arch/x86/power/cpu.c, which is
903 * dependent on CONFIG_PM_SLEEP.
904 */
905 if (!IS_ENABLED(CONFIG_PM_SLEEP))
906 return;
907
908 /*
909 * The nordrand option can clear X86_FEATURE_RDRAND, so check for
910 * RDRAND support using the CPUID function directly.
911 */
912 if (!(cpuid_ecx(1) & BIT(30)) || rdrand_force)
913 return;
914
915 msr_clear_bit(MSR_AMD64_CPUID_FN_1, 62);
916
917 /*
918 * Verify that the CPUID change has occurred in case the kernel is
919 * running virtualized and the hypervisor doesn't support the MSR.
920 */
921 if (cpuid_ecx(1) & BIT(30)) {
922 pr_info_once("BIOS may not properly restore RDRAND after suspend, but hypervisor does not support hiding RDRAND via CPUID.\n");
923 return;
924 }
925
926 clear_cpu_cap(c, X86_FEATURE_RDRAND);
927 pr_info_once("BIOS may not properly restore RDRAND after suspend, hiding RDRAND via CPUID. Use rdrand=force to reenable.\n");
928 }
929
init_amd_jg(struct cpuinfo_x86 * c)930 static void init_amd_jg(struct cpuinfo_x86 *c)
931 {
932 /*
933 * Some BIOS implementations do not restore proper RDRAND support
934 * across suspend and resume. Check on whether to hide the RDRAND
935 * instruction support via CPUID.
936 */
937 clear_rdrand_cpuid_bit(c);
938 }
939
init_amd_bd(struct cpuinfo_x86 * c)940 static void init_amd_bd(struct cpuinfo_x86 *c)
941 {
942 u64 value;
943
944 /*
945 * The way access filter has a performance penalty on some workloads.
946 * Disable it on the affected CPUs.
947 */
948 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
949 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) {
950 value |= 0x1E;
951 wrmsrl_safe(MSR_F15H_IC_CFG, value);
952 }
953 }
954
955 /*
956 * Some BIOS implementations do not restore proper RDRAND support
957 * across suspend and resume. Check on whether to hide the RDRAND
958 * instruction support via CPUID.
959 */
960 clear_rdrand_cpuid_bit(c);
961 }
962
init_spectral_chicken(struct cpuinfo_x86 * c)963 void init_spectral_chicken(struct cpuinfo_x86 *c)
964 {
965 #ifdef CONFIG_CPU_UNRET_ENTRY
966 u64 value;
967
968 /*
969 * On Zen2 we offer this chicken (bit) on the altar of Speculation.
970 *
971 * This suppresses speculation from the middle of a basic block, i.e. it
972 * suppresses non-branch predictions.
973 *
974 * We use STIBP as a heuristic to filter out Zen2 from the rest of F17H
975 */
976 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && cpu_has(c, X86_FEATURE_AMD_STIBP)) {
977 if (!rdmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, &value)) {
978 value |= MSR_ZEN2_SPECTRAL_CHICKEN_BIT;
979 wrmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, value);
980 }
981 }
982 #endif
983 /*
984 * Work around Erratum 1386. The XSAVES instruction malfunctions in
985 * certain circumstances on Zen1/2 uarch, and not all parts have had
986 * updated microcode at the time of writing (March 2023).
987 *
988 * Affected parts all have no supervisor XSAVE states, meaning that
989 * the XSAVEC instruction (which works fine) is equivalent.
990 */
991 clear_cpu_cap(c, X86_FEATURE_XSAVES);
992 }
993
init_amd_zn(struct cpuinfo_x86 * c)994 static void init_amd_zn(struct cpuinfo_x86 *c)
995 {
996 set_cpu_cap(c, X86_FEATURE_ZEN);
997
998 #ifdef CONFIG_NUMA
999 node_reclaim_distance = 32;
1000 #endif
1001
1002 /* Fix up CPUID bits, but only if not virtualised. */
1003 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) {
1004
1005 /* Erratum 1076: CPB feature bit not being set in CPUID. */
1006 if (!cpu_has(c, X86_FEATURE_CPB))
1007 set_cpu_cap(c, X86_FEATURE_CPB);
1008
1009 /*
1010 * Zen3 (Fam19 model < 0x10) parts are not susceptible to
1011 * Branch Type Confusion, but predate the allocation of the
1012 * BTC_NO bit.
1013 */
1014 if (c->x86 == 0x19 && !cpu_has(c, X86_FEATURE_BTC_NO))
1015 set_cpu_cap(c, X86_FEATURE_BTC_NO);
1016 }
1017 }
1018
cpu_has_zenbleed_microcode(void)1019 static bool cpu_has_zenbleed_microcode(void)
1020 {
1021 u32 good_rev = 0;
1022
1023 switch (boot_cpu_data.x86_model) {
1024 case 0x30 ... 0x3f: good_rev = 0x0830107a; break;
1025 case 0x60 ... 0x67: good_rev = 0x0860010b; break;
1026 case 0x68 ... 0x6f: good_rev = 0x08608105; break;
1027 case 0x70 ... 0x7f: good_rev = 0x08701032; break;
1028 case 0xa0 ... 0xaf: good_rev = 0x08a00008; break;
1029
1030 default:
1031 return false;
1032 break;
1033 }
1034
1035 if (boot_cpu_data.microcode < good_rev)
1036 return false;
1037
1038 return true;
1039 }
1040
zenbleed_check(struct cpuinfo_x86 * c)1041 static void zenbleed_check(struct cpuinfo_x86 *c)
1042 {
1043 if (!cpu_has_amd_erratum(c, amd_zenbleed))
1044 return;
1045
1046 if (cpu_has(c, X86_FEATURE_HYPERVISOR))
1047 return;
1048
1049 if (!cpu_has(c, X86_FEATURE_AVX))
1050 return;
1051
1052 if (!cpu_has_zenbleed_microcode()) {
1053 pr_notice_once("Zenbleed: please update your microcode for the most optimal fix\n");
1054 msr_set_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
1055 } else {
1056 msr_clear_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
1057 }
1058 }
1059
init_amd(struct cpuinfo_x86 * c)1060 static void init_amd(struct cpuinfo_x86 *c)
1061 {
1062 early_init_amd(c);
1063
1064 /*
1065 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
1066 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
1067 */
1068 clear_cpu_cap(c, 0*32+31);
1069
1070 if (c->x86 >= 0x10)
1071 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
1072
1073 /* get apicid instead of initial apic id from cpuid */
1074 c->apicid = hard_smp_processor_id();
1075
1076 /* K6s reports MCEs but don't actually have all the MSRs */
1077 if (c->x86 < 6)
1078 clear_cpu_cap(c, X86_FEATURE_MCE);
1079
1080 switch (c->x86) {
1081 case 4: init_amd_k5(c); break;
1082 case 5: init_amd_k6(c); break;
1083 case 6: init_amd_k7(c); break;
1084 case 0xf: init_amd_k8(c); break;
1085 case 0x10: init_amd_gh(c); break;
1086 case 0x12: init_amd_ln(c); break;
1087 case 0x15: init_amd_bd(c); break;
1088 case 0x16: init_amd_jg(c); break;
1089 case 0x17: init_spectral_chicken(c);
1090 fallthrough;
1091 case 0x19: init_amd_zn(c); break;
1092 }
1093
1094 /*
1095 * Enable workaround for FXSAVE leak on CPUs
1096 * without a XSaveErPtr feature
1097 */
1098 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR)))
1099 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);
1100
1101 cpu_detect_cache_sizes(c);
1102
1103 amd_detect_cmp(c);
1104 amd_get_topology(c);
1105 srat_detect_node(c);
1106 amd_detect_ppin(c);
1107
1108 init_amd_cacheinfo(c);
1109
1110 if (cpu_has(c, X86_FEATURE_XMM2)) {
1111 /*
1112 * Use LFENCE for execution serialization. On families which
1113 * don't have that MSR, LFENCE is already serializing.
1114 * msr_set_bit() uses the safe accessors, too, even if the MSR
1115 * is not present.
1116 */
1117 msr_set_bit(MSR_AMD64_DE_CFG,
1118 MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT);
1119
1120 /* A serializing LFENCE stops RDTSC speculation */
1121 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
1122 }
1123
1124 /*
1125 * Family 0x12 and above processors have APIC timer
1126 * running in deep C states.
1127 */
1128 if (c->x86 > 0x11)
1129 set_cpu_cap(c, X86_FEATURE_ARAT);
1130
1131 /* 3DNow or LM implies PREFETCHW */
1132 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH))
1133 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM))
1134 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH);
1135
1136 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */
1137 if (!cpu_has(c, X86_FEATURE_XENPV))
1138 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
1139
1140 /*
1141 * Turn on the Instructions Retired free counter on machines not
1142 * susceptible to erratum #1054 "Instructions Retired Performance
1143 * Counter May Be Inaccurate".
1144 */
1145 if (cpu_has(c, X86_FEATURE_IRPERF) &&
1146 !cpu_has_amd_erratum(c, amd_erratum_1054))
1147 msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT);
1148
1149 check_null_seg_clears_base(c);
1150
1151 zenbleed_check(c);
1152
1153 if (cpu_has_amd_erratum(c, amd_div0)) {
1154 pr_notice_once("AMD Zen1 DIV0 bug detected. Disable SMT for full protection.\n");
1155 setup_force_cpu_bug(X86_BUG_DIV0);
1156 }
1157
1158 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) &&
1159 cpu_has_amd_erratum(c, amd_erratum_1485))
1160 msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT);
1161 }
1162
1163 #ifdef CONFIG_X86_32
amd_size_cache(struct cpuinfo_x86 * c,unsigned int size)1164 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
1165 {
1166 /* AMD errata T13 (order #21922) */
1167 if (c->x86 == 6) {
1168 /* Duron Rev A0 */
1169 if (c->x86_model == 3 && c->x86_stepping == 0)
1170 size = 64;
1171 /* Tbird rev A1/A2 */
1172 if (c->x86_model == 4 &&
1173 (c->x86_stepping == 0 || c->x86_stepping == 1))
1174 size = 256;
1175 }
1176 return size;
1177 }
1178 #endif
1179
cpu_detect_tlb_amd(struct cpuinfo_x86 * c)1180 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
1181 {
1182 u32 ebx, eax, ecx, edx;
1183 u16 mask = 0xfff;
1184
1185 if (c->x86 < 0xf)
1186 return;
1187
1188 if (c->extended_cpuid_level < 0x80000006)
1189 return;
1190
1191 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
1192
1193 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
1194 tlb_lli_4k[ENTRIES] = ebx & mask;
1195
1196 /*
1197 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
1198 * characteristics from the CPUID function 0x80000005 instead.
1199 */
1200 if (c->x86 == 0xf) {
1201 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
1202 mask = 0xff;
1203 }
1204
1205 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
1206 if (!((eax >> 16) & mask))
1207 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
1208 else
1209 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
1210
1211 /* a 4M entry uses two 2M entries */
1212 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
1213
1214 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
1215 if (!(eax & mask)) {
1216 /* Erratum 658 */
1217 if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
1218 tlb_lli_2m[ENTRIES] = 1024;
1219 } else {
1220 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
1221 tlb_lli_2m[ENTRIES] = eax & 0xff;
1222 }
1223 } else
1224 tlb_lli_2m[ENTRIES] = eax & mask;
1225
1226 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
1227 }
1228
1229 static const struct cpu_dev amd_cpu_dev = {
1230 .c_vendor = "AMD",
1231 .c_ident = { "AuthenticAMD" },
1232 #ifdef CONFIG_X86_32
1233 .legacy_models = {
1234 { .family = 4, .model_names =
1235 {
1236 [3] = "486 DX/2",
1237 [7] = "486 DX/2-WB",
1238 [8] = "486 DX/4",
1239 [9] = "486 DX/4-WB",
1240 [14] = "Am5x86-WT",
1241 [15] = "Am5x86-WB"
1242 }
1243 },
1244 },
1245 .legacy_cache_size = amd_size_cache,
1246 #endif
1247 .c_early_init = early_init_amd,
1248 .c_detect_tlb = cpu_detect_tlb_amd,
1249 .c_bsp_init = bsp_init_amd,
1250 .c_init = init_amd,
1251 .c_x86_vendor = X86_VENDOR_AMD,
1252 };
1253
1254 cpu_dev_register(amd_cpu_dev);
1255
set_dr_addr_mask(unsigned long mask,int dr)1256 void set_dr_addr_mask(unsigned long mask, int dr)
1257 {
1258 if (!boot_cpu_has(X86_FEATURE_BPEXT))
1259 return;
1260
1261 switch (dr) {
1262 case 0:
1263 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0);
1264 break;
1265 case 1:
1266 case 2:
1267 case 3:
1268 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0);
1269 break;
1270 default:
1271 break;
1272 }
1273 }
1274
amd_get_highest_perf(void)1275 u32 amd_get_highest_perf(void)
1276 {
1277 struct cpuinfo_x86 *c = &boot_cpu_data;
1278
1279 if (c->x86 == 0x17 && ((c->x86_model >= 0x30 && c->x86_model < 0x40) ||
1280 (c->x86_model >= 0x70 && c->x86_model < 0x80)))
1281 return 166;
1282
1283 if (c->x86 == 0x19 && ((c->x86_model >= 0x20 && c->x86_model < 0x30) ||
1284 (c->x86_model >= 0x40 && c->x86_model < 0x70)))
1285 return 166;
1286
1287 return 255;
1288 }
1289 EXPORT_SYMBOL_GPL(amd_get_highest_perf);
1290
cpu_has_ibpb_brtype_microcode(void)1291 bool cpu_has_ibpb_brtype_microcode(void)
1292 {
1293 switch (boot_cpu_data.x86) {
1294 /* Zen1/2 IBPB flushes branch type predictions too. */
1295 case 0x17:
1296 return boot_cpu_has(X86_FEATURE_AMD_IBPB);
1297 case 0x19:
1298 /* Poke the MSR bit on Zen3/4 to check its presence. */
1299 if (!wrmsrl_safe(MSR_IA32_PRED_CMD, PRED_CMD_SBPB)) {
1300 setup_force_cpu_cap(X86_FEATURE_SBPB);
1301 return true;
1302 } else {
1303 return false;
1304 }
1305 default:
1306 return false;
1307 }
1308 }
1309
zenbleed_check_cpu(void * unused)1310 static void zenbleed_check_cpu(void *unused)
1311 {
1312 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
1313
1314 zenbleed_check(c);
1315 }
1316
amd_check_microcode(void)1317 void amd_check_microcode(void)
1318 {
1319 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
1320 return;
1321
1322 on_each_cpu(zenbleed_check_cpu, NULL, 1);
1323 }
1324
1325 /*
1326 * Issue a DIV 0/1 insn to clear any division data from previous DIV
1327 * operations.
1328 */
amd_clear_divider(void)1329 void noinstr amd_clear_divider(void)
1330 {
1331 asm volatile(ALTERNATIVE("", "div %2\n\t", X86_BUG_DIV0)
1332 :: "a" (0), "d" (0), "r" (1));
1333 }
1334 EXPORT_SYMBOL_GPL(amd_clear_divider);
1335