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Searched refs:BIT_1 (Results 1 – 25 of 38) sorted by relevance

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/drivers/scsi/
Dqla1280.h18 #define BIT_1 0x2 macro
121 #define ISP_CFG0_1020A BIT_1 /* ISP1020A */
135 #define ISP_EN_INT BIT_1 /* ISP enable interrupts. */
142 #define PCI_INT BIT_1 /* PCI interrupt */
147 #define NV_SELECT BIT_1
159 #define CDMA_CONF_BENAB BIT_1 /* Bus burst enable */
176 #define DDMA_CONF_BENAB BIT_1 /* Bus burst enable */
568 #define RF_FULL BIT_1 /* Full */
966 #define OF_ENABLE_TAG BIT_1 /* Tagged queue action enable */
Dqla1280.c1123 mr = BIT_3 | BIT_2 | BIT_1 | BIT_0; in qla1280_set_target_parameters()
1689 err = qla1280_mailbox_command(ha, BIT_0 | BIT_1 | BIT_2, mb); in qla1280_load_firmware_pio()
1703 #define CMD_ARGS (BIT_7 | BIT_6 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)
1707 #define CMD_ARGS (BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)
1831 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb); in qla1280_start_firmware()
1841 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]); in qla1280_start_firmware()
1908 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
1922 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
2142 status = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]); in qla1280_config_bus()
2215 BIT_7 | BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla1280_nvram_config()
[all …]
/drivers/scsi/qla2xxx/
Dqla_fw.h30 #define PDO_FORCE_ADISC BIT_1
45 #define PDF_HARD_ADDR BIT_1
457 #define BD_READ_DATA BIT_1
498 #define CF_READ_DATA BIT_1
540 #define TMF_READ_DATA BIT_1
974 #define TCF_TARGET_RESET BIT_1
1001 #define AOF_NO_RRQ BIT_1 /* Do not send RRQ. */
1195 #define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */
1265 #define GPDX_DATA_INOUT (BIT_1|BIT_0)
1273 #define GPEX_ENABLE (BIT_1|BIT_0)
[all …]
Dqla_edif.h20 #define EDIF_SA_CTL_FLG_DEL BIT_1
79 #define SA_FLAG_TX BIT_1 // 1=tx, 0=rx
Dqla_def.h104 #define BIT_1 0x2 macro
226 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1
246 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1
501 #define SRB_LOGIN_COND_PLOGI BIT_1
551 #define SRB_FXDISC_RESP_DMA_VALID BIT_1
784 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
802 #define NVR_SELECT BIT_1
1059 #define MBX_DMA_OUT BIT_1
1072 #define MBX_DMA_OUT BIT_1
1194 #define FO1_AE_ALL_LIP_RESET BIT_1
[all …]
Dqla_target.h225 #define ATIO_EXEC_READ BIT_1
422 #define EF_NEW_SA BIT_1
483 #define CTIO7_FLAGS_DATA_IN BIT_1 /* data to initiator */
844 TRC_DO_WORK = BIT_1,
972 #define QLA24XX_MGMT_ABORT_IO_ATTR_VALID BIT_1
Dqla_nvme.h60 #define CF_READ_DATA BIT_1
Dqla_tmpl.h61 #define CAPTURE_FLAG_PHYS_VIRT BIT_1
Dqla_init.c4473 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
4477 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
4487 ((rx_sens & (BIT_1 | BIT_0)) << 2) | in qla2x00_update_fw_options()
4488 (tx_sens & (BIT_1 | BIT_0)); in qla2x00_update_fw_options()
4493 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0); in qla2x00_update_fw_options()
4495 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
4505 ((rx_sens & (BIT_1 | BIT_0)) << 2) | in qla2x00_update_fw_options()
4506 (tx_sens & (BIT_1 | BIT_0)); in qla2x00_update_fw_options()
4817 mid_init_cb->options = cpu_to_le16(BIT_1); in qla2x00_init_rings()
5248 nv->firmware_options[0] = BIT_2 | BIT_1; in qla2x00_nvram_config()
[all …]
Dqla_mbx.c788 ha->max_supported_speed = mcp->mb[2] & (BIT_0|BIT_1); in qla2x00_execute_fw()
795 (BIT_0 | BIT_1 | BIT_2); in qla2x00_execute_fw()
1890 mcp->mb[1] |= BIT_1; in qla2x00_init_firmware()
2393 mcp->mb[1] = BIT_1; in qla2x00_lip_reset()
2526 if (opt & BIT_1) in qla24xx_login_fabric()
2586 mb[1] |= BIT_1; in qla24xx_login_fabric()
2595 mb[10] |= BIT_1; /* Class 3. */ in qla24xx_login_fabric()
4332 rval = BIT_1; in qla2x00_send_change_request()
4335 rval = BIT_1; in qla2x00_send_change_request()
5745 mcp->mb[2] = BIT_1; in qla24xx_set_fcp_prio()
[all …]
Dqla_inline.h387 RESOURCE_EXCH = BIT_1, /* exchange */
Dqla_mid.c894 options |= BIT_1; in qla25xx_create_rsp_que()
Dqla_gbl.h998 #define QLA2XX_SHT_LNK_DWN BIT_1
/drivers/net/ethernet/qlogic/qlcnic/
Dqlcnic_hw.h140 #define QLCNIC_GET_OWNER(val) ((val) & (BIT_0 | BIT_1))
Dqlcnic_hdr.h196 #define BIT_1 0x2 macro
493 #define TA_CTL_ENABLE BIT_1
Dqlcnic_ctx.c1352 arg2 |= (BIT_0 | BIT_1); in qlcnic_config_switch_port()
1364 arg2 &= ~(BIT_1 | BIT_2 | BIT_3); in qlcnic_config_switch_port()
1365 if (!(esw_cfg->offload_flags & BIT_1)) in qlcnic_config_switch_port()
Dqlcnic_83xx_hw.h531 #define QLC_REGISTER_DCB_AEN BIT_1
Dqlcnic.h913 #define QLCNIC_FW_CAPABILITY_TSO BIT_1
929 #define QLCNIC_83XX_FW_CAPAB_ENCAP_TX_OFFLOAD BIT_1
1315 #define QLCNIC_SWITCH_ENABLE BIT_1
Dqlcnic_hw.c815 #define QLCNIC_ENABLE_IPV6_LRO (BIT_1 | BIT_9)
1033 if (!(offload_flags & BIT_1)) in qlcnic_process_flags()
Dqlcnic_minidump.c24 #define QLCNIC_DUMP_RWCRB BIT_1
753 if (dma_sts & BIT_1) in qlcnic_start_pex_dma()
Dqlcnic_sriov_pf.c390 cmd.req.arg[1] = ((func & 0xf) << 2) | BIT_6 | BIT_1; in qlcnic_sriov_pf_cfg_eswitch()
703 cmd.req.arg[2] |= BIT_1 | BIT_3 | BIT_8; in qlcnic_sriov_set_vf_acl()
Dqlcnic_83xx_hw.c2023 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0); in qlcnic_83xx_config_hw_lro()
3539 cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16); in qlcnic_83xx_get_stats()
3570 #define QLCNIC_83XX_ADD_PORT1 BIT_1
/drivers/scsi/qla4xxx/
Dql4_def.h82 #define BIT_1 0x2 macro
Dql4_os.c3547 sess->erl |= BIT_1; in qla4xxx_copy_from_fwddb_param()
3560 conn->tcp_timer_scale |= BIT_1; in qla4xxx_copy_from_fwddb_param()
3678 SET_BITVAL(sess->erl & BIT_1, options, BIT_1); in qla4xxx_copy_to_fwddb_param()
3687 SET_BITVAL(conn->tcp_timer_scale & BIT_1, options, BIT_2); in qla4xxx_copy_to_fwddb_param()
3688 SET_BITVAL(conn->tcp_timer_scale & BIT_0, options, BIT_1); in qla4xxx_copy_to_fwddb_param()
3784 sess->erl |= BIT_1; in qla4xxx_copy_to_sess_conn_params()
3797 conn->tcp_timer_scale |= BIT_1; in qla4xxx_copy_to_sess_conn_params()
8910 if (PCI_FUNC(ha->pdev->devfn) & BIT_1) in qla4xxx_prevent_other_port_reinit()
Dql4_fw.h61 #define HSRX_RISC_IOCB_INT BIT_1 /* RISC to Host IOCB interrupt */

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