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Searched refs:GRBM_SOFT_RESET (Results 1 – 18 of 18) sorted by relevance

/drivers/gpu/drm/radeon/
Dni.c1652 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | in cayman_cp_resume()
1658 RREG32(GRBM_SOFT_RESET); in cayman_cp_resume()
1660 WREG32(GRBM_SOFT_RESET, 0); in cayman_cp_resume()
1661 RREG32(GRBM_SOFT_RESET); in cayman_cp_resume()
1907 tmp = RREG32(GRBM_SOFT_RESET); in cayman_gpu_soft_reset()
1910 WREG32(GRBM_SOFT_RESET, tmp); in cayman_gpu_soft_reset()
1911 tmp = RREG32(GRBM_SOFT_RESET); in cayman_gpu_soft_reset()
1916 WREG32(GRBM_SOFT_RESET, tmp); in cayman_gpu_soft_reset()
1917 tmp = RREG32(GRBM_SOFT_RESET); in cayman_gpu_soft_reset()
Devergreen.c3072 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | in evergreen_cp_resume()
3078 RREG32(GRBM_SOFT_RESET); in evergreen_cp_resume()
3080 WREG32(GRBM_SOFT_RESET, 0); in evergreen_cp_resume()
3081 RREG32(GRBM_SOFT_RESET); in evergreen_cp_resume()
3974 tmp = RREG32(GRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
3977 WREG32(GRBM_SOFT_RESET, tmp); in evergreen_gpu_soft_reset()
3978 tmp = RREG32(GRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
3983 WREG32(GRBM_SOFT_RESET, tmp); in evergreen_gpu_soft_reset()
3984 tmp = RREG32(GRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
Drv770.c1115 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); in rv770_cp_load_microcode()
1116 RREG32(GRBM_SOFT_RESET); in rv770_cp_load_microcode()
1118 WREG32(GRBM_SOFT_RESET, 0); in rv770_cp_load_microcode()
Dsi.c3950 tmp = RREG32(GRBM_SOFT_RESET); in si_gpu_soft_reset()
3953 WREG32(GRBM_SOFT_RESET, tmp); in si_gpu_soft_reset()
3954 tmp = RREG32(GRBM_SOFT_RESET); in si_gpu_soft_reset()
3959 WREG32(GRBM_SOFT_RESET, tmp); in si_gpu_soft_reset()
3960 tmp = RREG32(GRBM_SOFT_RESET); in si_gpu_soft_reset()
5808 u32 tmp = RREG32(GRBM_SOFT_RESET); in si_rlc_reset()
5811 WREG32(GRBM_SOFT_RESET, tmp); in si_rlc_reset()
5814 WREG32(GRBM_SOFT_RESET, tmp); in si_rlc_reset()
Dr600.c2661 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); in r600_cp_load_microcode()
2662 RREG32(GRBM_SOFT_RESET); in r600_cp_load_microcode()
2664 WREG32(GRBM_SOFT_RESET, 0); in r600_cp_load_microcode()
2724 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); in r600_cp_resume()
2725 RREG32(GRBM_SOFT_RESET); in r600_cp_resume()
2727 WREG32(GRBM_SOFT_RESET, 0); in r600_cp_resume()
Drv770d.h401 #define GRBM_SOFT_RESET 0x8020 macro
Dnid.h280 #define GRBM_SOFT_RESET 0x8020 macro
Dsid.h982 #define GRBM_SOFT_RESET 0x8020 macro
Dcikd.h1075 #define GRBM_SOFT_RESET 0x8020 macro
Dcik.c5009 tmp = RREG32(GRBM_SOFT_RESET); in cik_gpu_soft_reset()
5012 WREG32(GRBM_SOFT_RESET, tmp); in cik_gpu_soft_reset()
5013 tmp = RREG32(GRBM_SOFT_RESET); in cik_gpu_soft_reset()
5018 WREG32(GRBM_SOFT_RESET, tmp); in cik_gpu_soft_reset()
5019 tmp = RREG32(GRBM_SOFT_RESET); in cik_gpu_soft_reset()
Devergreend.h828 #define GRBM_SOFT_RESET 0x8020 macro
Dr600d.h295 #define GRBM_SOFT_RESET 0x8020 macro
/drivers/gpu/drm/amd/amdgpu/
Dgfx_v8_0.c4102 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v8_0_rlc_reset()
4105 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v8_0_rlc_reset()
4986 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); in gfx_v8_0_check_soft_reset()
4988 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); in gfx_v8_0_check_soft_reset()
4997 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v8_0_check_soft_reset()
5002 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, in gfx_v8_0_check_soft_reset()
5004 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, in gfx_v8_0_check_soft_reset()
5006 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, in gfx_v8_0_check_soft_reset()
5046 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) || in gfx_v8_0_pre_soft_reset()
5047 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX)) in gfx_v8_0_pre_soft_reset()
[all …]
Dgfx_v9_0.c3082 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v9_0_rlc_reset()
3084 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v9_0_rlc_reset()
4126 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); in gfx_v9_0_soft_reset()
4128 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); in gfx_v9_0_soft_reset()
4133 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); in gfx_v9_0_soft_reset()
4140 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v9_0_soft_reset()
Dsid.h980 #define GRBM_SOFT_RESET 0x2008 macro
Dgfx_v10_0.c5355 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v10_0_rlc_reset()
5357 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v10_0_rlc_reset()
7660 GRBM_SOFT_RESET, SOFT_RESET_CP, in gfx_v10_0_soft_reset()
7663 GRBM_SOFT_RESET, SOFT_RESET_GFX, in gfx_v10_0_soft_reset()
7669 GRBM_SOFT_RESET, SOFT_RESET_CP, in gfx_v10_0_soft_reset()
7684 GRBM_SOFT_RESET, in gfx_v10_0_soft_reset()
7691 GRBM_SOFT_RESET, in gfx_v10_0_soft_reset()
Dsdma_v5_2.c818 GRBM_SOFT_RESET, SOFT_RESET_SDMA0, in sdma_v5_2_soft_reset()
Dgfx_v6_0.c2497 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v6_0_rlc_reset()
2499 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v6_0_rlc_reset()