1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28
29 #include "amdgpu.h"
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_trace.h"
32
33 #include "gc/gc_10_3_0_offset.h"
34 #include "gc/gc_10_3_0_sh_mask.h"
35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h"
38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h"
39
40 #include "soc15_common.h"
41 #include "soc15.h"
42 #include "navi10_sdma_pkt_open.h"
43 #include "nbio_v2_3.h"
44 #include "sdma_common.h"
45 #include "sdma_v5_2.h"
46
47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
48 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");
49 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin");
50 MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin");
51
52 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin");
53 MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin");
54
55 #define SDMA1_REG_OFFSET 0x600
56 #define SDMA3_REG_OFFSET 0x400
57 #define SDMA0_HYP_DEC_REG_START 0x5880
58 #define SDMA0_HYP_DEC_REG_END 0x5893
59 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
60
61 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);
62 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);
63 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev);
64 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev);
65
sdma_v5_2_get_reg_offset(struct amdgpu_device * adev,u32 instance,u32 internal_offset)66 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
67 {
68 u32 base;
69
70 if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
71 internal_offset <= SDMA0_HYP_DEC_REG_END) {
72 base = adev->reg_offset[GC_HWIP][0][1];
73 if (instance != 0)
74 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
75 } else {
76 if (instance < 2) {
77 base = adev->reg_offset[GC_HWIP][0][0];
78 if (instance == 1)
79 internal_offset += SDMA1_REG_OFFSET;
80 } else {
81 base = adev->reg_offset[GC_HWIP][0][2];
82 if (instance == 3)
83 internal_offset += SDMA3_REG_OFFSET;
84 }
85 }
86
87 return base + internal_offset;
88 }
89
sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance * sdma_inst)90 static int sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
91 {
92 int err = 0;
93 const struct sdma_firmware_header_v1_0 *hdr;
94
95 err = amdgpu_ucode_validate(sdma_inst->fw);
96 if (err)
97 return err;
98
99 hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
100 sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
101 sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
102
103 if (sdma_inst->feature_version >= 20)
104 sdma_inst->burst_nop = true;
105
106 return 0;
107 }
108
sdma_v5_2_destroy_inst_ctx(struct amdgpu_device * adev)109 static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev)
110 {
111 release_firmware(adev->sdma.instance[0].fw);
112
113 memset((void *)adev->sdma.instance, 0,
114 sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
115 }
116
117 /**
118 * sdma_v5_2_init_microcode - load ucode images from disk
119 *
120 * @adev: amdgpu_device pointer
121 *
122 * Use the firmware interface to load the ucode images into
123 * the driver (not loaded into hw).
124 * Returns 0 on success, error on failure.
125 */
126
127 // emulation only, won't work on real chip
128 // navi10 real chip need to use PSP to load firmware
sdma_v5_2_init_microcode(struct amdgpu_device * adev)129 static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
130 {
131 const char *chip_name;
132 char fw_name[40];
133 int err = 0, i;
134 struct amdgpu_firmware_info *info = NULL;
135 const struct common_firmware_header *header = NULL;
136
137 DRM_DEBUG("\n");
138
139 switch (adev->asic_type) {
140 case CHIP_SIENNA_CICHLID:
141 chip_name = "sienna_cichlid";
142 break;
143 case CHIP_NAVY_FLOUNDER:
144 chip_name = "navy_flounder";
145 break;
146 case CHIP_VANGOGH:
147 chip_name = "vangogh";
148 break;
149 case CHIP_DIMGREY_CAVEFISH:
150 chip_name = "dimgrey_cavefish";
151 break;
152 case CHIP_BEIGE_GOBY:
153 chip_name = "beige_goby";
154 break;
155 case CHIP_YELLOW_CARP:
156 chip_name = "yellow_carp";
157 break;
158 default:
159 BUG();
160 }
161
162 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
163
164 err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
165 if (err)
166 goto out;
167
168 err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]);
169 if (err)
170 goto out;
171
172 for (i = 1; i < adev->sdma.num_instances; i++)
173 memcpy((void *)&adev->sdma.instance[i],
174 (void *)&adev->sdma.instance[0],
175 sizeof(struct amdgpu_sdma_instance));
176
177 if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_SIENNA_CICHLID))
178 return 0;
179
180 DRM_DEBUG("psp_load == '%s'\n",
181 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
182
183 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
184 for (i = 0; i < adev->sdma.num_instances; i++) {
185 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
186 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
187 info->fw = adev->sdma.instance[i].fw;
188 header = (const struct common_firmware_header *)info->fw->data;
189 adev->firmware.fw_size +=
190 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
191 }
192 }
193
194 out:
195 if (err) {
196 DRM_ERROR("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name);
197 sdma_v5_2_destroy_inst_ctx(adev);
198 }
199 return err;
200 }
201
sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring * ring)202 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring)
203 {
204 unsigned ret;
205
206 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
207 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
208 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
209 amdgpu_ring_write(ring, 1);
210 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
211 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
212
213 return ret;
214 }
215
sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring * ring,unsigned offset)216 static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring,
217 unsigned offset)
218 {
219 unsigned cur;
220
221 BUG_ON(offset > ring->buf_mask);
222 BUG_ON(ring->ring[offset] != 0x55aa55aa);
223
224 cur = (ring->wptr - 1) & ring->buf_mask;
225 if (cur > offset)
226 ring->ring[offset] = cur - offset;
227 else
228 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
229 }
230
231 /**
232 * sdma_v5_2_ring_get_rptr - get the current read pointer
233 *
234 * @ring: amdgpu ring pointer
235 *
236 * Get the current rptr from the hardware (NAVI10+).
237 */
sdma_v5_2_ring_get_rptr(struct amdgpu_ring * ring)238 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring)
239 {
240 u64 *rptr;
241
242 /* XXX check if swapping is necessary on BE */
243 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
244
245 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
246 return ((*rptr) >> 2);
247 }
248
249 /**
250 * sdma_v5_2_ring_get_wptr - get the current write pointer
251 *
252 * @ring: amdgpu ring pointer
253 *
254 * Get the current wptr from the hardware (NAVI10+).
255 */
sdma_v5_2_ring_get_wptr(struct amdgpu_ring * ring)256 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring)
257 {
258 struct amdgpu_device *adev = ring->adev;
259 u64 wptr;
260
261 if (ring->use_doorbell) {
262 /* XXX check if swapping is necessary on BE */
263 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
264 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
265 } else {
266 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
267 wptr = wptr << 32;
268 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
269 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
270 }
271
272 return wptr >> 2;
273 }
274
275 /**
276 * sdma_v5_2_ring_set_wptr - commit the write pointer
277 *
278 * @ring: amdgpu ring pointer
279 *
280 * Write the wptr back to the hardware (NAVI10+).
281 */
sdma_v5_2_ring_set_wptr(struct amdgpu_ring * ring)282 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring)
283 {
284 struct amdgpu_device *adev = ring->adev;
285
286 DRM_DEBUG("Setting write pointer\n");
287 if (ring->use_doorbell) {
288 DRM_DEBUG("Using doorbell -- "
289 "wptr_offs == 0x%08x "
290 "lower_32_bits(ring->wptr << 2) == 0x%08x "
291 "upper_32_bits(ring->wptr << 2) == 0x%08x\n",
292 ring->wptr_offs,
293 lower_32_bits(ring->wptr << 2),
294 upper_32_bits(ring->wptr << 2));
295 /* XXX check if swapping is necessary on BE */
296 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
297 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
298 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
299 ring->doorbell_index, ring->wptr << 2);
300 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
301 } else {
302 DRM_DEBUG("Not using doorbell -- "
303 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
304 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
305 ring->me,
306 lower_32_bits(ring->wptr << 2),
307 ring->me,
308 upper_32_bits(ring->wptr << 2));
309 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
310 lower_32_bits(ring->wptr << 2));
311 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
312 upper_32_bits(ring->wptr << 2));
313 }
314 }
315
sdma_v5_2_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)316 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
317 {
318 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
319 int i;
320
321 for (i = 0; i < count; i++)
322 if (sdma && sdma->burst_nop && (i == 0))
323 amdgpu_ring_write(ring, ring->funcs->nop |
324 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
325 else
326 amdgpu_ring_write(ring, ring->funcs->nop);
327 }
328
329 /**
330 * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine
331 *
332 * @ring: amdgpu ring pointer
333 * @job: job to retrieve vmid from
334 * @ib: IB object to schedule
335 * @flags: unused
336 *
337 * Schedule an IB in the DMA ring.
338 */
sdma_v5_2_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)339 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,
340 struct amdgpu_job *job,
341 struct amdgpu_ib *ib,
342 uint32_t flags)
343 {
344 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
345 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
346
347 /* An IB packet must end on a 8 DW boundary--the next dword
348 * must be on a 8-dword boundary. Our IB packet below is 6
349 * dwords long, thus add x number of NOPs, such that, in
350 * modular arithmetic,
351 * wptr + 6 + x = 8k, k >= 0, which in C is,
352 * (wptr + 6 + x) % 8 = 0.
353 * The expression below, is a solution of x.
354 */
355 sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
356
357 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
358 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
359 /* base must be 32 byte aligned */
360 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
361 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
362 amdgpu_ring_write(ring, ib->length_dw);
363 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
364 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
365 }
366
367 /**
368 * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse
369 *
370 * @ring: amdgpu ring pointer
371 * @job: job to retrieve vmid from
372 * @ib: IB object to schedule
373 *
374 * flush the IB by graphics cache rinse.
375 */
sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring * ring)376 static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring)
377 {
378 uint32_t gcr_cntl =
379 SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
380 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
381 SDMA_GCR_GLI_INV(1);
382
383 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
384 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
385 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
386 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
387 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
388 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
389 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
390 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
391 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
392 }
393
394 /**
395 * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
396 *
397 * @ring: amdgpu ring pointer
398 *
399 * Emit an hdp flush packet on the requested DMA ring.
400 */
sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring * ring)401 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
402 {
403 struct amdgpu_device *adev = ring->adev;
404 u32 ref_and_mask = 0;
405 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
406
407 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
408
409 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
410 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
411 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
412 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
413 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
414 amdgpu_ring_write(ring, ref_and_mask); /* reference */
415 amdgpu_ring_write(ring, ref_and_mask); /* mask */
416 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
417 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
418 }
419
420 /**
421 * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring
422 *
423 * @ring: amdgpu ring pointer
424 * @addr: address
425 * @seq: sequence number
426 * @flags: fence related flags
427 *
428 * Add a DMA fence packet to the ring to write
429 * the fence seq number and DMA trap packet to generate
430 * an interrupt if needed.
431 */
sdma_v5_2_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)432 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
433 unsigned flags)
434 {
435 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
436 /* write the fence */
437 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
438 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
439 /* zero in first two bits */
440 BUG_ON(addr & 0x3);
441 amdgpu_ring_write(ring, lower_32_bits(addr));
442 amdgpu_ring_write(ring, upper_32_bits(addr));
443 amdgpu_ring_write(ring, lower_32_bits(seq));
444
445 /* optionally write high bits as well */
446 if (write64bit) {
447 addr += 4;
448 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
449 SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
450 /* zero in first two bits */
451 BUG_ON(addr & 0x3);
452 amdgpu_ring_write(ring, lower_32_bits(addr));
453 amdgpu_ring_write(ring, upper_32_bits(addr));
454 amdgpu_ring_write(ring, upper_32_bits(seq));
455 }
456
457 if (flags & AMDGPU_FENCE_FLAG_INT) {
458 /* generate an interrupt */
459 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
460 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
461 }
462 }
463
464
465 /**
466 * sdma_v5_2_gfx_stop - stop the gfx async dma engines
467 *
468 * @adev: amdgpu_device pointer
469 *
470 * Stop the gfx async dma ring buffers.
471 */
sdma_v5_2_gfx_stop(struct amdgpu_device * adev)472 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
473 {
474 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
475 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
476 struct amdgpu_ring *sdma2 = &adev->sdma.instance[2].ring;
477 struct amdgpu_ring *sdma3 = &adev->sdma.instance[3].ring;
478 u32 rb_cntl, ib_cntl;
479 int i;
480
481 if ((adev->mman.buffer_funcs_ring == sdma0) ||
482 (adev->mman.buffer_funcs_ring == sdma1) ||
483 (adev->mman.buffer_funcs_ring == sdma2) ||
484 (adev->mman.buffer_funcs_ring == sdma3))
485 amdgpu_ttm_set_buffer_funcs_status(adev, false);
486
487 for (i = 0; i < adev->sdma.num_instances; i++) {
488 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
489 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
490 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
491 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
492 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
493 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
494 }
495 }
496
497 /**
498 * sdma_v5_2_rlc_stop - stop the compute async dma engines
499 *
500 * @adev: amdgpu_device pointer
501 *
502 * Stop the compute async dma queues.
503 */
sdma_v5_2_rlc_stop(struct amdgpu_device * adev)504 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
505 {
506 /* XXX todo */
507 }
508
509 /**
510 * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch
511 *
512 * @adev: amdgpu_device pointer
513 * @enable: enable/disable the DMA MEs context switch.
514 *
515 * Halt or unhalt the async dma engines context switch.
516 */
sdma_v5_2_ctx_switch_enable(struct amdgpu_device * adev,bool enable)517 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
518 {
519 u32 f32_cntl, phase_quantum = 0;
520 int i;
521
522 if (amdgpu_sdma_phase_quantum) {
523 unsigned value = amdgpu_sdma_phase_quantum;
524 unsigned unit = 0;
525
526 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
527 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
528 value = (value + 1) >> 1;
529 unit++;
530 }
531 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
532 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
533 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
534 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
535 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
536 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
537 WARN_ONCE(1,
538 "clamping sdma_phase_quantum to %uK clock cycles\n",
539 value << unit);
540 }
541 phase_quantum =
542 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
543 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
544 }
545
546 for (i = 0; i < adev->sdma.num_instances; i++) {
547 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
548 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
549 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
550 if (enable && amdgpu_sdma_phase_quantum) {
551 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
552 phase_quantum);
553 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
554 phase_quantum);
555 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
556 phase_quantum);
557 }
558 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
559 }
560
561 }
562
563 /**
564 * sdma_v5_2_enable - stop the async dma engines
565 *
566 * @adev: amdgpu_device pointer
567 * @enable: enable/disable the DMA MEs.
568 *
569 * Halt or unhalt the async dma engines.
570 */
sdma_v5_2_enable(struct amdgpu_device * adev,bool enable)571 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
572 {
573 u32 f32_cntl;
574 int i;
575
576 if (!enable) {
577 sdma_v5_2_gfx_stop(adev);
578 sdma_v5_2_rlc_stop(adev);
579 }
580
581 for (i = 0; i < adev->sdma.num_instances; i++) {
582 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
583 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
584 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
585 }
586 }
587
588 /**
589 * sdma_v5_2_gfx_resume - setup and start the async dma engines
590 *
591 * @adev: amdgpu_device pointer
592 *
593 * Set up the gfx DMA ring buffers and enable them.
594 * Returns 0 for success, error for failure.
595 */
sdma_v5_2_gfx_resume(struct amdgpu_device * adev)596 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
597 {
598 struct amdgpu_ring *ring;
599 u32 rb_cntl, ib_cntl;
600 u32 rb_bufsz;
601 u32 wb_offset;
602 u32 doorbell;
603 u32 doorbell_offset;
604 u32 temp;
605 u32 wptr_poll_cntl;
606 u64 wptr_gpu_addr;
607 int i, r;
608
609 for (i = 0; i < adev->sdma.num_instances; i++) {
610 ring = &adev->sdma.instance[i].ring;
611 wb_offset = (ring->rptr_offs * 4);
612
613 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
614
615 /* Set ring buffer size in dwords */
616 rb_bufsz = order_base_2(ring->ring_size / 4);
617 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
618 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
619 #ifdef __BIG_ENDIAN
620 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
621 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
622 RPTR_WRITEBACK_SWAP_ENABLE, 1);
623 #endif
624 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
625
626 /* Initialize the ring buffer's read and write pointers */
627 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
628 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
629 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
630 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
631
632 /* setup the wptr shadow polling */
633 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
634 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
635 lower_32_bits(wptr_gpu_addr));
636 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
637 upper_32_bits(wptr_gpu_addr));
638 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i,
639 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
640 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
641 SDMA0_GFX_RB_WPTR_POLL_CNTL,
642 F32_POLL_ENABLE, 1);
643 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
644 wptr_poll_cntl);
645
646 /* set the wb address whether it's enabled or not */
647 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
648 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
649 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
650 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
651
652 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
653
654 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
655 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
656
657 ring->wptr = 0;
658
659 /* before programing wptr to a less value, need set minor_ptr_update first */
660 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
661
662 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
663 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
664 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
665 }
666
667 doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
668 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
669
670 if (ring->use_doorbell) {
671 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
672 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
673 OFFSET, ring->doorbell_index);
674 } else {
675 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
676 }
677 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
678 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
679
680 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
681 ring->doorbell_index,
682 adev->doorbell_index.sdma_doorbell_range);
683
684 if (amdgpu_sriov_vf(adev))
685 sdma_v5_2_ring_set_wptr(ring);
686
687 /* set minor_ptr_update to 0 after wptr programed */
688 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
689
690 /* set utc l1 enable flag always to 1 */
691 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
692 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
693
694 /* enable MCBP */
695 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
696 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
697
698 /* Set up RESP_MODE to non-copy addresses */
699 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
700 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
701 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
702 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
703
704 /* program default cache read and write policy */
705 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
706 /* clean read policy and write policy bits */
707 temp &= 0xFF0FFF;
708 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
709 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
710 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
711 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
712
713 if (!amdgpu_sriov_vf(adev)) {
714 /* unhalt engine */
715 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
716 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
717 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
718 }
719
720 /* enable DMA RB */
721 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
722 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
723
724 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
725 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
726 #ifdef __BIG_ENDIAN
727 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
728 #endif
729 /* enable DMA IBs */
730 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
731
732 ring->sched.ready = true;
733
734 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
735 sdma_v5_2_ctx_switch_enable(adev, true);
736 sdma_v5_2_enable(adev, true);
737 }
738
739 r = amdgpu_ring_test_ring(ring);
740 if (r) {
741 ring->sched.ready = false;
742 return r;
743 }
744
745 if (adev->mman.buffer_funcs_ring == ring)
746 amdgpu_ttm_set_buffer_funcs_status(adev, true);
747 }
748
749 return 0;
750 }
751
752 /**
753 * sdma_v5_2_rlc_resume - setup and start the async dma engines
754 *
755 * @adev: amdgpu_device pointer
756 *
757 * Set up the compute DMA queues and enable them.
758 * Returns 0 for success, error for failure.
759 */
sdma_v5_2_rlc_resume(struct amdgpu_device * adev)760 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev)
761 {
762 return 0;
763 }
764
765 /**
766 * sdma_v5_2_load_microcode - load the sDMA ME ucode
767 *
768 * @adev: amdgpu_device pointer
769 *
770 * Loads the sDMA0/1/2/3 ucode.
771 * Returns 0 for success, -EINVAL if the ucode is not available.
772 */
sdma_v5_2_load_microcode(struct amdgpu_device * adev)773 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)
774 {
775 const struct sdma_firmware_header_v1_0 *hdr;
776 const __le32 *fw_data;
777 u32 fw_size;
778 int i, j;
779
780 /* halt the MEs */
781 sdma_v5_2_enable(adev, false);
782
783 for (i = 0; i < adev->sdma.num_instances; i++) {
784 if (!adev->sdma.instance[i].fw)
785 return -EINVAL;
786
787 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
788 amdgpu_ucode_print_sdma_hdr(&hdr->header);
789 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
790
791 fw_data = (const __le32 *)
792 (adev->sdma.instance[i].fw->data +
793 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
794
795 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
796
797 for (j = 0; j < fw_size; j++) {
798 if (amdgpu_emu_mode == 1 && j % 500 == 0)
799 msleep(1);
800 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
801 }
802
803 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
804 }
805
806 return 0;
807 }
808
sdma_v5_2_soft_reset(void * handle)809 static int sdma_v5_2_soft_reset(void *handle)
810 {
811 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
812 u32 grbm_soft_reset;
813 u32 tmp;
814 int i;
815
816 for (i = 0; i < adev->sdma.num_instances; i++) {
817 grbm_soft_reset = REG_SET_FIELD(0,
818 GRBM_SOFT_RESET, SOFT_RESET_SDMA0,
819 1);
820 grbm_soft_reset <<= i;
821
822 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
823 tmp |= grbm_soft_reset;
824 DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp);
825 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
826 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
827
828 udelay(50);
829
830 tmp &= ~grbm_soft_reset;
831 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
832 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
833
834 udelay(50);
835 }
836
837 return 0;
838 }
839
840 /**
841 * sdma_v5_2_start - setup and start the async dma engines
842 *
843 * @adev: amdgpu_device pointer
844 *
845 * Set up the DMA engines and enable them.
846 * Returns 0 for success, error for failure.
847 */
sdma_v5_2_start(struct amdgpu_device * adev)848 static int sdma_v5_2_start(struct amdgpu_device *adev)
849 {
850 int r = 0;
851
852 if (amdgpu_sriov_vf(adev)) {
853 sdma_v5_2_ctx_switch_enable(adev, false);
854 sdma_v5_2_enable(adev, false);
855
856 /* set RB registers */
857 r = sdma_v5_2_gfx_resume(adev);
858 return r;
859 }
860
861 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
862 r = sdma_v5_2_load_microcode(adev);
863 if (r)
864 return r;
865
866 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
867 if (amdgpu_emu_mode == 1)
868 msleep(1000);
869 }
870
871 /* TODO: check whether can submit a doorbell request to raise
872 * a doorbell fence to exit gfxoff.
873 */
874 if (adev->in_s0ix)
875 amdgpu_gfx_off_ctrl(adev, false);
876
877 sdma_v5_2_soft_reset(adev);
878 /* unhalt the MEs */
879 sdma_v5_2_enable(adev, true);
880 /* enable sdma ring preemption */
881 sdma_v5_2_ctx_switch_enable(adev, true);
882
883 /* start the gfx rings and rlc compute queues */
884 r = sdma_v5_2_gfx_resume(adev);
885 if (adev->in_s0ix)
886 amdgpu_gfx_off_ctrl(adev, true);
887 if (r)
888 return r;
889 r = sdma_v5_2_rlc_resume(adev);
890
891 return r;
892 }
893
894 /**
895 * sdma_v5_2_ring_test_ring - simple async dma engine test
896 *
897 * @ring: amdgpu_ring structure holding ring information
898 *
899 * Test the DMA engine by writing using it to write an
900 * value to memory.
901 * Returns 0 for success, error for failure.
902 */
sdma_v5_2_ring_test_ring(struct amdgpu_ring * ring)903 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)
904 {
905 struct amdgpu_device *adev = ring->adev;
906 unsigned i;
907 unsigned index;
908 int r;
909 u32 tmp;
910 u64 gpu_addr;
911
912 r = amdgpu_device_wb_get(adev, &index);
913 if (r) {
914 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
915 return r;
916 }
917
918 gpu_addr = adev->wb.gpu_addr + (index * 4);
919 tmp = 0xCAFEDEAD;
920 adev->wb.wb[index] = cpu_to_le32(tmp);
921
922 r = amdgpu_ring_alloc(ring, 5);
923 if (r) {
924 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
925 amdgpu_device_wb_free(adev, index);
926 return r;
927 }
928
929 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
930 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
931 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
932 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
933 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
934 amdgpu_ring_write(ring, 0xDEADBEEF);
935 amdgpu_ring_commit(ring);
936
937 for (i = 0; i < adev->usec_timeout; i++) {
938 tmp = le32_to_cpu(adev->wb.wb[index]);
939 if (tmp == 0xDEADBEEF)
940 break;
941 if (amdgpu_emu_mode == 1)
942 msleep(1);
943 else
944 udelay(1);
945 }
946
947 if (i >= adev->usec_timeout)
948 r = -ETIMEDOUT;
949
950 amdgpu_device_wb_free(adev, index);
951
952 return r;
953 }
954
955 /**
956 * sdma_v5_2_ring_test_ib - test an IB on the DMA engine
957 *
958 * @ring: amdgpu_ring structure holding ring information
959 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
960 *
961 * Test a simple IB in the DMA ring.
962 * Returns 0 on success, error on failure.
963 */
sdma_v5_2_ring_test_ib(struct amdgpu_ring * ring,long timeout)964 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
965 {
966 struct amdgpu_device *adev = ring->adev;
967 struct amdgpu_ib ib;
968 struct dma_fence *f = NULL;
969 unsigned index;
970 long r;
971 u32 tmp = 0;
972 u64 gpu_addr;
973
974 r = amdgpu_device_wb_get(adev, &index);
975 if (r) {
976 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
977 return r;
978 }
979
980 gpu_addr = adev->wb.gpu_addr + (index * 4);
981 tmp = 0xCAFEDEAD;
982 adev->wb.wb[index] = cpu_to_le32(tmp);
983 memset(&ib, 0, sizeof(ib));
984 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
985 if (r) {
986 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
987 goto err0;
988 }
989
990 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
991 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
992 ib.ptr[1] = lower_32_bits(gpu_addr);
993 ib.ptr[2] = upper_32_bits(gpu_addr);
994 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
995 ib.ptr[4] = 0xDEADBEEF;
996 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
997 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
998 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
999 ib.length_dw = 8;
1000
1001 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1002 if (r)
1003 goto err1;
1004
1005 r = dma_fence_wait_timeout(f, false, timeout);
1006 if (r == 0) {
1007 DRM_ERROR("amdgpu: IB test timed out\n");
1008 r = -ETIMEDOUT;
1009 goto err1;
1010 } else if (r < 0) {
1011 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1012 goto err1;
1013 }
1014 tmp = le32_to_cpu(adev->wb.wb[index]);
1015 if (tmp == 0xDEADBEEF)
1016 r = 0;
1017 else
1018 r = -EINVAL;
1019
1020 err1:
1021 amdgpu_ib_free(adev, &ib, NULL);
1022 dma_fence_put(f);
1023 err0:
1024 amdgpu_device_wb_free(adev, index);
1025 return r;
1026 }
1027
1028
1029 /**
1030 * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART
1031 *
1032 * @ib: indirect buffer to fill with commands
1033 * @pe: addr of the page entry
1034 * @src: src addr to copy from
1035 * @count: number of page entries to update
1036 *
1037 * Update PTEs by copying them from the GART using sDMA.
1038 */
sdma_v5_2_vm_copy_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t src,unsigned count)1039 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib,
1040 uint64_t pe, uint64_t src,
1041 unsigned count)
1042 {
1043 unsigned bytes = count * 8;
1044
1045 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1046 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1047 ib->ptr[ib->length_dw++] = bytes - 1;
1048 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1049 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1050 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1051 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1052 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1053
1054 }
1055
1056 /**
1057 * sdma_v5_2_vm_write_pte - update PTEs by writing them manually
1058 *
1059 * @ib: indirect buffer to fill with commands
1060 * @pe: addr of the page entry
1061 * @value: dst addr to write into pe
1062 * @count: number of page entries to update
1063 * @incr: increase next addr by incr bytes
1064 *
1065 * Update PTEs by writing them manually using sDMA.
1066 */
sdma_v5_2_vm_write_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t value,unsigned count,uint32_t incr)1067 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1068 uint64_t value, unsigned count,
1069 uint32_t incr)
1070 {
1071 unsigned ndw = count * 2;
1072
1073 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1074 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1075 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1076 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1077 ib->ptr[ib->length_dw++] = ndw - 1;
1078 for (; ndw > 0; ndw -= 2) {
1079 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1080 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1081 value += incr;
1082 }
1083 }
1084
1085 /**
1086 * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA
1087 *
1088 * @ib: indirect buffer to fill with commands
1089 * @pe: addr of the page entry
1090 * @addr: dst addr to write into pe
1091 * @count: number of page entries to update
1092 * @incr: increase next addr by incr bytes
1093 * @flags: access flags
1094 *
1095 * Update the page tables using sDMA.
1096 */
sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib * ib,uint64_t pe,uint64_t addr,unsigned count,uint32_t incr,uint64_t flags)1097 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1098 uint64_t pe,
1099 uint64_t addr, unsigned count,
1100 uint32_t incr, uint64_t flags)
1101 {
1102 /* for physically contiguous pages (vram) */
1103 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1104 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1105 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1106 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1107 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1108 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1109 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1110 ib->ptr[ib->length_dw++] = incr; /* increment size */
1111 ib->ptr[ib->length_dw++] = 0;
1112 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1113 }
1114
1115 /**
1116 * sdma_v5_2_ring_pad_ib - pad the IB
1117 *
1118 * @ib: indirect buffer to fill with padding
1119 * @ring: amdgpu_ring structure holding ring information
1120 *
1121 * Pad the IB with NOPs to a boundary multiple of 8.
1122 */
sdma_v5_2_ring_pad_ib(struct amdgpu_ring * ring,struct amdgpu_ib * ib)1123 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1124 {
1125 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1126 u32 pad_count;
1127 int i;
1128
1129 pad_count = (-ib->length_dw) & 0x7;
1130 for (i = 0; i < pad_count; i++)
1131 if (sdma && sdma->burst_nop && (i == 0))
1132 ib->ptr[ib->length_dw++] =
1133 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1134 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1135 else
1136 ib->ptr[ib->length_dw++] =
1137 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1138 }
1139
1140
1141 /**
1142 * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline
1143 *
1144 * @ring: amdgpu_ring pointer
1145 *
1146 * Make sure all previous operations are completed (CIK).
1147 */
sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring * ring)1148 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1149 {
1150 uint32_t seq = ring->fence_drv.sync_seq;
1151 uint64_t addr = ring->fence_drv.gpu_addr;
1152
1153 /* wait for idle */
1154 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1155 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1156 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1157 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1158 amdgpu_ring_write(ring, addr & 0xfffffffc);
1159 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1160 amdgpu_ring_write(ring, seq); /* reference */
1161 amdgpu_ring_write(ring, 0xffffffff); /* mask */
1162 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1163 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1164 }
1165
1166
1167 /**
1168 * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA
1169 *
1170 * @ring: amdgpu_ring pointer
1171 * @vmid: vmid number to use
1172 * @pd_addr: address
1173 *
1174 * Update the page table base and flush the VM TLB
1175 * using sDMA.
1176 */
sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)1177 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1178 unsigned vmid, uint64_t pd_addr)
1179 {
1180 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1181 }
1182
sdma_v5_2_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1183 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring,
1184 uint32_t reg, uint32_t val)
1185 {
1186 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1187 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1188 amdgpu_ring_write(ring, reg);
1189 amdgpu_ring_write(ring, val);
1190 }
1191
sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1192 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1193 uint32_t val, uint32_t mask)
1194 {
1195 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1196 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1197 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1198 amdgpu_ring_write(ring, reg << 2);
1199 amdgpu_ring_write(ring, 0);
1200 amdgpu_ring_write(ring, val); /* reference */
1201 amdgpu_ring_write(ring, mask); /* mask */
1202 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1203 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1204 }
1205
sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring * ring,uint32_t reg0,uint32_t reg1,uint32_t ref,uint32_t mask)1206 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1207 uint32_t reg0, uint32_t reg1,
1208 uint32_t ref, uint32_t mask)
1209 {
1210 amdgpu_ring_emit_wreg(ring, reg0, ref);
1211 /* wait for a cycle to reset vm_inv_eng*_ack */
1212 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1213 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1214 }
1215
sdma_v5_2_early_init(void * handle)1216 static int sdma_v5_2_early_init(void *handle)
1217 {
1218 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1219
1220 switch (adev->asic_type) {
1221 case CHIP_SIENNA_CICHLID:
1222 adev->sdma.num_instances = 4;
1223 break;
1224 case CHIP_NAVY_FLOUNDER:
1225 case CHIP_DIMGREY_CAVEFISH:
1226 adev->sdma.num_instances = 2;
1227 break;
1228 case CHIP_VANGOGH:
1229 case CHIP_BEIGE_GOBY:
1230 case CHIP_YELLOW_CARP:
1231 adev->sdma.num_instances = 1;
1232 break;
1233 default:
1234 break;
1235 }
1236
1237 sdma_v5_2_set_ring_funcs(adev);
1238 sdma_v5_2_set_buffer_funcs(adev);
1239 sdma_v5_2_set_vm_pte_funcs(adev);
1240 sdma_v5_2_set_irq_funcs(adev);
1241
1242 return 0;
1243 }
1244
sdma_v5_2_seq_to_irq_id(int seq_num)1245 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num)
1246 {
1247 switch (seq_num) {
1248 case 0:
1249 return SOC15_IH_CLIENTID_SDMA0;
1250 case 1:
1251 return SOC15_IH_CLIENTID_SDMA1;
1252 case 2:
1253 return SOC15_IH_CLIENTID_SDMA2;
1254 case 3:
1255 return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid;
1256 default:
1257 break;
1258 }
1259 return -EINVAL;
1260 }
1261
sdma_v5_2_seq_to_trap_id(int seq_num)1262 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num)
1263 {
1264 switch (seq_num) {
1265 case 0:
1266 return SDMA0_5_0__SRCID__SDMA_TRAP;
1267 case 1:
1268 return SDMA1_5_0__SRCID__SDMA_TRAP;
1269 case 2:
1270 return SDMA2_5_0__SRCID__SDMA_TRAP;
1271 case 3:
1272 return SDMA3_5_0__SRCID__SDMA_TRAP;
1273 default:
1274 break;
1275 }
1276 return -EINVAL;
1277 }
1278
sdma_v5_2_sw_init(void * handle)1279 static int sdma_v5_2_sw_init(void *handle)
1280 {
1281 struct amdgpu_ring *ring;
1282 int r, i;
1283 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1284
1285 /* SDMA trap event */
1286 for (i = 0; i < adev->sdma.num_instances; i++) {
1287 r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i),
1288 sdma_v5_2_seq_to_trap_id(i),
1289 &adev->sdma.trap_irq);
1290 if (r)
1291 return r;
1292 }
1293
1294 r = sdma_v5_2_init_microcode(adev);
1295 if (r) {
1296 DRM_ERROR("Failed to load sdma firmware!\n");
1297 return r;
1298 }
1299
1300 for (i = 0; i < adev->sdma.num_instances; i++) {
1301 ring = &adev->sdma.instance[i].ring;
1302 ring->ring_obj = NULL;
1303 ring->use_doorbell = true;
1304 ring->me = i;
1305
1306 DRM_INFO("use_doorbell being set to: [%s]\n",
1307 ring->use_doorbell?"true":"false");
1308
1309 ring->doorbell_index =
1310 (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset
1311
1312 sprintf(ring->name, "sdma%d", i);
1313 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1314 AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1315 AMDGPU_RING_PRIO_DEFAULT, NULL);
1316 if (r)
1317 return r;
1318 }
1319
1320 return r;
1321 }
1322
sdma_v5_2_sw_fini(void * handle)1323 static int sdma_v5_2_sw_fini(void *handle)
1324 {
1325 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1326 int i;
1327
1328 for (i = 0; i < adev->sdma.num_instances; i++)
1329 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1330
1331 sdma_v5_2_destroy_inst_ctx(adev);
1332
1333 return 0;
1334 }
1335
sdma_v5_2_hw_init(void * handle)1336 static int sdma_v5_2_hw_init(void *handle)
1337 {
1338 int r;
1339 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1340
1341 r = sdma_v5_2_start(adev);
1342
1343 return r;
1344 }
1345
sdma_v5_2_hw_fini(void * handle)1346 static int sdma_v5_2_hw_fini(void *handle)
1347 {
1348 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1349
1350 if (amdgpu_sriov_vf(adev))
1351 return 0;
1352
1353 sdma_v5_2_ctx_switch_enable(adev, false);
1354 sdma_v5_2_enable(adev, false);
1355
1356 return 0;
1357 }
1358
sdma_v5_2_suspend(void * handle)1359 static int sdma_v5_2_suspend(void *handle)
1360 {
1361 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1362
1363 return sdma_v5_2_hw_fini(adev);
1364 }
1365
sdma_v5_2_resume(void * handle)1366 static int sdma_v5_2_resume(void *handle)
1367 {
1368 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1369
1370 return sdma_v5_2_hw_init(adev);
1371 }
1372
sdma_v5_2_is_idle(void * handle)1373 static bool sdma_v5_2_is_idle(void *handle)
1374 {
1375 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1376 u32 i;
1377
1378 for (i = 0; i < adev->sdma.num_instances; i++) {
1379 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1380
1381 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1382 return false;
1383 }
1384
1385 return true;
1386 }
1387
sdma_v5_2_wait_for_idle(void * handle)1388 static int sdma_v5_2_wait_for_idle(void *handle)
1389 {
1390 unsigned i;
1391 u32 sdma0, sdma1, sdma2, sdma3;
1392 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1393
1394 for (i = 0; i < adev->usec_timeout; i++) {
1395 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1396 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1397 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG));
1398 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG));
1399
1400 if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK)
1401 return 0;
1402 udelay(1);
1403 }
1404 return -ETIMEDOUT;
1405 }
1406
sdma_v5_2_ring_preempt_ib(struct amdgpu_ring * ring)1407 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)
1408 {
1409 int i, r = 0;
1410 struct amdgpu_device *adev = ring->adev;
1411 u32 index = 0;
1412 u64 sdma_gfx_preempt;
1413
1414 amdgpu_sdma_get_index_from_ring(ring, &index);
1415 sdma_gfx_preempt =
1416 sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT);
1417
1418 /* assert preemption condition */
1419 amdgpu_ring_set_preempt_cond_exec(ring, false);
1420
1421 /* emit the trailing fence */
1422 ring->trail_seq += 1;
1423 amdgpu_ring_alloc(ring, 10);
1424 sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1425 ring->trail_seq, 0);
1426 amdgpu_ring_commit(ring);
1427
1428 /* assert IB preemption */
1429 WREG32(sdma_gfx_preempt, 1);
1430
1431 /* poll the trailing fence */
1432 for (i = 0; i < adev->usec_timeout; i++) {
1433 if (ring->trail_seq ==
1434 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1435 break;
1436 udelay(1);
1437 }
1438
1439 if (i >= adev->usec_timeout) {
1440 r = -EINVAL;
1441 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1442 }
1443
1444 /* deassert IB preemption */
1445 WREG32(sdma_gfx_preempt, 0);
1446
1447 /* deassert the preemption condition */
1448 amdgpu_ring_set_preempt_cond_exec(ring, true);
1449 return r;
1450 }
1451
sdma_v5_2_set_trap_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1452 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev,
1453 struct amdgpu_irq_src *source,
1454 unsigned type,
1455 enum amdgpu_interrupt_state state)
1456 {
1457 u32 sdma_cntl;
1458
1459 u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);
1460
1461 sdma_cntl = RREG32(reg_offset);
1462 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1463 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1464 WREG32(reg_offset, sdma_cntl);
1465
1466 return 0;
1467 }
1468
sdma_v5_2_process_trap_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1469 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
1470 struct amdgpu_irq_src *source,
1471 struct amdgpu_iv_entry *entry)
1472 {
1473 DRM_DEBUG("IH: SDMA trap\n");
1474 switch (entry->client_id) {
1475 case SOC15_IH_CLIENTID_SDMA0:
1476 switch (entry->ring_id) {
1477 case 0:
1478 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1479 break;
1480 case 1:
1481 /* XXX compute */
1482 break;
1483 case 2:
1484 /* XXX compute */
1485 break;
1486 case 3:
1487 /* XXX page queue*/
1488 break;
1489 }
1490 break;
1491 case SOC15_IH_CLIENTID_SDMA1:
1492 switch (entry->ring_id) {
1493 case 0:
1494 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1495 break;
1496 case 1:
1497 /* XXX compute */
1498 break;
1499 case 2:
1500 /* XXX compute */
1501 break;
1502 case 3:
1503 /* XXX page queue*/
1504 break;
1505 }
1506 break;
1507 case SOC15_IH_CLIENTID_SDMA2:
1508 switch (entry->ring_id) {
1509 case 0:
1510 amdgpu_fence_process(&adev->sdma.instance[2].ring);
1511 break;
1512 case 1:
1513 /* XXX compute */
1514 break;
1515 case 2:
1516 /* XXX compute */
1517 break;
1518 case 3:
1519 /* XXX page queue*/
1520 break;
1521 }
1522 break;
1523 case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid:
1524 switch (entry->ring_id) {
1525 case 0:
1526 amdgpu_fence_process(&adev->sdma.instance[3].ring);
1527 break;
1528 case 1:
1529 /* XXX compute */
1530 break;
1531 case 2:
1532 /* XXX compute */
1533 break;
1534 case 3:
1535 /* XXX page queue*/
1536 break;
1537 }
1538 break;
1539 }
1540 return 0;
1541 }
1542
sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1543 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1544 struct amdgpu_irq_src *source,
1545 struct amdgpu_iv_entry *entry)
1546 {
1547 return 0;
1548 }
1549
sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)1550 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1551 bool enable)
1552 {
1553 uint32_t data, def;
1554 int i;
1555
1556 for (i = 0; i < adev->sdma.num_instances; i++) {
1557
1558 if (adev->sdma.instance[i].fw_version < 70 && adev->asic_type == CHIP_VANGOGH)
1559 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG;
1560
1561 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1562 /* Enable sdma clock gating */
1563 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1564 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1565 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1566 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1567 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1568 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1569 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1570 if (def != data)
1571 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1572 } else {
1573 /* Disable sdma clock gating */
1574 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1575 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1576 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1577 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1578 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1579 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1580 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1581 if (def != data)
1582 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1583 }
1584 }
1585 }
1586
sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)1587 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1588 bool enable)
1589 {
1590 uint32_t data, def;
1591 int i;
1592
1593 for (i = 0; i < adev->sdma.num_instances; i++) {
1594
1595 if (adev->sdma.instance[i].fw_version < 70 && adev->asic_type == CHIP_VANGOGH)
1596 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS;
1597
1598 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1599 /* Enable sdma mem light sleep */
1600 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1601 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1602 if (def != data)
1603 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1604
1605 } else {
1606 /* Disable sdma mem light sleep */
1607 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1608 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1609 if (def != data)
1610 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1611
1612 }
1613 }
1614 }
1615
sdma_v5_2_set_clockgating_state(void * handle,enum amd_clockgating_state state)1616 static int sdma_v5_2_set_clockgating_state(void *handle,
1617 enum amd_clockgating_state state)
1618 {
1619 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1620
1621 if (amdgpu_sriov_vf(adev))
1622 return 0;
1623
1624 switch (adev->asic_type) {
1625 case CHIP_SIENNA_CICHLID:
1626 case CHIP_NAVY_FLOUNDER:
1627 case CHIP_VANGOGH:
1628 case CHIP_DIMGREY_CAVEFISH:
1629 case CHIP_BEIGE_GOBY:
1630 case CHIP_YELLOW_CARP:
1631 sdma_v5_2_update_medium_grain_clock_gating(adev,
1632 state == AMD_CG_STATE_GATE);
1633 sdma_v5_2_update_medium_grain_light_sleep(adev,
1634 state == AMD_CG_STATE_GATE);
1635 break;
1636 default:
1637 break;
1638 }
1639
1640 return 0;
1641 }
1642
sdma_v5_2_set_powergating_state(void * handle,enum amd_powergating_state state)1643 static int sdma_v5_2_set_powergating_state(void *handle,
1644 enum amd_powergating_state state)
1645 {
1646 return 0;
1647 }
1648
sdma_v5_2_get_clockgating_state(void * handle,u32 * flags)1649 static void sdma_v5_2_get_clockgating_state(void *handle, u32 *flags)
1650 {
1651 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1652 int data;
1653
1654 if (amdgpu_sriov_vf(adev))
1655 *flags = 0;
1656
1657 /* AMD_CG_SUPPORT_SDMA_LS */
1658 data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1659 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1660 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1661 }
1662
sdma_v5_2_ring_begin_use(struct amdgpu_ring * ring)1663 static void sdma_v5_2_ring_begin_use(struct amdgpu_ring *ring)
1664 {
1665 struct amdgpu_device *adev = ring->adev;
1666
1667 /* SDMA 5.2.3 (RMB) FW doesn't seem to properly
1668 * disallow GFXOFF in some cases leading to
1669 * hangs in SDMA. Disallow GFXOFF while SDMA is active.
1670 * We can probably just limit this to 5.2.3,
1671 * but it shouldn't hurt for other parts since
1672 * this GFXOFF will be disallowed anyway when SDMA is
1673 * active, this just makes it explicit.
1674 */
1675 amdgpu_gfx_off_ctrl(adev, false);
1676 }
1677
sdma_v5_2_ring_end_use(struct amdgpu_ring * ring)1678 static void sdma_v5_2_ring_end_use(struct amdgpu_ring *ring)
1679 {
1680 struct amdgpu_device *adev = ring->adev;
1681
1682 /* SDMA 5.2.3 (RMB) FW doesn't seem to properly
1683 * disallow GFXOFF in some cases leading to
1684 * hangs in SDMA. Allow GFXOFF when SDMA is complete.
1685 */
1686 amdgpu_gfx_off_ctrl(adev, true);
1687 }
1688
1689 const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
1690 .name = "sdma_v5_2",
1691 .early_init = sdma_v5_2_early_init,
1692 .late_init = NULL,
1693 .sw_init = sdma_v5_2_sw_init,
1694 .sw_fini = sdma_v5_2_sw_fini,
1695 .hw_init = sdma_v5_2_hw_init,
1696 .hw_fini = sdma_v5_2_hw_fini,
1697 .suspend = sdma_v5_2_suspend,
1698 .resume = sdma_v5_2_resume,
1699 .is_idle = sdma_v5_2_is_idle,
1700 .wait_for_idle = sdma_v5_2_wait_for_idle,
1701 .soft_reset = sdma_v5_2_soft_reset,
1702 .set_clockgating_state = sdma_v5_2_set_clockgating_state,
1703 .set_powergating_state = sdma_v5_2_set_powergating_state,
1704 .get_clockgating_state = sdma_v5_2_get_clockgating_state,
1705 };
1706
1707 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
1708 .type = AMDGPU_RING_TYPE_SDMA,
1709 .align_mask = 0xf,
1710 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1711 .support_64bit_ptrs = true,
1712 .vmhub = AMDGPU_GFXHUB_0,
1713 .get_rptr = sdma_v5_2_ring_get_rptr,
1714 .get_wptr = sdma_v5_2_ring_get_wptr,
1715 .set_wptr = sdma_v5_2_ring_set_wptr,
1716 .emit_frame_size =
1717 5 + /* sdma_v5_2_ring_init_cond_exec */
1718 6 + /* sdma_v5_2_ring_emit_hdp_flush */
1719 3 + /* hdp_invalidate */
1720 6 + /* sdma_v5_2_ring_emit_pipeline_sync */
1721 /* sdma_v5_2_ring_emit_vm_flush */
1722 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1723 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1724 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */
1725 .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */
1726 .emit_ib = sdma_v5_2_ring_emit_ib,
1727 .emit_mem_sync = sdma_v5_2_ring_emit_mem_sync,
1728 .emit_fence = sdma_v5_2_ring_emit_fence,
1729 .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync,
1730 .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush,
1731 .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush,
1732 .test_ring = sdma_v5_2_ring_test_ring,
1733 .test_ib = sdma_v5_2_ring_test_ib,
1734 .insert_nop = sdma_v5_2_ring_insert_nop,
1735 .pad_ib = sdma_v5_2_ring_pad_ib,
1736 .begin_use = sdma_v5_2_ring_begin_use,
1737 .end_use = sdma_v5_2_ring_end_use,
1738 .emit_wreg = sdma_v5_2_ring_emit_wreg,
1739 .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait,
1740 .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,
1741 .init_cond_exec = sdma_v5_2_ring_init_cond_exec,
1742 .patch_cond_exec = sdma_v5_2_ring_patch_cond_exec,
1743 .preempt_ib = sdma_v5_2_ring_preempt_ib,
1744 };
1745
sdma_v5_2_set_ring_funcs(struct amdgpu_device * adev)1746 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)
1747 {
1748 int i;
1749
1750 for (i = 0; i < adev->sdma.num_instances; i++) {
1751 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs;
1752 adev->sdma.instance[i].ring.me = i;
1753 }
1754 }
1755
1756 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = {
1757 .set = sdma_v5_2_set_trap_irq_state,
1758 .process = sdma_v5_2_process_trap_irq,
1759 };
1760
1761 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = {
1762 .process = sdma_v5_2_process_illegal_inst_irq,
1763 };
1764
sdma_v5_2_set_irq_funcs(struct amdgpu_device * adev)1765 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev)
1766 {
1767 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1768 adev->sdma.num_instances;
1769 adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs;
1770 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs;
1771 }
1772
1773 /**
1774 * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine
1775 *
1776 * @ib: indirect buffer to copy to
1777 * @src_offset: src GPU address
1778 * @dst_offset: dst GPU address
1779 * @byte_count: number of bytes to xfer
1780 * @tmz: if a secure copy should be used
1781 *
1782 * Copy GPU buffers using the DMA engine.
1783 * Used by the amdgpu ttm implementation to move pages if
1784 * registered as the asic copy callback.
1785 */
sdma_v5_2_emit_copy_buffer(struct amdgpu_ib * ib,uint64_t src_offset,uint64_t dst_offset,uint32_t byte_count,bool tmz)1786 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib,
1787 uint64_t src_offset,
1788 uint64_t dst_offset,
1789 uint32_t byte_count,
1790 bool tmz)
1791 {
1792 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1793 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1794 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1795 ib->ptr[ib->length_dw++] = byte_count - 1;
1796 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1797 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1798 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1799 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1800 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1801 }
1802
1803 /**
1804 * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine
1805 *
1806 * @ib: indirect buffer to fill
1807 * @src_data: value to write to buffer
1808 * @dst_offset: dst GPU address
1809 * @byte_count: number of bytes to xfer
1810 *
1811 * Fill GPU buffers using the DMA engine.
1812 */
sdma_v5_2_emit_fill_buffer(struct amdgpu_ib * ib,uint32_t src_data,uint64_t dst_offset,uint32_t byte_count)1813 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
1814 uint32_t src_data,
1815 uint64_t dst_offset,
1816 uint32_t byte_count)
1817 {
1818 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1819 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1820 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1821 ib->ptr[ib->length_dw++] = src_data;
1822 ib->ptr[ib->length_dw++] = byte_count - 1;
1823 }
1824
1825 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
1826 .copy_max_bytes = 0x400000,
1827 .copy_num_dw = 7,
1828 .emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
1829
1830 .fill_max_bytes = 0x400000,
1831 .fill_num_dw = 5,
1832 .emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
1833 };
1834
sdma_v5_2_set_buffer_funcs(struct amdgpu_device * adev)1835 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev)
1836 {
1837 if (adev->mman.buffer_funcs == NULL) {
1838 adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs;
1839 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1840 }
1841 }
1842
1843 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = {
1844 .copy_pte_num_dw = 7,
1845 .copy_pte = sdma_v5_2_vm_copy_pte,
1846 .write_pte = sdma_v5_2_vm_write_pte,
1847 .set_pte_pde = sdma_v5_2_vm_set_pte_pde,
1848 };
1849
sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device * adev)1850 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev)
1851 {
1852 unsigned i;
1853
1854 if (adev->vm_manager.vm_pte_funcs == NULL) {
1855 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs;
1856 for (i = 0; i < adev->sdma.num_instances; i++) {
1857 adev->vm_manager.vm_pte_scheds[i] =
1858 &adev->sdma.instance[i].ring.sched;
1859 }
1860 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1861 }
1862 }
1863
1864 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = {
1865 .type = AMD_IP_BLOCK_TYPE_SDMA,
1866 .major = 5,
1867 .minor = 2,
1868 .rev = 0,
1869 .funcs = &sdma_v5_2_ip_funcs,
1870 };
1871