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Searched refs:HVS_READ (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/vc4/
Dvc4_hvs.c207 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1), in vc4_hvs_get_fifo_frame_count()
211 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1), in vc4_hvs_get_fifo_frame_count()
215 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT2), in vc4_hvs_get_fifo_frame_count()
240 reg = HVS_READ(SCALER_DISPECTRL); in vc4_hvs_get_fifo_from_output()
248 reg = HVS_READ(SCALER_DISPCTRL); in vc4_hvs_get_fifo_from_output()
256 reg = HVS_READ(SCALER_DISPEOLN); in vc4_hvs_get_fifo_from_output()
264 reg = HVS_READ(SCALER_DISPDITHER); in vc4_hvs_get_fifo_from_output()
311 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(chan)); in vc4_hvs_init_channel()
332 if (HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_ENABLE) in vc4_hvs_stop_channel()
336 HVS_READ(SCALER_DISPCTRLX(chan)) | SCALER_DISPCTRLX_RESET); in vc4_hvs_stop_channel()
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Dvc4_kms.c262 dispctrl = HVS_READ(SCALER_DISPCTRL) & in vc4_hvs_pv_muxing_commit()
287 reg = HVS_READ(SCALER_DISPECTRL); in vc5_hvs_pv_muxing_commit()
299 reg = HVS_READ(SCALER_DISPCTRL); in vc5_hvs_pv_muxing_commit()
311 reg = HVS_READ(SCALER_DISPEOLN); in vc5_hvs_pv_muxing_commit()
324 reg = HVS_READ(SCALER_DISPDITHER); in vc5_hvs_pv_muxing_commit()
Dvc4_crtc.c73 u32 dispbase = HVS_READ(SCALER_DISPBASEX(channel)); in vc4_crtc_get_cob_allocation()
110 val = HVS_READ(SCALER_DISPSTATX(vc4_crtc_state->assigned_channel)); in vc4_crtc_get_scanout_position()
432 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) != in require_hvs_enabled()
721 (vc4_crtc->current_dlist == HVS_READ(SCALER_DISPLACTX(chan)) || in vc4_crtc_handle_page_flip()
Dvc4_drv.h575 #define HVS_READ(offset) readl(vc4->hvs->regs + offset) macro