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Searched refs:NUM_LINK_LEVELS (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/pm/inc/
Dsmu9_driver_if.h44 #define NUM_LINK_LEVELS 2 macro
53 #define MAX_LINK_DPM_LEVEL (NUM_LINK_LEVELS - 1)
236 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; /* 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */
237 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; /* 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */
238 …uint8_t LclkDid[NUM_LINK_LEVELS]; /* Leave at 0 to use hardcoded values in FW */
Dsmu11_driver_if.h48 #define NUM_LINK_LEVELS 2 macro
63 #define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1)
452 uint8_t PcieGenSpeed[NUM_LINK_LEVELS];
453 uint8_t PcieLaneCount[NUM_LINK_LEVELS];
454 uint16_t LclkFreq[NUM_LINK_LEVELS];
Dsmu11_driver_if_sienna_cichlid.h47 #define NUM_LINK_LEVELS 2 macro
66 #define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1)
738 …uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:P…
739 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
740 uint16_t LclkFreq[NUM_LINK_LEVELS];
1097 …uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:P…
1098 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
1099 uint16_t LclkFreq[NUM_LINK_LEVELS];
Dsmu11_driver_if_navi10.h47 #define NUM_LINK_LEVELS 2 macro
62 #define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1)
625 …uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:P…
626 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
627 uint16_t LclkFreq[NUM_LINK_LEVELS];
/drivers/gpu/drm/amd/pm/inc/vega12/
Dsmu9_driver_if.h46 #define NUM_LINK_LEVELS 2 macro
59 #define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1)
340 uint8_t PcieGenSpeed[NUM_LINK_LEVELS];
341 uint8_t PcieLaneCount[NUM_LINK_LEVELS];
342 uint16_t LclkFreq[NUM_LINK_LEVELS];
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dvega20_processpptables.c399 for (i = 0; i < NUM_LINK_LEVELS; i++)
403 for (i = 0; i < NUM_LINK_LEVELS; i++)
407 for (i = 0; i < NUM_LINK_LEVELS; i++)
Dvega10_hwmgr.c1262 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega10_setup_default_pcie_table()
1284 pcie_table->count = NUM_LINK_LEVELS; in vega10_setup_default_pcie_table()
1541 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega10_override_pcie_parameters()
1550 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega10_override_pcie_parameters()
1581 while (i < NUM_LINK_LEVELS) { in vega10_populate_smc_link_levels()
4699 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega10_print_clock_levels()
Dvega20_hwmgr.c866 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega20_override_pcie_parameters()
890 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega20_override_pcie_parameters()
2698 if (soft_min_level >= NUM_LINK_LEVELS || in vega20_force_clock_level()
2699 soft_max_level >= NUM_LINK_LEVELS) in vega20_force_clock_level()
3460 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega20_print_clock_levels()
Dvega12_hwmgr.c521 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega12_override_pcie_parameters()
545 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega12_override_pcie_parameters()
/drivers/gpu/drm/amd/pm/swsmu/smu11/
Dsienna_cichlid_ppt.c1172 for (i = 0; i < NUM_LINK_LEVELS; i++) in sienna_cichlid_print_clk_levels()
2015 for (i = 0; i < NUM_LINK_LEVELS; i++) { in sienna_cichlid_update_pcie_parameters()
2729 for (i = 0; i < NUM_LINK_LEVELS; i++) in beige_goby_dump_pptable()
2733 for (i = 0; i < NUM_LINK_LEVELS; i++) in beige_goby_dump_pptable()
2737 for (i = 0; i < NUM_LINK_LEVELS; i++) in beige_goby_dump_pptable()
3367 for (i = 0; i < NUM_LINK_LEVELS; i++) in sienna_cichlid_dump_pptable()
3371 for (i = 0; i < NUM_LINK_LEVELS; i++) in sienna_cichlid_dump_pptable()
3375 for (i = 0; i < NUM_LINK_LEVELS; i++) in sienna_cichlid_dump_pptable()
Dnavi10_ppt.c1338 for (i = 0; i < NUM_LINK_LEVELS; i++) in navi10_print_clk_levels()
2205 for (i = 0; i < NUM_LINK_LEVELS; i++) { in navi10_update_pcie_parameters()