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Searched refs:RCS0 (Results 1 – 22 of 22) sorted by relevance

/drivers/gpu/drm/i915/gvt/
Dmmio_context.c47 {RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
48 {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
49 {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
50 {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
51 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
52 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
53 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
54 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
55 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
56 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
[all …]
Dscheduler.c99 if (workload->engine->id != RCS0) in sr_oa_regs()
163 if (workload->engine->id == RCS0) { in populate_shadow_context()
216 if (IS_BROADWELL(gvt->gt->i915) && workload->engine->id == RCS0) in populate_shadow_context()
503 if (workload->engine->id == RCS0 && in intel_gvt_scan_and_shadow_workload()
976 if (IS_BROADWELL(rq->engine->i915) && rq->engine->id == RCS0) in update_guest_context()
1702 if (engine->id == RCS0) { in intel_vgpu_create_workload()
Dexeclist.c49 [RCS0] = RCS_AS_CONTEXT_SWITCH,
Dcmd_parser.c421 #define R_RCS BIT(RCS0)
593 [RCS0] = {
1047 if (IS_BROADWELL(s->engine->i915) && s->engine->id != RCS0) { in cmd_handler_lri()
1148 [RCS0] = {
Dhandlers.c329 engine_mask |= BIT(RCS0); in gdrst_mmio_write()
2079 id = RCS0; in gvt_reg_tlb_control_handler()
/drivers/gpu/drm/i915/
Di915_pci.c169 .platform_engine_mask = BIT(RCS0), \
189 .platform_engine_mask = BIT(RCS0), \
227 .platform_engine_mask = BIT(RCS0), \
318 .platform_engine_mask = BIT(RCS0), \
350 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
360 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
369 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
400 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
452 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
525 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
[all …]
Di915_irq.c4058 intel_engine_cs_irq(dev_priv->gt.engine[RCS0], iir); in i8xx_irq_handler()
4166 intel_engine_cs_irq(dev_priv->gt.engine[RCS0], iir); in i915_irq_handler()
4311 intel_engine_cs_irq(dev_priv->gt.engine[RCS0], in i965_irq_handler()
Di915_gpu_error.c1178 case RCS0: in engine_record_registers()
/drivers/gpu/drm/i915/selftests/
Dmock_gem_device.c201 i915->gt.engine[RCS0] = mock_engine(i915, "mock", RCS0); in mock_gem_device()
202 if (!i915->gt.engine[RCS0]) in mock_gem_device()
205 if (mock_engine_init(i915->gt.engine[RCS0])) in mock_gem_device()
Di915_request.c213 ce = i915_gem_context_get_engine(ctx[0], RCS0); in igt_request_rewind()
227 ce = i915_gem_context_get_engine(ctx[1], RCS0); in igt_request_rewind()
/drivers/gpu/drm/i915/gt/
Dselftest_gt_pm.c108 if (GRAPHICS_VER(engine->i915) < 7 && engine->id != RCS0) in live_gt_clocks()
Dintel_engine_types.h101 RCS0 = 0, enumerator
Dintel_engine_cs.c54 [RCS0] = {
1178 if (engine->id != RCS0) in intel_engine_get_instdone()
1202 if (engine->id != RCS0) in intel_engine_get_instdone()
1218 if (engine->id == RCS0) in intel_engine_get_instdone()
Dintel_engine_user.c161 [RENDER_CLASS] = { RCS0, 1 }, in legacy_ring_idx()
Dintel_mocs.c427 [RCS0] = __GEN9_RCS0_MOCS0, in mocs_offset()
Dintel_ring_submission.c85 case RCS0: in set_hwsp()
929 GEM_BUG_ON(engine->id != RCS0); in switch_context()
Dselftest_hangcheck.c1303 struct intel_engine_cs *engine = gt->engine[RCS0]; in igt_reset_wait()
1433 struct intel_engine_cs *engine = gt->engine[RCS0]; in __igt_reset_evict_vma()
1820 struct intel_engine_cs *engine = gt->engine[RCS0]; in igt_handle_error()
Dintel_reset.c323 [RCS0] = GEN6_GRDOM_RENDER, in __gen6_reset_engines()
532 [RCS0] = GEN11_GRDOM_RENDER, in __gen11_reset_engines()
Dintel_execlists_submission.c3378 [RCS0] = GEN8_RCS_IRQ_SHIFT, in logical_ring_default_irqs()
/drivers/gpu/drm/i915/gem/
Di915_gem_execbuffer.c2034 if (GRAPHICS_VER(rq->engine->i915) != 7 || rq->engine->id != RCS0) { in i915_reset_gen7_sol_offsets()
2276 [I915_EXEC_DEFAULT] = RCS0,
2277 [I915_EXEC_RENDER] = RCS0,
/drivers/gpu/drm/i915/display/
Dintel_overlay.c1388 engine = dev_priv->gt.engine[RCS0]; in intel_overlay_setup()
/drivers/gpu/drm/i915/gt/uc/
Dintel_guc_submission.c1284 return mask >> RCS0; in adjust_engine_mask()