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Searched refs:REG_MASK (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_pingpong.c76 data = dither_depth_map[cfg->c0_bitdepth] & REG_MASK(2); in dpu_hw_pp_setup_dither()
77 data |= (dither_depth_map[cfg->c1_bitdepth] & REG_MASK(2)) << 2; in dpu_hw_pp_setup_dither()
78 data |= (dither_depth_map[cfg->c2_bitdepth] & REG_MASK(2)) << 4; in dpu_hw_pp_setup_dither()
79 data |= (dither_depth_map[cfg->c3_bitdepth] & REG_MASK(2)) << 6; in dpu_hw_pp_setup_dither()
85 data = (cfg->matrix[i] & REG_MASK(4)) | in dpu_hw_pp_setup_dither()
86 ((cfg->matrix[i + 1] & REG_MASK(4)) << 4) | in dpu_hw_pp_setup_dither()
87 ((cfg->matrix[i + 2] & REG_MASK(4)) << 8) | in dpu_hw_pp_setup_dither()
88 ((cfg->matrix[i + 3] & REG_MASK(4)) << 12); in dpu_hw_pp_setup_dither()
Ddpu_hw_util.h12 #define REG_MASK(n) ((BIT(n)) - 1) macro
/drivers/net/ethernet/mscc/
Docelot_io.c21 ocelot->map[target][reg & REG_MASK] + offset, &val); in __ocelot_read_ix()
33 ocelot->map[target][reg & REG_MASK] + offset, val); in __ocelot_write_ix()
45 ocelot->map[target][reg & REG_MASK] + offset, in __ocelot_rmw_ix()
58 regmap_read(port->target, ocelot->map[target][reg & REG_MASK], &val); in ocelot_port_readl()
70 regmap_write(port->target, ocelot->map[target][reg & REG_MASK], val); in ocelot_port_writel()
114 regfield.reg = ocelot->map[target][reg & REG_MASK]; in ocelot_regfields_init()
/drivers/media/dvb-frontends/
Drtl2832.c11 #define REG_MASK(b) (BIT(b + 1) - 1) macro
155 mask = REG_MASK(msb - lsb); in rtl2832_rd_demod_reg()
185 mask = REG_MASK(msb - lsb); in rtl2832_wr_demod_reg()
/drivers/soc/ti/
Dknav_dma.c30 #define REG_MASK 0xffffffff macro
309 v = ~DMA_ENABLE & REG_MASK; in knav_dma_hw_destroy()