/drivers/gpu/drm/radeon/ |
D | ci_smc.c | 116 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in ci_start_smc() 124 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in ci_reset_smc() 139 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in ci_stop_smc_clock() 148 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in ci_start_smc_clock() 157 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in ci_is_smc_running() 158 u32 pc_c = RREG32_SMC(SMC_PC_C); in ci_is_smc_running() 176 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
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D | si_smc.c | 115 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in si_start_smc() 131 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in si_reset_smc() 145 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in si_stop_smc_clock() 154 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in si_start_smc_clock() 163 u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in si_is_smc_running() 164 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in si_is_smc_running() 202 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in si_wait_for_smc_inactive()
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D | trinity_dpm.c | 334 value = RREG32_SMC(GFX_POWER_GATING_CNTL); in trinity_gfx_powergating_initialize() 462 if (RREG32_SMC(CC_SMU_TST_EFUSE1_MISC) & RB_BACKEND_DISABLE_MASK) in trinity_gfx_powergating_enable() 463 WREG32_SMC(SMU_SCRATCH_A, (RREG32_SMC(SMU_SCRATCH_A) | 0x01)); in trinity_gfx_powergating_enable() 478 value = RREG32_SMC(PM_I_CNTL_1); in trinity_gfx_dynamic_mgpg_enable() 483 value = RREG32_SMC(SMU_S_PG_CNTL); in trinity_gfx_dynamic_mgpg_enable() 488 value = RREG32_SMC(SMU_S_PG_CNTL); in trinity_gfx_dynamic_mgpg_enable() 492 value = RREG32_SMC(PM_I_CNTL_1); in trinity_gfx_dynamic_mgpg_enable() 552 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix); in trinity_set_divider_value() 562 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix); in trinity_set_divider_value() 574 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); in trinity_set_ds_dividers() [all …]
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D | ci_dpm.c | 560 data = RREG32_SMC(config_regs->offset); in ci_program_pt_config_registers() 862 tmp = RREG32_SMC(CG_THERMAL_INT); in ci_thermal_set_temperature_range() 870 tmp = RREG32_SMC(CG_THERMAL_CTRL); in ci_thermal_set_temperature_range() 885 u32 thermal_int = RREG32_SMC(CG_THERMAL_INT); in ci_thermal_enable_alert() 917 tmp = (RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; in ci_fan_ctrl_set_static_mode() 919 tmp = (RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; in ci_fan_ctrl_set_static_mode() 924 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK; in ci_fan_ctrl_set_static_mode() 928 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; in ci_fan_ctrl_set_static_mode() 949 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; in ci_thermal_setup_fan_table() 993 tmp = (RREG32_SMC(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; in ci_thermal_setup_fan_table() [all …]
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D | kv_dpm.c | 174 data = RREG32_SMC(config_regs->offset); in kv_program_pt_config_registers() 488 u32 tmp = RREG32_SMC(GENERAL_PWRMGT); in kv_start_dpm() 503 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); in kv_start_am() 513 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); in kv_reset_am() 1019 thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL); in kv_enable_thermal_int() 2238 nbdpmconfig1 = RREG32_SMC(NB_DPM_CONFIG_1); in kv_program_nbps_index_settings() 2265 tmp = RREG32_SMC(CG_THERMAL_INT_CTRL); in kv_set_thermal_temperature_range() 2603 (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >> in kv_dpm_debugfs_print_current_performance_level() 2612 tmp = (RREG32_SMC(SMU_VOLTAGE_STATUS) & SMU_VOLTAGE_CURRENT_LEVEL_MASK) >> in kv_dpm_debugfs_print_current_performance_level() 2626 (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >> in kv_dpm_get_current_sclk()
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D | kv_smc.c | 60 *enable_mask = RREG32_SMC(SMC_SYSCON_MSG_ARG_0); in kv_dpm_get_enable_mask()
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D | cik.c | 207 temp = (RREG32_SMC(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >> in ci_get_temp() 224 temp = RREG32_SMC(0xC0300E0C); in kv_get_temp() 1710 if (RREG32_SMC(GENERAL_PWRMGT) & GPU_COUNTER_CLK) in cik_get_xclk() 1713 if (RREG32_SMC(CG_CLKPIN_CNTL) & XTALIN_DIVIDE) in cik_get_xclk() 9419 tmp = RREG32_SMC(cntl_reg); in cik_set_uvd_clock() 9425 if (RREG32_SMC(status_reg) & DCLK_STATUS) in cik_set_uvd_clock() 9459 if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS) in cik_set_vce_clocks() 9466 tmp = RREG32_SMC(CG_ECLK_CNTL); in cik_set_vce_clocks() 9472 if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS) in cik_set_vce_clocks() 9748 orig = data = RREG32_SMC(THM_CLK_CNTL); in cik_program_aspm() [all …]
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D | radeon.h | 2561 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) macro 2593 uint32_t tmp_ = RREG32_SMC(reg); \
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D | ni.c | 869 u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff; in tn_get_temp()
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/drivers/gpu/drm/amd/pm/powerplay/ |
D | si_smc.c | 113 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in amdgpu_si_start_smc() 129 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL) | in amdgpu_si_reset_smc() 143 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in amdgpu_si_smc_clock() 155 u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in amdgpu_si_is_smc_running() 156 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in amdgpu_si_is_smc_running() 194 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in amdgpu_si_wait_for_smc_inactive()
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D | kv_dpm.c | 426 data = RREG32_SMC(config_regs->offset); in kv_program_pt_config_registers() 727 u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT); in kv_start_dpm() 742 u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL); in kv_start_am() 753 u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL); in kv_reset_am() 2493 nbdpmconfig1 = RREG32_SMC(ixNB_DPM_CONFIG_1); in kv_program_nbps_index_settings() 2522 tmp = RREG32_SMC(ixCG_THERMAL_INT_CTRL); in kv_set_thermal_temperature_range() 2854 (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) & in kv_dpm_debugfs_print_current_performance_level() 2864 tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) & in kv_dpm_debugfs_print_current_performance_level() 2939 temp = RREG32_SMC(0xC0300E0C); in kv_dpm_get_temp() 3133 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL); in kv_dpm_set_interrupt_state() [all …]
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D | kv_smc.c | 63 *enable_mask = RREG32_SMC(ixSMC_SYSCON_MSG_ARG_0); in amdgpu_kv_dpm_get_enable_mask()
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D | si_dpm.c | 2831 data = RREG32_SMC(offset); in si_program_cac_config_registers() 7509 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); in si_dpm_set_interrupt_state() 7514 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); in si_dpm_set_interrupt_state() 7526 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); in si_dpm_set_interrupt_state() 7531 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); in si_dpm_set_interrupt_state()
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/drivers/gpu/drm/amd/amdgpu/ |
D | vi.c | 555 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2); in vi_get_xclk() 559 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL); in vi_get_xclk() 610 rom_cntl = RREG32_SMC(ixROM_CNTL); in vi_read_disabled_bios() 999 tmp = RREG32_SMC(cntl_reg); in vi_set_uvd_clock() 1010 tmp = RREG32_SMC(status_reg); in vi_set_uvd_clock() 1086 if (RREG32_SMC(reg_status) & status_mask) in vi_set_vce_clocks() 1094 tmp = RREG32_SMC(reg_ctrl); in vi_set_vce_clocks() 1100 if (RREG32_SMC(reg_status) & status_mask) in vi_set_vce_clocks() 1211 orig = data = RREG32_SMC(ixTHM_CLK_CNTL); in vi_program_aspm() 1218 orig = data = RREG32_SMC(ixMISC_CLK_CTRL); in vi_program_aspm() [all …]
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D | cik.c | 922 if (RREG32_SMC(ixGENERAL_PWRMGT) & GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK) in cik_get_xclk() 925 if (RREG32_SMC(ixCG_CLKPIN_CNTL) & CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK) in cik_get_xclk() 982 rom_cntl = RREG32_SMC(ixROM_CNTL); in cik_read_disabled_bios() 1464 tmp = RREG32_SMC(cntl_reg); in cik_set_uvd_clock() 1471 if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK) in cik_set_uvd_clock() 1506 if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK) in cik_set_vce_clocks() 1513 tmp = RREG32_SMC(ixCG_ECLK_CNTL); in cik_set_vce_clocks() 1520 if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK) in cik_set_vce_clocks() 1806 orig = data = RREG32_SMC(ixTHM_CLK_CNTL); in cik_program_aspm() 1814 orig = data = RREG32_SMC(ixMISC_CLK_CTRL); in cik_program_aspm() [all …]
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D | vce_v3_0.c | 373 tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) & in vce_v3_0_get_harvest_config() 377 tmp = (RREG32_SMC(ixCC_HARVEST_FUSES) & in vce_v3_0_get_harvest_config() 840 data = RREG32_SMC(ixCURRENT_PG_STATUS_APU); in vce_v3_0_get_clockgating_state() 842 data = RREG32_SMC(ixCURRENT_PG_STATUS); in vce_v3_0_get_clockgating_state()
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D | uvd_v4_2.c | 728 if (!(RREG32_SMC(ixCURRENT_PG_STATUS) & in uvd_v4_2_set_powergating_state() 739 if (RREG32_SMC(ixCURRENT_PG_STATUS) & in uvd_v4_2_set_powergating_state()
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D | uvd_v6_0.c | 372 (RREG32_SMC(ixCC_HARVEST_FUSES) & CC_HARVEST_FUSES__UVD_DISABLE_MASK)) in uvd_v6_0_early_init() 1514 data = RREG32_SMC(ixCURRENT_PG_STATUS_APU); in uvd_v6_0_get_clockgating_state() 1516 data = RREG32_SMC(ixCURRENT_PG_STATUS); in uvd_v6_0_get_clockgating_state()
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D | amdgpu_cgs.c | 66 return RREG32_SMC(index); in amdgpu_cgs_read_ind_register()
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D | amdgpu.h | 1185 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) macro 1216 u32 tmp = RREG32_SMC(_Reg); \
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D | uvd_v5_0.c | 843 if (RREG32_SMC(ixCURRENT_PG_STATUS) & in uvd_v5_0_get_clockgating_state()
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D | vce_v4_0.c | 906 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
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D | amdgpu_debugfs.c | 488 value = RREG32_SMC(*pos); in amdgpu_debugfs_regs_smc_read()
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D | si.c | 1882 if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask) in si_vce_send_vcepll_ctlreq()
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D | uvd_v7_0.c | 1715 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
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