Searched refs:S3C_EP0SR (Results 1 – 1 of 1) sorted by relevance
58 #define S3C_EP0SR S3C_HSUDC_REG(0x24) /* EP0 Status */ macro268 writel(S3C_EP0SR_RX_SUCCESS, hsudc->regs + S3C_EP0SR); in s3c_hsudc_read_setup_pkt()335 offset = (ep_index(hsep)) ? S3C_ESR : S3C_EP0SR; in s3c_hsudc_read_fifo()646 u32 csr = readl(hsudc->regs + S3C_EP0SR); in s3c_hsudc_handle_ep0_intr()654 writel(S3C_EP0SR_STALL, hsudc->regs + S3C_EP0SR); in s3c_hsudc_handle_ep0_intr()664 writel(S3C_EP0SR_TX_SUCCESS, hsudc->regs + S3C_EP0SR); in s3c_hsudc_handle_ep0_intr()848 offset = (ep_index(hsep)) ? S3C_ESR : S3C_EP0SR; in s3c_hsudc_queue()