Searched refs:_MMIO (Results 1 – 17 of 17) sorted by relevance
/drivers/gpu/drm/i915/ |
D | i915_reg.h | 185 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) macro 187 #define INVALID_MMIO_REG _MMIO(0) 235 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) 236 #define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b)) 237 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) 238 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) 239 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) 240 #define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b)) 244 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) 245 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) [all …]
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D | i915_pvinfo.h | 117 #define vgtif_reg(x) _MMIO(VGT_PVINFO_PAGE + vgtif_offset(x))
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D | i915_perf.c | 4026 oa_regs[i].addr = _MMIO(addr); in alloc_oa_regs()
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/drivers/gpu/drm/i915/gt/uc/ |
D | intel_guc_reg.h | 16 #define GUC_STATUS _MMIO(0xc000) 39 #define SOFT_SCRATCH(n) _MMIO(0xc180 + (n) * 4) 42 #define GEN11_SOFT_SCRATCH(n) _MMIO(0x190240 + (n) * 4) 45 #define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4) 48 #define DMA_ADDR_0_LOW _MMIO(0xc300) 49 #define DMA_ADDR_0_HIGH _MMIO(0xc304) 50 #define DMA_ADDR_1_LOW _MMIO(0xc308) 51 #define DMA_ADDR_1_HIGH _MMIO(0xc30c) 54 #define DMA_COPY_SIZE _MMIO(0xc310) 55 #define DMA_CTRL _MMIO(0xc314) [all …]
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D | intel_guc.c | 55 return _MMIO(guc->send_regs.base + 4 * i); in guc_send_reg()
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/drivers/gpu/drm/i915/gvt/ |
D | reg.h | 72 (((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \ 73 (_MMIO(0x50090))) : \ 74 (((p) == PIPE_B) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50088)) : \ 75 (_MMIO(0x50098))) : \ 76 (((p) == PIPE_C) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x5008C)) : \ 77 (_MMIO(0x5009C))) : \ 78 (_MMIO(0x50080))))); }) 118 #define PCH_GPIO_BASE _MMIO(0xc5010) 120 #define PCH_GMBUS0 _MMIO(0xc5100) 121 #define PCH_GMBUS1 _MMIO(0xc5104) [all …]
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D | handlers.c | 45 #define PCH_PP_STATUS _MMIO(0xc7200) 46 #define PCH_PP_CONTROL _MMIO(0xc7204) 47 #define PCH_PP_ON_DELAYS _MMIO(0xc7208) 48 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 49 #define PCH_PP_DIVISOR _MMIO(0xc7210) 716 _MMIO(0xd80), 723 _MMIO(0x2690), 724 _MMIO(0x2694), 725 _MMIO(0x2698), 726 _MMIO(0x2754), [all …]
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D | mmio_context.c | 122 {RCS0, _MMIO(0x4dfc), 0, true}, 141 {RCS0, _MMIO(0x20D8), 0xffff, true}, /* 0x20d8 */ 369 reg = _MMIO(regs[engine->id]); in handle_tlb_pending_event()
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D | debugfs.c | 65 preg = intel_uncore_read_notrace(gvt->gt->uncore, _MMIO(offset)); in mmio_diff_handler()
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D | firmware.c | 72 _MMIO(offset)); in mmio_snapshot_handler()
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D | cmd_parser.c | 850 return i915_mmio_reg_equal(_MMIO(offset), GEN8_RING_PDP_UDW(base, 0)); in is_cmd_update_pdps()
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/drivers/gpu/drm/i915/gt/ |
D | intel_lrc_reg.h | 57 #define RING_ELSP(base) _MMIO((base) + 0x230) 58 #define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234) 59 #define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4) 60 #define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244) 66 #define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0) 67 #define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510) 68 #define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550)
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D | intel_mocs.c | 421 intel_uncore_write_fw(uncore, _MMIO(addr + i * 4), mocs); in __init_mocs_table()
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D | intel_workarounds.c | 1491 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), in icl_whitelist_build() 1494 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), in icl_whitelist_build() 1497 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), in icl_whitelist_build()
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D | intel_execlists_submission.c | 1767 _MMIO(engine->mmio_base + status)); in wa_csb_read()
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/drivers/gpu/drm/i915/selftests/ |
D | intel_uncore.c | 196 i915_reg_t mmio = _MMIO(engine->mmio_base + r->offset); in live_forcewake_ops()
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/drivers/gpu/drm/i915/display/ |
D | intel_dmc.c | 492 dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]); in parse_dmc_fw_header()
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