Home
last modified time | relevance | path

Searched refs:_val (Results 1 – 25 of 63) sorted by relevance

123

/drivers/staging/rtl8723bs/include/
Drtw_ht.h81 #define SET_HT_CTRL_CSI_STEERING(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 6, 2, _… argument
82 #define SET_HT_CTRL_NDP_ANNOUNCEMENT(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+3, 0, 1,… argument
86 …ne SET_EXT_CAPABILITY_ELE_BSS_COEXIST(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart), 0, 1,… argument
96 …_HT_CAP_TXBF_RECEIVE_NDP_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 3… argument
97 …HT_CAP_TXBF_TRANSMIT_NDP_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 4,… argument
98 …BF_EXPLICIT_COMP_STEERING_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 10,… argument
99 …BF_EXPLICIT_COMP_FEEDBACK_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 15,… argument
100 …BF_COMP_STEERING_NUM_ANTENNAS(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 23, … argument
Dbasic_types.h39 #define EF1BYTE(_val) \ argument
40 ((u8)(_val))
41 #define EF2BYTE(_val) \ argument
42 (le16_to_cpu(_val))
43 #define EF4BYTE(_val) \ argument
44 (le32_to_cpu(_val))
56 #define WRITEEF1BYTE(_ptr, _val) \ argument
58 (*((u8 *)(_ptr))) = EF1BYTE(_val); \
61 #define WRITEEF2BYTE(_ptr, _val) \ argument
63 (*((u16 *)(_ptr))) = EF2BYTE(_val); \
[all …]
/drivers/net/wireless/intel/iwlwifi/
Diwl-csr.h284 #define CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) argument
285 #define CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) argument
286 #define CSR_HW_REV_TYPE(_val) (((_val) & 0x000FFF0) >> 4) argument
289 #define CSR_HW_RFID_FLAVOR(_val) (((_val) & 0x000000F) >> 0) argument
290 #define CSR_HW_RFID_DASH(_val) (((_val) & 0x00000F0) >> 4) argument
291 #define CSR_HW_RFID_STEP(_val) (((_val) & 0x0000F00) >> 8) argument
292 #define CSR_HW_RFID_TYPE(_val) (((_val) & 0x0FFF000) >> 12) argument
293 #define CSR_HW_RFID_IS_CDB(_val) (((_val) & 0x10000000) >> 28) argument
294 #define CSR_HW_RFID_IS_JACKET(_val) (((_val) & 0x20000000) >> 29) argument
343 #define CSR_HW_RF_STEP(_val) (((_val) >> 8) & 0xF) argument
/drivers/staging/r8188eu/include/
Dbasic_types.h32 #define EF1BYTE(_val) \ argument
33 ((u8)(_val))
34 #define EF2BYTE(_val) \ argument
35 (le16_to_cpu(_val))
36 #define EF4BYTE(_val) \ argument
37 (le32_to_cpu(_val))
49 #define WRITEEF1BYTE(_ptr, _val) \ argument
51 (*((u8 *)(_ptr))) = EF1BYTE(_val) \
54 #define WRITEEF2BYTE(_ptr, _val) \ argument
56 (*((u16 *)(_ptr))) = EF2BYTE(_val) \
[all …]
/drivers/net/ethernet/amd/xgbe/
Dxgbe-common.h1411 #define SET_BITS(_var, _index, _width, _val) \ argument
1414 (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \
1420 #define SET_BITS_LE(_var, _index, _width, _val) \ argument
1423 (_var) |= cpu_to_le32((((_val) & \
1440 #define XGMAC_SET_BITS(_var, _prefix, _field, _val) \ argument
1443 _prefix##_##_field##_WIDTH, (_val))
1450 #define XGMAC_SET_BITS_LE(_var, _prefix, _field, _val) \ argument
1453 _prefix##_##_field##_WIDTH, (_val))
1470 #define XGMAC_IOWRITE(_pdata, _reg, _val) \ argument
1471 iowrite32((_val), (_pdata)->xgmac_regs + _reg)
[all …]
/drivers/net/wireless/realtek/rtlwifi/
Dbase.h49 #define SET_80211_PS_POLL_AID(_hdr, _val) \ argument
50 (*(u16 *)((u8 *)(_hdr) + 2) = _val)
51 #define SET_80211_PS_POLL_BSSID(_hdr, _val) \ argument
52 ether_addr_copy(((u8 *)(_hdr)) + 4, (u8 *)(_val))
53 #define SET_80211_PS_POLL_TA(_hdr, _val) \ argument
54 ether_addr_copy(((u8 *)(_hdr))+10, (u8 *)(_val))
56 #define SET_80211_HDR_ADDRESS1(_hdr, _val) \ argument
57 CP_MACADDR((u8 *)(_hdr)+FRAME_OFFSET_ADDRESS1, (u8 *)(_val))
58 #define SET_80211_HDR_ADDRESS2(_hdr, _val) \ argument
59 CP_MACADDR((u8 *)(_hdr)+FRAME_OFFSET_ADDRESS2, (u8 *)(_val))
[all …]
/drivers/pinctrl/mvebu/
Dpinctrl-mvebu.h157 #define _MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \ argument
159 .val = _val, \
167 #define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \ argument
168 _MPP_VAR_FUNCTION(_val, _name, _subname, _mask)
170 #define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \ argument
171 _MPP_VAR_FUNCTION(_val, _name, NULL, _mask)
174 #define MPP_FUNCTION(_val, _name, _subname) \ argument
175 MPP_VAR_FUNCTION(_val, _name, _subname, (u8)-1)
/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
Dfw.h324 #define FW_CMD_IO_UPDATE(rtlpriv, _val) \ argument
325 rtlpriv->rtlhal.fwcmd_iomap = _val;
327 #define FW_CMD_IO_SET(rtlpriv, _val) \ argument
329 rtl_write_word(rtlpriv, LBUS_MON_ADDR, (u16)_val); \
330 FW_CMD_IO_UPDATE(rtlpriv, _val); \
333 #define FW_CMD_PARA_SET(rtlpriv, _val) \ argument
335 rtl_write_dword(rtlpriv, LBUS_ADDR_MASK, _val); \
336 rtlpriv->rtlhal.fwcmd_ioparam = _val; \
/drivers/pinctrl/sunxi/
Dpinctrl-sunxi.h190 #define SUNXI_FUNCTION(_val, _name) \ argument
193 .muxval = _val, \
196 #define SUNXI_FUNCTION_VARIANT(_val, _name, _variant) \ argument
199 .muxval = _val, \
203 #define SUNXI_FUNCTION_IRQ(_val, _irq) \ argument
206 .muxval = _val, \
210 #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \ argument
213 .muxval = _val, \
/drivers/net/wireless/ath/ath11k/
Ddp.h1187 #define HTT_USR_RATE_PREAMBLE(_val) \ argument
1188 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M, _val)
1189 #define HTT_USR_RATE_BW(_val) \ argument
1190 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M, _val)
1191 #define HTT_USR_RATE_NSS(_val) \ argument
1192 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M, _val)
1193 #define HTT_USR_RATE_MCS(_val) \ argument
1194 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M, _val)
1195 #define HTT_USR_RATE_GI(_val) \ argument
1196 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M, _val)
[all …]
/drivers/media/tuners/
Dmc44s803_priv.h179 #define MC44S803_REG_SM(_val, _reg) \ argument
180 (((_val) << _reg##_S) & (_reg))
183 #define MC44S803_REG_MS(_val, _reg) \ argument
184 (((_val) & (_reg)) >> _reg##_S)
/drivers/gpu/drm/i915/gvt/
Dreg.h97 #define IS_MASKED_BITS_ENABLED(_val, _b) \ argument
98 (((_val) & _MASKED_BIT_ENABLE(_b)) == _MASKED_BIT_ENABLE(_b))
99 #define IS_MASKED_BITS_DISABLED(_val, _b) \ argument
100 ((_val) & _MASKED_BIT_DISABLE(_b))
/drivers/net/ethernet/synopsys/
Ddwc-xlgmac.h117 typeof(val) _val = (val); \
118 _val = (_val << _pos) & GENMASK(_pos + _len - 1, _pos); \
119 _var = (_var & ~GENMASK(_pos + _len - 1, _pos)) | _val; \
126 typeof(val) _val = (val); \
127 _val = (_val << _pos) & GENMASK(_pos + _len - 1, _pos); \
128 _var = (_var & ~GENMASK(_pos + _len - 1, _pos)) | _val; \
/drivers/power/supply/
Dmax77650-charger.c64 #define MAX77650_CHARGER_VCHGIN_MIN_SHIFT(_val) ((_val) << 5) argument
67 #define MAX77650_CHARGER_ICHGIN_LIM_SHIFT(_val) ((_val) << 2) argument
/drivers/pinctrl/mediatek/
Dpinctrl-paris.h37 #define MTK_FUNCTION(_val, _name) \ argument
39 .muxval = _val, \
/drivers/media/i2c/ccs/
Dccs-quirk.h59 #define CCS_MK_QUIRK_REG_8(_reg, _val) \ argument
62 .val = _val, \
/drivers/net/ethernet/stmicro/stmmac/
Ddwmac5.h65 #define SZ_CAP_HBFQ_MASK(_val) ({ typeof(_val) (val) = (_val); \ argument
/drivers/nvmem/
Duniphier-efuse.c20 unsigned int reg, void *_val, size_t bytes) in uniphier_reg_read() argument
23 u8 *val = _val; in uniphier_reg_read()
Dmtk-efuse.c19 unsigned int reg, void *_val, size_t bytes) in mtk_reg_read() argument
22 u32 *val = _val; in mtk_reg_read()
Dnintendo-otp.c49 unsigned int reg, void *_val, size_t bytes) in nintendo_otp_reg_read() argument
52 u32 *val = _val; in nintendo_otp_reg_read()
Dqfprom.c257 static int qfprom_reg_write(void *context, unsigned int reg, void *_val, in qfprom_reg_write() argument
263 u32 *value = _val; in qfprom_reg_write()
322 unsigned int reg, void *_val, size_t bytes) in qfprom_reg_read() argument
325 u8 *val = _val; in qfprom_reg_read()
/drivers/clk/meson/
Dvid-pll-div.c33 #define VID_PLL_DIV(_val, _sel, _ft, _fb) \ argument
35 .shift_val = (_val), \
/drivers/net/wireless/ath/
Dhw.c24 #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg) argument
/drivers/i2c/busses/
Di2c-brcmstb.c178 #define __bsc_writel(_val, _reg) iowrite32be(_val, _reg) argument
181 #define __bsc_writel(_val, _reg) iowrite32(_val, _reg) argument
187 #define bsc_writel(_dev, _val, _reg) \ argument
188 __bsc_writel(_val, _dev->base + offsetof(struct bsc_regs, _reg))
/drivers/gpu/drm/gma500/
Dpsb_drv.h807 #define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs)) argument
824 #define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs)) argument
828 #define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs)) argument

123