| /drivers/clk/ux500/ |
| D | u8500_of_clk.c | 65 u32 bases[CLKRST_MAX]; in u8500_clk_init() local
68 for (i = 0; i < ARRAY_SIZE(bases); i++) { in u8500_clk_init()
75 bases[i] = r.start; in u8500_clk_init()
256 clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
260 clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
264 clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
268 clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
272 clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
276 clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
280 clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
[all …]
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| /drivers/iommu/ |
| D | rockchip-iommu.c | 106 void __iomem **bases; member
348 writel(command, iommu->bases[i] + RK_MMU_COMMAND); in rk_iommu_command()
368 rk_iommu_write(iommu->bases[i], RK_MMU_ZAP_ONE_LINE, iova); in rk_iommu_zap_lines()
378 active &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) & in rk_iommu_is_stall_active()
390 enable &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) & in rk_iommu_is_paging_enabled()
402 done &= rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR) == 0; in rk_iommu_is_reset_done()
427 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_enable_stall()
448 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_disable_stall()
469 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_enable_paging()
490 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_disable_paging()
[all …]
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| /drivers/gpu/host1x/ |
| D | syncpt.c | 25 struct host1x_syncpt_base *bases = host->bases; in host1x_syncpt_base_request() local
29 if (!bases[i].requested) in host1x_syncpt_base_request()
35 bases[i].requested = true; in host1x_syncpt_base_request()
36 return &bases[i]; in host1x_syncpt_base_request()
321 struct host1x_syncpt_base *bases; in host1x_syncpt_init() local
330 bases = devm_kcalloc(host->dev, host->info->nb_bases, sizeof(*bases), in host1x_syncpt_init()
332 if (!bases) in host1x_syncpt_init()
348 bases[i].id = i; in host1x_syncpt_init()
352 host->bases = bases; in host1x_syncpt_init()
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| D | dev.h | 118 struct host1x_syncpt_base *bases; member
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| /drivers/gpu/drm/nouveau/dispnv50/ |
| D | base.c | 33 } bases[] = { in nv50_base_new() local
46 cid = nvif_mclass(&disp->disp->object, bases); in nv50_base_new()
52 return bases[cid].new(drm, head, bases[cid].oclass, pwndw); in nv50_base_new()
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| /drivers/iommu/arm/arm-smmu/ |
| D | arm-smmu-nvidia.c | 36 void __iomem *bases[MAX_SMMU_INSTANCES]; member
52 return nvidia_smmu->bases[inst] + (page << smmu->pgshift); in nvidia_smmu_page()
324 nvidia_smmu->bases[0] = smmu->base; in nvidia_smmu_impl_init()
332 nvidia_smmu->bases[i] = devm_ioremap_resource(dev, res); in nvidia_smmu_impl_init()
333 if (IS_ERR(nvidia_smmu->bases[i])) in nvidia_smmu_impl_init()
334 return ERR_CAST(nvidia_smmu->bases[i]); in nvidia_smmu_impl_init()
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| /drivers/gpu/drm/exynos/ |
| D | exynos_drm_scaler.c | 154 static unsigned int bases[] = { in scaler_set_src_base() local
162 scaler_write(src_buf->dma_addr[i], bases[i]); in scaler_set_src_base()
217 static unsigned int bases[] = { in scaler_set_dst_base() local
225 scaler_write(dst_buf->dma_addr[i], bases[i]); in scaler_set_dst_base()
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| /drivers/net/wireless/broadcom/b43/ |
| D | pio.c | 82 static const u16 bases[] = { in index_to_pioqueue_base() local
105 B43_WARN_ON(index >= ARRAY_SIZE(bases)); in index_to_pioqueue_base()
106 return bases[index]; in index_to_pioqueue_base()
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| /drivers/platform/mellanox/ |
| D | Kconfig | 33 are defined per system type bases and include the registers related
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| /drivers/gpu/drm/i915/gt/ |
| D | intel_engine_cs.c | 241 const struct engine_mmio_base *bases) in __engine_mmio_base() argument
246 if (GRAPHICS_VER(i915) >= bases[i].graphics_ver) in __engine_mmio_base()
250 GEM_BUG_ON(!bases[i].base); in __engine_mmio_base()
252 return bases[i].base; in __engine_mmio_base()
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| /drivers/gpu/drm/msm/ |
| D | NOTES | 58 register interface is same, just different bases.)
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| /drivers/media/usb/gspca/ |
| D | Kconfig | 442 Say Y here if you want support for Xirlink C-It bases cameras.
|