1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * IOMMU API for Rockchip
4 *
5 * Module Authors: Simon Xue <xxm@rock-chips.com>
6 * Daniel Kurtz <djkurtz@chromium.org>
7 */
8
9 #include <linux/clk.h>
10 #include <linux/compiler.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/errno.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/iommu.h>
18 #include <linux/iopoll.h>
19 #include <linux/list.h>
20 #include <linux/mm.h>
21 #include <linux/init.h>
22 #include <linux/of.h>
23 #include <linux/of_platform.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/slab.h>
27 #include <linux/spinlock.h>
28
29 /** MMU register offsets */
30 #define RK_MMU_DTE_ADDR 0x00 /* Directory table address */
31 #define RK_MMU_STATUS 0x04
32 #define RK_MMU_COMMAND 0x08
33 #define RK_MMU_PAGE_FAULT_ADDR 0x0C /* IOVA of last page fault */
34 #define RK_MMU_ZAP_ONE_LINE 0x10 /* Shootdown one IOTLB entry */
35 #define RK_MMU_INT_RAWSTAT 0x14 /* IRQ status ignoring mask */
36 #define RK_MMU_INT_CLEAR 0x18 /* Acknowledge and re-arm irq */
37 #define RK_MMU_INT_MASK 0x1C /* IRQ enable */
38 #define RK_MMU_INT_STATUS 0x20 /* IRQ status after masking */
39 #define RK_MMU_AUTO_GATING 0x24
40
41 #define DTE_ADDR_DUMMY 0xCAFEBABE
42
43 #define RK_MMU_POLL_PERIOD_US 100
44 #define RK_MMU_FORCE_RESET_TIMEOUT_US 100000
45 #define RK_MMU_POLL_TIMEOUT_US 1000
46
47 /* RK_MMU_STATUS fields */
48 #define RK_MMU_STATUS_PAGING_ENABLED BIT(0)
49 #define RK_MMU_STATUS_PAGE_FAULT_ACTIVE BIT(1)
50 #define RK_MMU_STATUS_STALL_ACTIVE BIT(2)
51 #define RK_MMU_STATUS_IDLE BIT(3)
52 #define RK_MMU_STATUS_REPLAY_BUFFER_EMPTY BIT(4)
53 #define RK_MMU_STATUS_PAGE_FAULT_IS_WRITE BIT(5)
54 #define RK_MMU_STATUS_STALL_NOT_ACTIVE BIT(31)
55
56 /* RK_MMU_COMMAND command values */
57 #define RK_MMU_CMD_ENABLE_PAGING 0 /* Enable memory translation */
58 #define RK_MMU_CMD_DISABLE_PAGING 1 /* Disable memory translation */
59 #define RK_MMU_CMD_ENABLE_STALL 2 /* Stall paging to allow other cmds */
60 #define RK_MMU_CMD_DISABLE_STALL 3 /* Stop stall re-enables paging */
61 #define RK_MMU_CMD_ZAP_CACHE 4 /* Shoot down entire IOTLB */
62 #define RK_MMU_CMD_PAGE_FAULT_DONE 5 /* Clear page fault */
63 #define RK_MMU_CMD_FORCE_RESET 6 /* Reset all registers */
64
65 /* RK_MMU_INT_* register fields */
66 #define RK_MMU_IRQ_PAGE_FAULT 0x01 /* page fault */
67 #define RK_MMU_IRQ_BUS_ERROR 0x02 /* bus read error */
68 #define RK_MMU_IRQ_MASK (RK_MMU_IRQ_PAGE_FAULT | RK_MMU_IRQ_BUS_ERROR)
69
70 #define NUM_DT_ENTRIES 1024
71 #define NUM_PT_ENTRIES 1024
72
73 #define SPAGE_ORDER 12
74 #define SPAGE_SIZE (1 << SPAGE_ORDER)
75
76 /*
77 * Support mapping any size that fits in one page table:
78 * 4 KiB to 4 MiB
79 */
80 #define RK_IOMMU_PGSIZE_BITMAP 0x007ff000
81
82 struct rk_iommu_domain {
83 struct list_head iommus;
84 u32 *dt; /* page directory table */
85 dma_addr_t dt_dma;
86 spinlock_t iommus_lock; /* lock for iommus list */
87 spinlock_t dt_lock; /* lock for modifying page directory table */
88
89 struct iommu_domain domain;
90 };
91
92 /* list of clocks required by IOMMU */
93 static const char * const rk_iommu_clocks[] = {
94 "aclk", "iface",
95 };
96
97 struct rk_iommu_ops {
98 phys_addr_t (*pt_address)(u32 dte);
99 u32 (*mk_dtentries)(dma_addr_t pt_dma);
100 u32 (*mk_ptentries)(phys_addr_t page, int prot);
101 u64 dma_bit_mask;
102 };
103
104 struct rk_iommu {
105 struct device *dev;
106 void __iomem **bases;
107 int num_mmu;
108 int num_irq;
109 struct clk_bulk_data *clocks;
110 int num_clocks;
111 bool reset_disabled;
112 struct iommu_device iommu;
113 struct list_head node; /* entry in rk_iommu_domain.iommus */
114 struct iommu_domain *domain; /* domain to which iommu is attached */
115 struct iommu_group *group;
116 };
117
118 struct rk_iommudata {
119 struct device_link *link; /* runtime PM link from IOMMU to master */
120 struct rk_iommu *iommu;
121 };
122
123 static struct device *dma_dev;
124 static const struct rk_iommu_ops *rk_ops;
125
rk_table_flush(struct rk_iommu_domain * dom,dma_addr_t dma,unsigned int count)126 static inline void rk_table_flush(struct rk_iommu_domain *dom, dma_addr_t dma,
127 unsigned int count)
128 {
129 size_t size = count * sizeof(u32); /* count of u32 entry */
130
131 dma_sync_single_for_device(dma_dev, dma, size, DMA_TO_DEVICE);
132 }
133
to_rk_domain(struct iommu_domain * dom)134 static struct rk_iommu_domain *to_rk_domain(struct iommu_domain *dom)
135 {
136 return container_of(dom, struct rk_iommu_domain, domain);
137 }
138
139 /*
140 * The Rockchip rk3288 iommu uses a 2-level page table.
141 * The first level is the "Directory Table" (DT).
142 * The DT consists of 1024 4-byte Directory Table Entries (DTEs), each pointing
143 * to a "Page Table".
144 * The second level is the 1024 Page Tables (PT).
145 * Each PT consists of 1024 4-byte Page Table Entries (PTEs), each pointing to
146 * a 4 KB page of physical memory.
147 *
148 * The DT and each PT fits in a single 4 KB page (4-bytes * 1024 entries).
149 * Each iommu device has a MMU_DTE_ADDR register that contains the physical
150 * address of the start of the DT page.
151 *
152 * The structure of the page table is as follows:
153 *
154 * DT
155 * MMU_DTE_ADDR -> +-----+
156 * | |
157 * +-----+ PT
158 * | DTE | -> +-----+
159 * +-----+ | | Memory
160 * | | +-----+ Page
161 * | | | PTE | -> +-----+
162 * +-----+ +-----+ | |
163 * | | | |
164 * | | | |
165 * +-----+ | |
166 * | |
167 * | |
168 * +-----+
169 */
170
171 /*
172 * Each DTE has a PT address and a valid bit:
173 * +---------------------+-----------+-+
174 * | PT address | Reserved |V|
175 * +---------------------+-----------+-+
176 * 31:12 - PT address (PTs always starts on a 4 KB boundary)
177 * 11: 1 - Reserved
178 * 0 - 1 if PT @ PT address is valid
179 */
180 #define RK_DTE_PT_ADDRESS_MASK 0xfffff000
181 #define RK_DTE_PT_VALID BIT(0)
182
rk_dte_pt_address(u32 dte)183 static inline phys_addr_t rk_dte_pt_address(u32 dte)
184 {
185 return (phys_addr_t)dte & RK_DTE_PT_ADDRESS_MASK;
186 }
187
188 /*
189 * In v2:
190 * 31:12 - PT address bit 31:0
191 * 11: 8 - PT address bit 35:32
192 * 7: 4 - PT address bit 39:36
193 * 3: 1 - Reserved
194 * 0 - 1 if PT @ PT address is valid
195 */
196 #define RK_DTE_PT_ADDRESS_MASK_V2 GENMASK_ULL(31, 4)
197 #define DTE_HI_MASK1 GENMASK(11, 8)
198 #define DTE_HI_MASK2 GENMASK(7, 4)
199 #define DTE_HI_SHIFT1 24 /* shift bit 8 to bit 32 */
200 #define DTE_HI_SHIFT2 32 /* shift bit 4 to bit 36 */
201 #define PAGE_DESC_HI_MASK1 GENMASK_ULL(35, 32)
202 #define PAGE_DESC_HI_MASK2 GENMASK_ULL(39, 36)
203
rk_dte_pt_address_v2(u32 dte)204 static inline phys_addr_t rk_dte_pt_address_v2(u32 dte)
205 {
206 u64 dte_v2 = dte;
207
208 dte_v2 = ((dte_v2 & DTE_HI_MASK2) << DTE_HI_SHIFT2) |
209 ((dte_v2 & DTE_HI_MASK1) << DTE_HI_SHIFT1) |
210 (dte_v2 & RK_DTE_PT_ADDRESS_MASK);
211
212 return (phys_addr_t)dte_v2;
213 }
214
rk_dte_is_pt_valid(u32 dte)215 static inline bool rk_dte_is_pt_valid(u32 dte)
216 {
217 return dte & RK_DTE_PT_VALID;
218 }
219
rk_mk_dte(dma_addr_t pt_dma)220 static inline u32 rk_mk_dte(dma_addr_t pt_dma)
221 {
222 return (pt_dma & RK_DTE_PT_ADDRESS_MASK) | RK_DTE_PT_VALID;
223 }
224
rk_mk_dte_v2(dma_addr_t pt_dma)225 static inline u32 rk_mk_dte_v2(dma_addr_t pt_dma)
226 {
227 pt_dma = (pt_dma & RK_DTE_PT_ADDRESS_MASK) |
228 ((pt_dma & PAGE_DESC_HI_MASK1) >> DTE_HI_SHIFT1) |
229 (pt_dma & PAGE_DESC_HI_MASK2) >> DTE_HI_SHIFT2;
230
231 return (pt_dma & RK_DTE_PT_ADDRESS_MASK_V2) | RK_DTE_PT_VALID;
232 }
233
234 /*
235 * Each PTE has a Page address, some flags and a valid bit:
236 * +---------------------+---+-------+-+
237 * | Page address |Rsv| Flags |V|
238 * +---------------------+---+-------+-+
239 * 31:12 - Page address (Pages always start on a 4 KB boundary)
240 * 11: 9 - Reserved
241 * 8: 1 - Flags
242 * 8 - Read allocate - allocate cache space on read misses
243 * 7 - Read cache - enable cache & prefetch of data
244 * 6 - Write buffer - enable delaying writes on their way to memory
245 * 5 - Write allocate - allocate cache space on write misses
246 * 4 - Write cache - different writes can be merged together
247 * 3 - Override cache attributes
248 * if 1, bits 4-8 control cache attributes
249 * if 0, the system bus defaults are used
250 * 2 - Writable
251 * 1 - Readable
252 * 0 - 1 if Page @ Page address is valid
253 */
254 #define RK_PTE_PAGE_ADDRESS_MASK 0xfffff000
255 #define RK_PTE_PAGE_FLAGS_MASK 0x000001fe
256 #define RK_PTE_PAGE_WRITABLE BIT(2)
257 #define RK_PTE_PAGE_READABLE BIT(1)
258 #define RK_PTE_PAGE_VALID BIT(0)
259
rk_pte_is_page_valid(u32 pte)260 static inline bool rk_pte_is_page_valid(u32 pte)
261 {
262 return pte & RK_PTE_PAGE_VALID;
263 }
264
265 /* TODO: set cache flags per prot IOMMU_CACHE */
rk_mk_pte(phys_addr_t page,int prot)266 static u32 rk_mk_pte(phys_addr_t page, int prot)
267 {
268 u32 flags = 0;
269 flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE : 0;
270 flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE : 0;
271 page &= RK_PTE_PAGE_ADDRESS_MASK;
272 return page | flags | RK_PTE_PAGE_VALID;
273 }
274
275 /*
276 * In v2:
277 * 31:12 - Page address bit 31:0
278 * 11: 8 - Page address bit 35:32
279 * 7: 4 - Page address bit 39:36
280 * 3 - Security
281 * 2 - Writable
282 * 1 - Readable
283 * 0 - 1 if Page @ Page address is valid
284 */
285
rk_mk_pte_v2(phys_addr_t page,int prot)286 static u32 rk_mk_pte_v2(phys_addr_t page, int prot)
287 {
288 u32 flags = 0;
289
290 flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE : 0;
291 flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE : 0;
292
293 return rk_mk_dte_v2(page) | flags;
294 }
295
rk_mk_pte_invalid(u32 pte)296 static u32 rk_mk_pte_invalid(u32 pte)
297 {
298 return pte & ~RK_PTE_PAGE_VALID;
299 }
300
301 /*
302 * rk3288 iova (IOMMU Virtual Address) format
303 * 31 22.21 12.11 0
304 * +-----------+-----------+-------------+
305 * | DTE index | PTE index | Page offset |
306 * +-----------+-----------+-------------+
307 * 31:22 - DTE index - index of DTE in DT
308 * 21:12 - PTE index - index of PTE in PT @ DTE.pt_address
309 * 11: 0 - Page offset - offset into page @ PTE.page_address
310 */
311 #define RK_IOVA_DTE_MASK 0xffc00000
312 #define RK_IOVA_DTE_SHIFT 22
313 #define RK_IOVA_PTE_MASK 0x003ff000
314 #define RK_IOVA_PTE_SHIFT 12
315 #define RK_IOVA_PAGE_MASK 0x00000fff
316 #define RK_IOVA_PAGE_SHIFT 0
317
rk_iova_dte_index(dma_addr_t iova)318 static u32 rk_iova_dte_index(dma_addr_t iova)
319 {
320 return (u32)(iova & RK_IOVA_DTE_MASK) >> RK_IOVA_DTE_SHIFT;
321 }
322
rk_iova_pte_index(dma_addr_t iova)323 static u32 rk_iova_pte_index(dma_addr_t iova)
324 {
325 return (u32)(iova & RK_IOVA_PTE_MASK) >> RK_IOVA_PTE_SHIFT;
326 }
327
rk_iova_page_offset(dma_addr_t iova)328 static u32 rk_iova_page_offset(dma_addr_t iova)
329 {
330 return (u32)(iova & RK_IOVA_PAGE_MASK) >> RK_IOVA_PAGE_SHIFT;
331 }
332
rk_iommu_read(void __iomem * base,u32 offset)333 static u32 rk_iommu_read(void __iomem *base, u32 offset)
334 {
335 return readl(base + offset);
336 }
337
rk_iommu_write(void __iomem * base,u32 offset,u32 value)338 static void rk_iommu_write(void __iomem *base, u32 offset, u32 value)
339 {
340 writel(value, base + offset);
341 }
342
rk_iommu_command(struct rk_iommu * iommu,u32 command)343 static void rk_iommu_command(struct rk_iommu *iommu, u32 command)
344 {
345 int i;
346
347 for (i = 0; i < iommu->num_mmu; i++)
348 writel(command, iommu->bases[i] + RK_MMU_COMMAND);
349 }
350
rk_iommu_base_command(void __iomem * base,u32 command)351 static void rk_iommu_base_command(void __iomem *base, u32 command)
352 {
353 writel(command, base + RK_MMU_COMMAND);
354 }
rk_iommu_zap_lines(struct rk_iommu * iommu,dma_addr_t iova_start,size_t size)355 static void rk_iommu_zap_lines(struct rk_iommu *iommu, dma_addr_t iova_start,
356 size_t size)
357 {
358 int i;
359 dma_addr_t iova_end = iova_start + size;
360 /*
361 * TODO(djkurtz): Figure out when it is more efficient to shootdown the
362 * entire iotlb rather than iterate over individual iovas.
363 */
364 for (i = 0; i < iommu->num_mmu; i++) {
365 dma_addr_t iova;
366
367 for (iova = iova_start; iova < iova_end; iova += SPAGE_SIZE)
368 rk_iommu_write(iommu->bases[i], RK_MMU_ZAP_ONE_LINE, iova);
369 }
370 }
371
rk_iommu_is_stall_active(struct rk_iommu * iommu)372 static bool rk_iommu_is_stall_active(struct rk_iommu *iommu)
373 {
374 bool active = true;
375 int i;
376
377 for (i = 0; i < iommu->num_mmu; i++)
378 active &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) &
379 RK_MMU_STATUS_STALL_ACTIVE);
380
381 return active;
382 }
383
rk_iommu_is_paging_enabled(struct rk_iommu * iommu)384 static bool rk_iommu_is_paging_enabled(struct rk_iommu *iommu)
385 {
386 bool enable = true;
387 int i;
388
389 for (i = 0; i < iommu->num_mmu; i++)
390 enable &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) &
391 RK_MMU_STATUS_PAGING_ENABLED);
392
393 return enable;
394 }
395
rk_iommu_is_reset_done(struct rk_iommu * iommu)396 static bool rk_iommu_is_reset_done(struct rk_iommu *iommu)
397 {
398 bool done = true;
399 int i;
400
401 for (i = 0; i < iommu->num_mmu; i++)
402 done &= rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR) == 0;
403
404 return done;
405 }
406
rk_iommu_enable_stall(struct rk_iommu * iommu)407 static int rk_iommu_enable_stall(struct rk_iommu *iommu)
408 {
409 int ret, i;
410 bool val;
411
412 if (rk_iommu_is_stall_active(iommu))
413 return 0;
414
415 /* Stall can only be enabled if paging is enabled */
416 if (!rk_iommu_is_paging_enabled(iommu))
417 return 0;
418
419 rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_STALL);
420
421 ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val,
422 val, RK_MMU_POLL_PERIOD_US,
423 RK_MMU_POLL_TIMEOUT_US);
424 if (ret)
425 for (i = 0; i < iommu->num_mmu; i++)
426 dev_err(iommu->dev, "Enable stall request timed out, status: %#08x\n",
427 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
428
429 return ret;
430 }
431
rk_iommu_disable_stall(struct rk_iommu * iommu)432 static int rk_iommu_disable_stall(struct rk_iommu *iommu)
433 {
434 int ret, i;
435 bool val;
436
437 if (!rk_iommu_is_stall_active(iommu))
438 return 0;
439
440 rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_STALL);
441
442 ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val,
443 !val, RK_MMU_POLL_PERIOD_US,
444 RK_MMU_POLL_TIMEOUT_US);
445 if (ret)
446 for (i = 0; i < iommu->num_mmu; i++)
447 dev_err(iommu->dev, "Disable stall request timed out, status: %#08x\n",
448 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
449
450 return ret;
451 }
452
rk_iommu_enable_paging(struct rk_iommu * iommu)453 static int rk_iommu_enable_paging(struct rk_iommu *iommu)
454 {
455 int ret, i;
456 bool val;
457
458 if (rk_iommu_is_paging_enabled(iommu))
459 return 0;
460
461 rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_PAGING);
462
463 ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val,
464 val, RK_MMU_POLL_PERIOD_US,
465 RK_MMU_POLL_TIMEOUT_US);
466 if (ret)
467 for (i = 0; i < iommu->num_mmu; i++)
468 dev_err(iommu->dev, "Enable paging request timed out, status: %#08x\n",
469 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
470
471 return ret;
472 }
473
rk_iommu_disable_paging(struct rk_iommu * iommu)474 static int rk_iommu_disable_paging(struct rk_iommu *iommu)
475 {
476 int ret, i;
477 bool val;
478
479 if (!rk_iommu_is_paging_enabled(iommu))
480 return 0;
481
482 rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_PAGING);
483
484 ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val,
485 !val, RK_MMU_POLL_PERIOD_US,
486 RK_MMU_POLL_TIMEOUT_US);
487 if (ret)
488 for (i = 0; i < iommu->num_mmu; i++)
489 dev_err(iommu->dev, "Disable paging request timed out, status: %#08x\n",
490 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
491
492 return ret;
493 }
494
rk_iommu_force_reset(struct rk_iommu * iommu)495 static int rk_iommu_force_reset(struct rk_iommu *iommu)
496 {
497 int ret, i;
498 u32 dte_addr;
499 bool val;
500
501 if (iommu->reset_disabled)
502 return 0;
503
504 /*
505 * Check if register DTE_ADDR is working by writing DTE_ADDR_DUMMY
506 * and verifying that upper 5 (v1) or 7 (v2) nybbles are read back.
507 */
508 for (i = 0; i < iommu->num_mmu; i++) {
509 dte_addr = rk_ops->pt_address(DTE_ADDR_DUMMY);
510 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, dte_addr);
511
512 if (dte_addr != rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR)) {
513 dev_err(iommu->dev, "Error during raw reset. MMU_DTE_ADDR is not functioning\n");
514 return -EFAULT;
515 }
516 }
517
518 rk_iommu_command(iommu, RK_MMU_CMD_FORCE_RESET);
519
520 ret = readx_poll_timeout(rk_iommu_is_reset_done, iommu, val,
521 val, RK_MMU_FORCE_RESET_TIMEOUT_US,
522 RK_MMU_POLL_TIMEOUT_US);
523 if (ret) {
524 dev_err(iommu->dev, "FORCE_RESET command timed out\n");
525 return ret;
526 }
527
528 return 0;
529 }
530
log_iova(struct rk_iommu * iommu,int index,dma_addr_t iova)531 static void log_iova(struct rk_iommu *iommu, int index, dma_addr_t iova)
532 {
533 void __iomem *base = iommu->bases[index];
534 u32 dte_index, pte_index, page_offset;
535 u32 mmu_dte_addr;
536 phys_addr_t mmu_dte_addr_phys, dte_addr_phys;
537 u32 *dte_addr;
538 u32 dte;
539 phys_addr_t pte_addr_phys = 0;
540 u32 *pte_addr = NULL;
541 u32 pte = 0;
542 phys_addr_t page_addr_phys = 0;
543 u32 page_flags = 0;
544
545 dte_index = rk_iova_dte_index(iova);
546 pte_index = rk_iova_pte_index(iova);
547 page_offset = rk_iova_page_offset(iova);
548
549 mmu_dte_addr = rk_iommu_read(base, RK_MMU_DTE_ADDR);
550 mmu_dte_addr_phys = rk_ops->pt_address(mmu_dte_addr);
551
552 dte_addr_phys = mmu_dte_addr_phys + (4 * dte_index);
553 dte_addr = phys_to_virt(dte_addr_phys);
554 dte = *dte_addr;
555
556 if (!rk_dte_is_pt_valid(dte))
557 goto print_it;
558
559 pte_addr_phys = rk_ops->pt_address(dte) + (pte_index * 4);
560 pte_addr = phys_to_virt(pte_addr_phys);
561 pte = *pte_addr;
562
563 if (!rk_pte_is_page_valid(pte))
564 goto print_it;
565
566 page_addr_phys = rk_ops->pt_address(pte) + page_offset;
567 page_flags = pte & RK_PTE_PAGE_FLAGS_MASK;
568
569 print_it:
570 dev_err(iommu->dev, "iova = %pad: dte_index: %#03x pte_index: %#03x page_offset: %#03x\n",
571 &iova, dte_index, pte_index, page_offset);
572 dev_err(iommu->dev, "mmu_dte_addr: %pa dte@%pa: %#08x valid: %u pte@%pa: %#08x valid: %u page@%pa flags: %#03x\n",
573 &mmu_dte_addr_phys, &dte_addr_phys, dte,
574 rk_dte_is_pt_valid(dte), &pte_addr_phys, pte,
575 rk_pte_is_page_valid(pte), &page_addr_phys, page_flags);
576 }
577
rk_iommu_irq(int irq,void * dev_id)578 static irqreturn_t rk_iommu_irq(int irq, void *dev_id)
579 {
580 struct rk_iommu *iommu = dev_id;
581 u32 status;
582 u32 int_status;
583 dma_addr_t iova;
584 irqreturn_t ret = IRQ_NONE;
585 int i, err;
586
587 err = pm_runtime_get_if_in_use(iommu->dev);
588 if (!err || WARN_ON_ONCE(err < 0))
589 return ret;
590
591 if (WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks)))
592 goto out;
593
594 for (i = 0; i < iommu->num_mmu; i++) {
595 int_status = rk_iommu_read(iommu->bases[i], RK_MMU_INT_STATUS);
596 if (int_status == 0)
597 continue;
598
599 ret = IRQ_HANDLED;
600 iova = rk_iommu_read(iommu->bases[i], RK_MMU_PAGE_FAULT_ADDR);
601
602 if (int_status & RK_MMU_IRQ_PAGE_FAULT) {
603 int flags;
604
605 status = rk_iommu_read(iommu->bases[i], RK_MMU_STATUS);
606 flags = (status & RK_MMU_STATUS_PAGE_FAULT_IS_WRITE) ?
607 IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
608
609 dev_err(iommu->dev, "Page fault at %pad of type %s\n",
610 &iova,
611 (flags == IOMMU_FAULT_WRITE) ? "write" : "read");
612
613 log_iova(iommu, i, iova);
614
615 /*
616 * Report page fault to any installed handlers.
617 * Ignore the return code, though, since we always zap cache
618 * and clear the page fault anyway.
619 */
620 if (iommu->domain)
621 report_iommu_fault(iommu->domain, iommu->dev, iova,
622 flags);
623 else
624 dev_err(iommu->dev, "Page fault while iommu not attached to domain?\n");
625
626 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE);
627 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_PAGE_FAULT_DONE);
628 }
629
630 if (int_status & RK_MMU_IRQ_BUS_ERROR)
631 dev_err(iommu->dev, "BUS_ERROR occurred at %pad\n", &iova);
632
633 if (int_status & ~RK_MMU_IRQ_MASK)
634 dev_err(iommu->dev, "unexpected int_status: %#08x\n",
635 int_status);
636
637 rk_iommu_write(iommu->bases[i], RK_MMU_INT_CLEAR, int_status);
638 }
639
640 clk_bulk_disable(iommu->num_clocks, iommu->clocks);
641
642 out:
643 pm_runtime_put(iommu->dev);
644 return ret;
645 }
646
rk_iommu_iova_to_phys(struct iommu_domain * domain,dma_addr_t iova)647 static phys_addr_t rk_iommu_iova_to_phys(struct iommu_domain *domain,
648 dma_addr_t iova)
649 {
650 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
651 unsigned long flags;
652 phys_addr_t pt_phys, phys = 0;
653 u32 dte, pte;
654 u32 *page_table;
655
656 spin_lock_irqsave(&rk_domain->dt_lock, flags);
657
658 dte = rk_domain->dt[rk_iova_dte_index(iova)];
659 if (!rk_dte_is_pt_valid(dte))
660 goto out;
661
662 pt_phys = rk_ops->pt_address(dte);
663 page_table = (u32 *)phys_to_virt(pt_phys);
664 pte = page_table[rk_iova_pte_index(iova)];
665 if (!rk_pte_is_page_valid(pte))
666 goto out;
667
668 phys = rk_ops->pt_address(pte) + rk_iova_page_offset(iova);
669 out:
670 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
671
672 return phys;
673 }
674
rk_iommu_zap_iova(struct rk_iommu_domain * rk_domain,dma_addr_t iova,size_t size)675 static void rk_iommu_zap_iova(struct rk_iommu_domain *rk_domain,
676 dma_addr_t iova, size_t size)
677 {
678 struct list_head *pos;
679 unsigned long flags;
680
681 /* shootdown these iova from all iommus using this domain */
682 spin_lock_irqsave(&rk_domain->iommus_lock, flags);
683 list_for_each(pos, &rk_domain->iommus) {
684 struct rk_iommu *iommu;
685 int ret;
686
687 iommu = list_entry(pos, struct rk_iommu, node);
688
689 /* Only zap TLBs of IOMMUs that are powered on. */
690 ret = pm_runtime_get_if_in_use(iommu->dev);
691 if (WARN_ON_ONCE(ret < 0))
692 continue;
693 if (ret) {
694 WARN_ON(clk_bulk_enable(iommu->num_clocks,
695 iommu->clocks));
696 rk_iommu_zap_lines(iommu, iova, size);
697 clk_bulk_disable(iommu->num_clocks, iommu->clocks);
698 pm_runtime_put(iommu->dev);
699 }
700 }
701 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags);
702 }
703
rk_iommu_zap_iova_first_last(struct rk_iommu_domain * rk_domain,dma_addr_t iova,size_t size)704 static void rk_iommu_zap_iova_first_last(struct rk_iommu_domain *rk_domain,
705 dma_addr_t iova, size_t size)
706 {
707 rk_iommu_zap_iova(rk_domain, iova, SPAGE_SIZE);
708 if (size > SPAGE_SIZE)
709 rk_iommu_zap_iova(rk_domain, iova + size - SPAGE_SIZE,
710 SPAGE_SIZE);
711 }
712
rk_dte_get_page_table(struct rk_iommu_domain * rk_domain,dma_addr_t iova)713 static u32 *rk_dte_get_page_table(struct rk_iommu_domain *rk_domain,
714 dma_addr_t iova)
715 {
716 u32 *page_table, *dte_addr;
717 u32 dte_index, dte;
718 phys_addr_t pt_phys;
719 dma_addr_t pt_dma;
720
721 assert_spin_locked(&rk_domain->dt_lock);
722
723 dte_index = rk_iova_dte_index(iova);
724 dte_addr = &rk_domain->dt[dte_index];
725 dte = *dte_addr;
726 if (rk_dte_is_pt_valid(dte))
727 goto done;
728
729 page_table = (u32 *)get_zeroed_page(GFP_ATOMIC | GFP_DMA32);
730 if (!page_table)
731 return ERR_PTR(-ENOMEM);
732
733 pt_dma = dma_map_single(dma_dev, page_table, SPAGE_SIZE, DMA_TO_DEVICE);
734 if (dma_mapping_error(dma_dev, pt_dma)) {
735 dev_err(dma_dev, "DMA mapping error while allocating page table\n");
736 free_page((unsigned long)page_table);
737 return ERR_PTR(-ENOMEM);
738 }
739
740 dte = rk_ops->mk_dtentries(pt_dma);
741 *dte_addr = dte;
742
743 rk_table_flush(rk_domain,
744 rk_domain->dt_dma + dte_index * sizeof(u32), 1);
745 done:
746 pt_phys = rk_ops->pt_address(dte);
747 return (u32 *)phys_to_virt(pt_phys);
748 }
749
rk_iommu_unmap_iova(struct rk_iommu_domain * rk_domain,u32 * pte_addr,dma_addr_t pte_dma,size_t size)750 static size_t rk_iommu_unmap_iova(struct rk_iommu_domain *rk_domain,
751 u32 *pte_addr, dma_addr_t pte_dma,
752 size_t size)
753 {
754 unsigned int pte_count;
755 unsigned int pte_total = size / SPAGE_SIZE;
756
757 assert_spin_locked(&rk_domain->dt_lock);
758
759 for (pte_count = 0; pte_count < pte_total; pte_count++) {
760 u32 pte = pte_addr[pte_count];
761 if (!rk_pte_is_page_valid(pte))
762 break;
763
764 pte_addr[pte_count] = rk_mk_pte_invalid(pte);
765 }
766
767 rk_table_flush(rk_domain, pte_dma, pte_count);
768
769 return pte_count * SPAGE_SIZE;
770 }
771
rk_iommu_map_iova(struct rk_iommu_domain * rk_domain,u32 * pte_addr,dma_addr_t pte_dma,dma_addr_t iova,phys_addr_t paddr,size_t size,int prot)772 static int rk_iommu_map_iova(struct rk_iommu_domain *rk_domain, u32 *pte_addr,
773 dma_addr_t pte_dma, dma_addr_t iova,
774 phys_addr_t paddr, size_t size, int prot)
775 {
776 unsigned int pte_count;
777 unsigned int pte_total = size / SPAGE_SIZE;
778 phys_addr_t page_phys;
779
780 assert_spin_locked(&rk_domain->dt_lock);
781
782 for (pte_count = 0; pte_count < pte_total; pte_count++) {
783 u32 pte = pte_addr[pte_count];
784
785 if (rk_pte_is_page_valid(pte))
786 goto unwind;
787
788 pte_addr[pte_count] = rk_ops->mk_ptentries(paddr, prot);
789
790 paddr += SPAGE_SIZE;
791 }
792
793 rk_table_flush(rk_domain, pte_dma, pte_total);
794
795 /*
796 * Zap the first and last iova to evict from iotlb any previously
797 * mapped cachelines holding stale values for its dte and pte.
798 * We only zap the first and last iova, since only they could have
799 * dte or pte shared with an existing mapping.
800 */
801 rk_iommu_zap_iova_first_last(rk_domain, iova, size);
802
803 return 0;
804 unwind:
805 /* Unmap the range of iovas that we just mapped */
806 rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma,
807 pte_count * SPAGE_SIZE);
808
809 iova += pte_count * SPAGE_SIZE;
810 page_phys = rk_ops->pt_address(pte_addr[pte_count]);
811 pr_err("iova: %pad already mapped to %pa cannot remap to phys: %pa prot: %#x\n",
812 &iova, &page_phys, &paddr, prot);
813
814 return -EADDRINUSE;
815 }
816
rk_iommu_map(struct iommu_domain * domain,unsigned long _iova,phys_addr_t paddr,size_t size,int prot,gfp_t gfp)817 static int rk_iommu_map(struct iommu_domain *domain, unsigned long _iova,
818 phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
819 {
820 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
821 unsigned long flags;
822 dma_addr_t pte_dma, iova = (dma_addr_t)_iova;
823 u32 *page_table, *pte_addr;
824 u32 dte_index, pte_index;
825 int ret;
826
827 spin_lock_irqsave(&rk_domain->dt_lock, flags);
828
829 /*
830 * pgsize_bitmap specifies iova sizes that fit in one page table
831 * (1024 4-KiB pages = 4 MiB).
832 * So, size will always be 4096 <= size <= 4194304.
833 * Since iommu_map() guarantees that both iova and size will be
834 * aligned, we will always only be mapping from a single dte here.
835 */
836 page_table = rk_dte_get_page_table(rk_domain, iova);
837 if (IS_ERR(page_table)) {
838 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
839 return PTR_ERR(page_table);
840 }
841
842 dte_index = rk_domain->dt[rk_iova_dte_index(iova)];
843 pte_index = rk_iova_pte_index(iova);
844 pte_addr = &page_table[pte_index];
845
846 pte_dma = rk_ops->pt_address(dte_index) + pte_index * sizeof(u32);
847 ret = rk_iommu_map_iova(rk_domain, pte_addr, pte_dma, iova,
848 paddr, size, prot);
849
850 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
851
852 return ret;
853 }
854
rk_iommu_unmap(struct iommu_domain * domain,unsigned long _iova,size_t size,struct iommu_iotlb_gather * gather)855 static size_t rk_iommu_unmap(struct iommu_domain *domain, unsigned long _iova,
856 size_t size, struct iommu_iotlb_gather *gather)
857 {
858 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
859 unsigned long flags;
860 dma_addr_t pte_dma, iova = (dma_addr_t)_iova;
861 phys_addr_t pt_phys;
862 u32 dte;
863 u32 *pte_addr;
864 size_t unmap_size;
865
866 spin_lock_irqsave(&rk_domain->dt_lock, flags);
867
868 /*
869 * pgsize_bitmap specifies iova sizes that fit in one page table
870 * (1024 4-KiB pages = 4 MiB).
871 * So, size will always be 4096 <= size <= 4194304.
872 * Since iommu_unmap() guarantees that both iova and size will be
873 * aligned, we will always only be unmapping from a single dte here.
874 */
875 dte = rk_domain->dt[rk_iova_dte_index(iova)];
876 /* Just return 0 if iova is unmapped */
877 if (!rk_dte_is_pt_valid(dte)) {
878 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
879 return 0;
880 }
881
882 pt_phys = rk_ops->pt_address(dte);
883 pte_addr = (u32 *)phys_to_virt(pt_phys) + rk_iova_pte_index(iova);
884 pte_dma = pt_phys + rk_iova_pte_index(iova) * sizeof(u32);
885 unmap_size = rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma, size);
886
887 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
888
889 /* Shootdown iotlb entries for iova range that was just unmapped */
890 rk_iommu_zap_iova(rk_domain, iova, unmap_size);
891
892 return unmap_size;
893 }
894
rk_iommu_from_dev(struct device * dev)895 static struct rk_iommu *rk_iommu_from_dev(struct device *dev)
896 {
897 struct rk_iommudata *data = dev_iommu_priv_get(dev);
898
899 return data ? data->iommu : NULL;
900 }
901
902 /* Must be called with iommu powered on and attached */
rk_iommu_disable(struct rk_iommu * iommu)903 static void rk_iommu_disable(struct rk_iommu *iommu)
904 {
905 int i;
906
907 /* Ignore error while disabling, just keep going */
908 WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks));
909 rk_iommu_enable_stall(iommu);
910 rk_iommu_disable_paging(iommu);
911 for (i = 0; i < iommu->num_mmu; i++) {
912 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, 0);
913 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, 0);
914 }
915 rk_iommu_disable_stall(iommu);
916 clk_bulk_disable(iommu->num_clocks, iommu->clocks);
917 }
918
919 /* Must be called with iommu powered on and attached */
rk_iommu_enable(struct rk_iommu * iommu)920 static int rk_iommu_enable(struct rk_iommu *iommu)
921 {
922 struct iommu_domain *domain = iommu->domain;
923 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
924 int ret, i;
925
926 ret = clk_bulk_enable(iommu->num_clocks, iommu->clocks);
927 if (ret)
928 return ret;
929
930 ret = rk_iommu_enable_stall(iommu);
931 if (ret)
932 goto out_disable_clocks;
933
934 ret = rk_iommu_force_reset(iommu);
935 if (ret)
936 goto out_disable_stall;
937
938 for (i = 0; i < iommu->num_mmu; i++) {
939 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR,
940 rk_ops->mk_dtentries(rk_domain->dt_dma));
941 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE);
942 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, RK_MMU_IRQ_MASK);
943 }
944
945 ret = rk_iommu_enable_paging(iommu);
946
947 out_disable_stall:
948 rk_iommu_disable_stall(iommu);
949 out_disable_clocks:
950 clk_bulk_disable(iommu->num_clocks, iommu->clocks);
951 return ret;
952 }
953
rk_iommu_detach_device(struct iommu_domain * domain,struct device * dev)954 static void rk_iommu_detach_device(struct iommu_domain *domain,
955 struct device *dev)
956 {
957 struct rk_iommu *iommu;
958 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
959 unsigned long flags;
960 int ret;
961
962 /* Allow 'virtual devices' (eg drm) to detach from domain */
963 iommu = rk_iommu_from_dev(dev);
964 if (!iommu)
965 return;
966
967 dev_dbg(dev, "Detaching from iommu domain\n");
968
969 /* iommu already detached */
970 if (iommu->domain != domain)
971 return;
972
973 iommu->domain = NULL;
974
975 spin_lock_irqsave(&rk_domain->iommus_lock, flags);
976 list_del_init(&iommu->node);
977 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags);
978
979 ret = pm_runtime_get_if_in_use(iommu->dev);
980 WARN_ON_ONCE(ret < 0);
981 if (ret > 0) {
982 rk_iommu_disable(iommu);
983 pm_runtime_put(iommu->dev);
984 }
985 }
986
rk_iommu_attach_device(struct iommu_domain * domain,struct device * dev)987 static int rk_iommu_attach_device(struct iommu_domain *domain,
988 struct device *dev)
989 {
990 struct rk_iommu *iommu;
991 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
992 unsigned long flags;
993 int ret;
994
995 /*
996 * Allow 'virtual devices' (e.g., drm) to attach to domain.
997 * Such a device does not belong to an iommu group.
998 */
999 iommu = rk_iommu_from_dev(dev);
1000 if (!iommu)
1001 return 0;
1002
1003 dev_dbg(dev, "Attaching to iommu domain\n");
1004
1005 /* iommu already attached */
1006 if (iommu->domain == domain)
1007 return 0;
1008
1009 if (iommu->domain)
1010 rk_iommu_detach_device(iommu->domain, dev);
1011
1012 iommu->domain = domain;
1013
1014 spin_lock_irqsave(&rk_domain->iommus_lock, flags);
1015 list_add_tail(&iommu->node, &rk_domain->iommus);
1016 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags);
1017
1018 ret = pm_runtime_get_if_in_use(iommu->dev);
1019 if (!ret || WARN_ON_ONCE(ret < 0))
1020 return 0;
1021
1022 ret = rk_iommu_enable(iommu);
1023 if (ret)
1024 rk_iommu_detach_device(iommu->domain, dev);
1025
1026 pm_runtime_put(iommu->dev);
1027
1028 return ret;
1029 }
1030
rk_iommu_domain_alloc(unsigned type)1031 static struct iommu_domain *rk_iommu_domain_alloc(unsigned type)
1032 {
1033 struct rk_iommu_domain *rk_domain;
1034
1035 if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA)
1036 return NULL;
1037
1038 if (!dma_dev)
1039 return NULL;
1040
1041 rk_domain = kzalloc(sizeof(*rk_domain), GFP_KERNEL);
1042 if (!rk_domain)
1043 return NULL;
1044
1045 /*
1046 * rk32xx iommus use a 2 level pagetable.
1047 * Each level1 (dt) and level2 (pt) table has 1024 4-byte entries.
1048 * Allocate one 4 KiB page for each table.
1049 */
1050 rk_domain->dt = (u32 *)get_zeroed_page(GFP_KERNEL | GFP_DMA32);
1051 if (!rk_domain->dt)
1052 goto err_free_domain;
1053
1054 rk_domain->dt_dma = dma_map_single(dma_dev, rk_domain->dt,
1055 SPAGE_SIZE, DMA_TO_DEVICE);
1056 if (dma_mapping_error(dma_dev, rk_domain->dt_dma)) {
1057 dev_err(dma_dev, "DMA map error for DT\n");
1058 goto err_free_dt;
1059 }
1060
1061 spin_lock_init(&rk_domain->iommus_lock);
1062 spin_lock_init(&rk_domain->dt_lock);
1063 INIT_LIST_HEAD(&rk_domain->iommus);
1064
1065 rk_domain->domain.geometry.aperture_start = 0;
1066 rk_domain->domain.geometry.aperture_end = DMA_BIT_MASK(32);
1067 rk_domain->domain.geometry.force_aperture = true;
1068
1069 return &rk_domain->domain;
1070
1071 err_free_dt:
1072 free_page((unsigned long)rk_domain->dt);
1073 err_free_domain:
1074 kfree(rk_domain);
1075
1076 return NULL;
1077 }
1078
rk_iommu_domain_free(struct iommu_domain * domain)1079 static void rk_iommu_domain_free(struct iommu_domain *domain)
1080 {
1081 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
1082 int i;
1083
1084 WARN_ON(!list_empty(&rk_domain->iommus));
1085
1086 for (i = 0; i < NUM_DT_ENTRIES; i++) {
1087 u32 dte = rk_domain->dt[i];
1088 if (rk_dte_is_pt_valid(dte)) {
1089 phys_addr_t pt_phys = rk_ops->pt_address(dte);
1090 u32 *page_table = phys_to_virt(pt_phys);
1091 dma_unmap_single(dma_dev, pt_phys,
1092 SPAGE_SIZE, DMA_TO_DEVICE);
1093 free_page((unsigned long)page_table);
1094 }
1095 }
1096
1097 dma_unmap_single(dma_dev, rk_domain->dt_dma,
1098 SPAGE_SIZE, DMA_TO_DEVICE);
1099 free_page((unsigned long)rk_domain->dt);
1100
1101 kfree(rk_domain);
1102 }
1103
rk_iommu_probe_device(struct device * dev)1104 static struct iommu_device *rk_iommu_probe_device(struct device *dev)
1105 {
1106 struct rk_iommudata *data;
1107 struct rk_iommu *iommu;
1108
1109 data = dev_iommu_priv_get(dev);
1110 if (!data)
1111 return ERR_PTR(-ENODEV);
1112
1113 iommu = rk_iommu_from_dev(dev);
1114
1115 data->link = device_link_add(dev, iommu->dev,
1116 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME);
1117
1118 return &iommu->iommu;
1119 }
1120
rk_iommu_release_device(struct device * dev)1121 static void rk_iommu_release_device(struct device *dev)
1122 {
1123 struct rk_iommudata *data = dev_iommu_priv_get(dev);
1124
1125 device_link_del(data->link);
1126 }
1127
rk_iommu_device_group(struct device * dev)1128 static struct iommu_group *rk_iommu_device_group(struct device *dev)
1129 {
1130 struct rk_iommu *iommu;
1131
1132 iommu = rk_iommu_from_dev(dev);
1133
1134 return iommu_group_ref_get(iommu->group);
1135 }
1136
rk_iommu_of_xlate(struct device * dev,struct of_phandle_args * args)1137 static int rk_iommu_of_xlate(struct device *dev,
1138 struct of_phandle_args *args)
1139 {
1140 struct platform_device *iommu_dev;
1141 struct rk_iommudata *data;
1142
1143 data = devm_kzalloc(dma_dev, sizeof(*data), GFP_KERNEL);
1144 if (!data)
1145 return -ENOMEM;
1146
1147 iommu_dev = of_find_device_by_node(args->np);
1148
1149 data->iommu = platform_get_drvdata(iommu_dev);
1150 dev_iommu_priv_set(dev, data);
1151
1152 platform_device_put(iommu_dev);
1153
1154 return 0;
1155 }
1156
1157 static const struct iommu_ops rk_iommu_ops = {
1158 .domain_alloc = rk_iommu_domain_alloc,
1159 .domain_free = rk_iommu_domain_free,
1160 .attach_dev = rk_iommu_attach_device,
1161 .detach_dev = rk_iommu_detach_device,
1162 .map = rk_iommu_map,
1163 .unmap = rk_iommu_unmap,
1164 .probe_device = rk_iommu_probe_device,
1165 .release_device = rk_iommu_release_device,
1166 .iova_to_phys = rk_iommu_iova_to_phys,
1167 .device_group = rk_iommu_device_group,
1168 .pgsize_bitmap = RK_IOMMU_PGSIZE_BITMAP,
1169 .of_xlate = rk_iommu_of_xlate,
1170 };
1171
rk_iommu_probe(struct platform_device * pdev)1172 static int rk_iommu_probe(struct platform_device *pdev)
1173 {
1174 struct device *dev = &pdev->dev;
1175 struct rk_iommu *iommu;
1176 struct resource *res;
1177 const struct rk_iommu_ops *ops;
1178 int num_res = pdev->num_resources;
1179 int err, i;
1180
1181 iommu = devm_kzalloc(dev, sizeof(*iommu), GFP_KERNEL);
1182 if (!iommu)
1183 return -ENOMEM;
1184
1185 platform_set_drvdata(pdev, iommu);
1186 iommu->dev = dev;
1187 iommu->num_mmu = 0;
1188
1189 ops = of_device_get_match_data(dev);
1190 if (!rk_ops)
1191 rk_ops = ops;
1192
1193 /*
1194 * That should not happen unless different versions of the
1195 * hardware block are embedded the same SoC
1196 */
1197 if (WARN_ON(rk_ops != ops))
1198 return -EINVAL;
1199
1200 iommu->bases = devm_kcalloc(dev, num_res, sizeof(*iommu->bases),
1201 GFP_KERNEL);
1202 if (!iommu->bases)
1203 return -ENOMEM;
1204
1205 for (i = 0; i < num_res; i++) {
1206 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1207 if (!res)
1208 continue;
1209 iommu->bases[i] = devm_ioremap_resource(&pdev->dev, res);
1210 if (IS_ERR(iommu->bases[i]))
1211 continue;
1212 iommu->num_mmu++;
1213 }
1214 if (iommu->num_mmu == 0)
1215 return PTR_ERR(iommu->bases[0]);
1216
1217 iommu->num_irq = platform_irq_count(pdev);
1218 if (iommu->num_irq < 0)
1219 return iommu->num_irq;
1220
1221 iommu->reset_disabled = device_property_read_bool(dev,
1222 "rockchip,disable-mmu-reset");
1223
1224 iommu->num_clocks = ARRAY_SIZE(rk_iommu_clocks);
1225 iommu->clocks = devm_kcalloc(iommu->dev, iommu->num_clocks,
1226 sizeof(*iommu->clocks), GFP_KERNEL);
1227 if (!iommu->clocks)
1228 return -ENOMEM;
1229
1230 for (i = 0; i < iommu->num_clocks; ++i)
1231 iommu->clocks[i].id = rk_iommu_clocks[i];
1232
1233 /*
1234 * iommu clocks should be present for all new devices and devicetrees
1235 * but there are older devicetrees without clocks out in the wild.
1236 * So clocks as optional for the time being.
1237 */
1238 err = devm_clk_bulk_get(iommu->dev, iommu->num_clocks, iommu->clocks);
1239 if (err == -ENOENT)
1240 iommu->num_clocks = 0;
1241 else if (err)
1242 return err;
1243
1244 err = clk_bulk_prepare(iommu->num_clocks, iommu->clocks);
1245 if (err)
1246 return err;
1247
1248 iommu->group = iommu_group_alloc();
1249 if (IS_ERR(iommu->group)) {
1250 err = PTR_ERR(iommu->group);
1251 goto err_unprepare_clocks;
1252 }
1253
1254 err = iommu_device_sysfs_add(&iommu->iommu, dev, NULL, dev_name(dev));
1255 if (err)
1256 goto err_put_group;
1257
1258 err = iommu_device_register(&iommu->iommu, &rk_iommu_ops, dev);
1259 if (err)
1260 goto err_remove_sysfs;
1261
1262 /*
1263 * Use the first registered IOMMU device for domain to use with DMA
1264 * API, since a domain might not physically correspond to a single
1265 * IOMMU device..
1266 */
1267 if (!dma_dev)
1268 dma_dev = &pdev->dev;
1269
1270 bus_set_iommu(&platform_bus_type, &rk_iommu_ops);
1271
1272 pm_runtime_enable(dev);
1273
1274 for (i = 0; i < iommu->num_irq; i++) {
1275 int irq = platform_get_irq(pdev, i);
1276
1277 if (irq < 0) {
1278 err = irq;
1279 goto err_pm_disable;
1280 }
1281
1282 err = devm_request_irq(iommu->dev, irq, rk_iommu_irq,
1283 IRQF_SHARED, dev_name(dev), iommu);
1284 if (err)
1285 goto err_pm_disable;
1286 }
1287
1288 dma_set_mask_and_coherent(dev, rk_ops->dma_bit_mask);
1289
1290 return 0;
1291 err_pm_disable:
1292 pm_runtime_disable(dev);
1293 err_remove_sysfs:
1294 iommu_device_sysfs_remove(&iommu->iommu);
1295 err_put_group:
1296 iommu_group_put(iommu->group);
1297 err_unprepare_clocks:
1298 clk_bulk_unprepare(iommu->num_clocks, iommu->clocks);
1299 return err;
1300 }
1301
rk_iommu_shutdown(struct platform_device * pdev)1302 static void rk_iommu_shutdown(struct platform_device *pdev)
1303 {
1304 struct rk_iommu *iommu = platform_get_drvdata(pdev);
1305 int i;
1306
1307 for (i = 0; i < iommu->num_irq; i++) {
1308 int irq = platform_get_irq(pdev, i);
1309
1310 devm_free_irq(iommu->dev, irq, iommu);
1311 }
1312
1313 pm_runtime_force_suspend(&pdev->dev);
1314 }
1315
rk_iommu_suspend(struct device * dev)1316 static int __maybe_unused rk_iommu_suspend(struct device *dev)
1317 {
1318 struct rk_iommu *iommu = dev_get_drvdata(dev);
1319
1320 if (!iommu->domain)
1321 return 0;
1322
1323 rk_iommu_disable(iommu);
1324 return 0;
1325 }
1326
rk_iommu_resume(struct device * dev)1327 static int __maybe_unused rk_iommu_resume(struct device *dev)
1328 {
1329 struct rk_iommu *iommu = dev_get_drvdata(dev);
1330
1331 if (!iommu->domain)
1332 return 0;
1333
1334 return rk_iommu_enable(iommu);
1335 }
1336
1337 static const struct dev_pm_ops rk_iommu_pm_ops = {
1338 SET_RUNTIME_PM_OPS(rk_iommu_suspend, rk_iommu_resume, NULL)
1339 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1340 pm_runtime_force_resume)
1341 };
1342
1343 static struct rk_iommu_ops iommu_data_ops_v1 = {
1344 .pt_address = &rk_dte_pt_address,
1345 .mk_dtentries = &rk_mk_dte,
1346 .mk_ptentries = &rk_mk_pte,
1347 .dma_bit_mask = DMA_BIT_MASK(32),
1348 };
1349
1350 static struct rk_iommu_ops iommu_data_ops_v2 = {
1351 .pt_address = &rk_dte_pt_address_v2,
1352 .mk_dtentries = &rk_mk_dte_v2,
1353 .mk_ptentries = &rk_mk_pte_v2,
1354 .dma_bit_mask = DMA_BIT_MASK(40),
1355 };
1356
1357 static const struct of_device_id rk_iommu_dt_ids[] = {
1358 { .compatible = "rockchip,iommu",
1359 .data = &iommu_data_ops_v1,
1360 },
1361 { .compatible = "rockchip,rk3568-iommu",
1362 .data = &iommu_data_ops_v2,
1363 },
1364 { /* sentinel */ }
1365 };
1366
1367 static struct platform_driver rk_iommu_driver = {
1368 .probe = rk_iommu_probe,
1369 .shutdown = rk_iommu_shutdown,
1370 .driver = {
1371 .name = "rk_iommu",
1372 .of_match_table = rk_iommu_dt_ids,
1373 .pm = &rk_iommu_pm_ops,
1374 .suppress_bind_attrs = true,
1375 },
1376 };
1377
rk_iommu_init(void)1378 static int __init rk_iommu_init(void)
1379 {
1380 return platform_driver_register(&rk_iommu_driver);
1381 }
1382 subsys_initcall(rk_iommu_init);
1383