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Searched refs:bcr (Results 1 – 18 of 18) sorted by relevance

/drivers/memory/
Dstm32-fmc2-ebi.c139 u32 bcr[FMC2_MAX_EBI_CE]; member
181 u32 bcr; in stm32_fmc2_ebi_check_mux() local
183 regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); in stm32_fmc2_ebi_check_mux()
185 if (bcr & FMC2_BCR_MTYP) in stm32_fmc2_ebi_check_mux()
195 u32 bcr, val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); in stm32_fmc2_ebi_check_waitcfg() local
197 regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); in stm32_fmc2_ebi_check_waitcfg()
199 if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN) in stm32_fmc2_ebi_check_waitcfg()
209 u32 bcr; in stm32_fmc2_ebi_check_sync_trans() local
211 regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); in stm32_fmc2_ebi_check_sync_trans()
213 if (bcr & FMC2_BCR_BURSTEN) in stm32_fmc2_ebi_check_sync_trans()
[all …]
/drivers/mtd/spi-nor/controllers/
Dintel-spi-pci.c22 u32 bcr; in intel_spi_pci_set_writeable() local
25 pci_read_config_dword(pdev, BCR, &bcr); in intel_spi_pci_set_writeable()
26 if (!(bcr & BCR_WPD)) { in intel_spi_pci_set_writeable()
27 bcr |= BCR_WPD; in intel_spi_pci_set_writeable()
28 pci_write_config_dword(pdev, BCR, bcr); in intel_spi_pci_set_writeable()
29 pci_read_config_dword(pdev, BCR, &bcr); in intel_spi_pci_set_writeable()
32 return bcr & BCR_WPD; in intel_spi_pci_set_writeable()
/drivers/i2c/busses/
Di2c-synquacer.c261 unsigned char bsr, bcr; in synquacer_i2c_master_start() local
269 bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR); in synquacer_i2c_master_start()
270 dev_dbg(i2c->dev, "bsr:0x%02x, bcr:0x%02x\n", bsr, bcr); in synquacer_i2c_master_start()
273 !(bcr & SYNQUACER_I2C_BCR_MSS)) { in synquacer_i2c_master_start()
280 writeb(bcr | SYNQUACER_I2C_BCR_SCC, in synquacer_i2c_master_start()
283 if (bcr & SYNQUACER_I2C_BCR_MSS) { in synquacer_i2c_master_start()
289 writeb(bcr | SYNQUACER_I2C_BCR_MSS | in synquacer_i2c_master_start()
298 bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR); in synquacer_i2c_master_start()
299 dev_dbg(i2c->dev, "bsr:0x%02x, bcr:0x%02x\n", bsr, bcr); in synquacer_i2c_master_start()
302 !(bcr & SYNQUACER_I2C_BCR_MSS)) { in synquacer_i2c_master_start()
[all …]
/drivers/net/can/cc770/
Dcc770_isa.c74 static u8 bcr[MAXDEV] = {[0 ... (MAXDEV - 1)] = 0xff}; variable
99 module_param_array(bcr, byte, NULL, 0444);
100 MODULE_PARM_DESC(bcr, "Bus configuration register (default=0x40 [CBY])");
246 if (bcr[idx] != 0xff) in cc770_isa_probe()
247 priv->bus_config = bcr[idx]; in cc770_isa_probe()
248 else if (bcr[0] != 0xff) in cc770_isa_probe()
249 priv->bus_config = bcr[0]; in cc770_isa_probe()
Dcc770_platform.c153 priv->bus_config = pdata->bcr; in cc770_get_platform_data()
/drivers/mfd/
Dlpc_ich.c1106 u32 bcr; in lpc_ich_lpt_set_writeable() local
1108 pci_read_config_dword(pdev, BCR, &bcr); in lpc_ich_lpt_set_writeable()
1109 if (!(bcr & BCR_WPD)) { in lpc_ich_lpt_set_writeable()
1110 bcr |= BCR_WPD; in lpc_ich_lpt_set_writeable()
1111 pci_write_config_dword(pdev, BCR, bcr); in lpc_ich_lpt_set_writeable()
1112 pci_read_config_dword(pdev, BCR, &bcr); in lpc_ich_lpt_set_writeable()
1115 return bcr & BCR_WPD; in lpc_ich_lpt_set_writeable()
1122 u32 bcr; in lpc_ich_bxt_set_writeable() local
1124 pci_bus_read_config_dword(bus, spi, BCR, &bcr); in lpc_ich_bxt_set_writeable()
1125 if (!(bcr & BCR_WPD)) { in lpc_ich_bxt_set_writeable()
[all …]
/drivers/i3c/master/mipi-i3c-hci/
Ddct_v1.c21 u64 *pid, unsigned int *dcr, unsigned int *bcr) in i3c_hci_dct_get_val() argument
35 *bcr = FIELD_GET(W2_MASK(79, 72), dct_entry_data[2]); in i3c_hci_dct_get_val()
Dcmd_v2.c246 unsigned int dcr, bcr; in hci_cmd_v2_daa() local
294 bcr = FIELD_GET(W1_MASK(55, 48), device_id[1]); in hci_cmd_v2_daa()
297 next_addr, pid, dcr, bcr); in hci_cmd_v2_daa()
Dcmd_v1.c298 unsigned int dcr, bcr; in hci_cmd_v1_daa() local
351 i3c_hci_dct_get_val(hci, 0, &pid, &dcr, &bcr); in hci_cmd_v1_daa()
353 next_addr, pid, dcr, bcr); in hci_cmd_v1_daa()
Ddct.h14 u64 *pid, unsigned int *dcr, unsigned int *bcr);
/drivers/i3c/
Dmaster.c141 ret = sprintf(buf, "%x\n", desc->info.bcr); in bcr_show()
146 static DEVICE_ATTR_RO(bcr);
916 if (I3C_BCR_DEVICE_ROLE(i3cdev->info.bcr) == in i3c_master_defslvs_locked()
935 defslvs->master.bcr = master->this->info.bcr; in i3c_master_defslvs_locked()
952 desc->bcr = i3cdev->info.bcr; in i3c_master_defslvs_locked()
1020 if (!(info->bcr & I3C_BCR_IBI_PAYLOAD)) in i3c_master_getmrl_locked()
1190 info->bcr = getbcr->bcr; in i3c_master_getbcr_locked()
1250 if (dev->info.bcr & I3C_BCR_MAX_DATA_SPEED_LIM) { in i3c_master_retrieve_dev_info()
1256 if (dev->info.bcr & I3C_BCR_IBI_PAYLOAD) in i3c_master_retrieve_dev_info()
1262 if (dev->info.bcr & I3C_BCR_HDR_CAP) { in i3c_master_retrieve_dev_info()
[all …]
/drivers/net/can/rcar/
Drcar_can.c65 u8 bcr[3]; /* Bit Configuration Register */ member
431 u32 bcr; in rcar_can_set_bittiming() local
433 bcr = RCAR_CAN_BCR_TSEG1(bt->phase_seg1 + bt->prop_seg - 1) | in rcar_can_set_bittiming()
440 writel((bcr << 8) | priv->clock_select, &priv->regs->bcr); in rcar_can_set_bittiming()
/drivers/i3c/master/
Di3c-master-cdns.c301 #define DEV_ID_RR2_BCR(bcr) ((bcr) << 8) argument
1058 info->bcr = rr >> 8; in cdns_i3c_master_dev_rr_to_info()
1276 if (info.bcr & I3C_BCR_HDR_CAP) in cdns_i3c_master_bus_init()
1447 sircfg = SIR_MAP_DEV_ROLE(dev->info.bcr >> 6) | in cdns_i3c_master_enable_ibi()
1452 if (dev->info.bcr & I3C_BCR_MAX_DATA_SPEED_LIM) in cdns_i3c_master_enable_ibi()
Dsvc-i3c-master.c800 if (I3C_BCR_DEVICE_ROLE(dev->info.bcr) == I3C_BCR_I3C_MASTER) in svc_i3c_update_ibirules()
803 if (dev->info.bcr & I3C_BCR_IBI_PAYLOAD) { in svc_i3c_update_ibirules()
/drivers/dma/
Dfsldma.h113 u32 bcr; /* 0x20 - Byte Count Register */ member
Dfsldma.c81 FSL_DMA_OUT(chan, &chan->regs->bcr, val, 32); in set_bcr()
86 return FSL_DMA_IN(chan, &chan->regs->bcr, 32); in get_bcr()
/drivers/video/fbdev/omap2/omapfb/dss/
Ddispc.c239 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb; member
671 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by)); in dispc_ovl_write_color_conv_coef()
/drivers/gpu/drm/omapdrm/dss/
Ddispc.c852 int ry, rcb, rcr, gy, gcb, gcr, by, bcb, bcr; member
870 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by)); in dispc_ovl_write_color_conv_coef()