1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * lpc_ich.c - LPC interface for Intel ICH
4 *
5 * LPC bridge function of the Intel ICH contains many other
6 * functional units, such as Interrupt controllers, Timers,
7 * Power Management, System Management, GPIO, RTC, and LPC
8 * Configuration Registers.
9 *
10 * This driver is derived from lpc_sch.
11
12 * Copyright (c) 2011 Extreme Engineering Solution, Inc.
13 * Author: Aaron Sierra <asierra@xes-inc.com>
14 *
15 * This driver supports the following I/O Controller hubs:
16 * (See the intel documentation on http://developer.intel.com.)
17 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
18 * document number 290687-002, 298242-027: 82801BA (ICH2)
19 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
20 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
21 * document number 290744-001, 290745-025: 82801DB (ICH4)
22 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
23 * document number 273599-001, 273645-002: 82801E (C-ICH)
24 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
25 * document number 300641-004, 300884-013: 6300ESB
26 * document number 301473-002, 301474-026: 82801F (ICH6)
27 * document number 313082-001, 313075-006: 631xESB, 632xESB
28 * document number 307013-003, 307014-024: 82801G (ICH7)
29 * document number 322896-001, 322897-001: NM10
30 * document number 313056-003, 313057-017: 82801H (ICH8)
31 * document number 316972-004, 316973-012: 82801I (ICH9)
32 * document number 319973-002, 319974-002: 82801J (ICH10)
33 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
34 * document number 320066-003, 320257-008: EP80597 (IICH)
35 * document number 324645-001, 324646-001: Cougar Point (CPT)
36 */
37
38 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
39
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/errno.h>
43 #include <linux/acpi.h>
44 #include <linux/pci.h>
45 #include <linux/mfd/core.h>
46 #include <linux/mfd/lpc_ich.h>
47 #include <linux/platform_data/itco_wdt.h>
48
49 #define ACPIBASE 0x40
50 #define ACPIBASE_GPE_OFF 0x28
51 #define ACPIBASE_GPE_END 0x2f
52 #define ACPIBASE_SMI_OFF 0x30
53 #define ACPIBASE_SMI_END 0x33
54 #define ACPIBASE_PMC_OFF 0x08
55 #define ACPIBASE_PMC_END 0x0c
56 #define ACPIBASE_TCO_OFF 0x60
57 #define ACPIBASE_TCO_END 0x7f
58 #define ACPICTRL_PMCBASE 0x44
59
60 #define ACPIBASE_GCS_OFF 0x3410
61 #define ACPIBASE_GCS_END 0x3414
62
63 #define SPIBASE_BYT 0x54
64 #define SPIBASE_BYT_SZ 512
65 #define SPIBASE_BYT_EN BIT(1)
66 #define BYT_BCR 0xfc
67 #define BYT_BCR_WPD BIT(0)
68
69 #define SPIBASE_LPT 0x3800
70 #define SPIBASE_LPT_SZ 512
71 #define BCR 0xdc
72 #define BCR_WPD BIT(0)
73
74 #define SPIBASE_APL_SZ 4096
75
76 #define GPIOBASE_ICH0 0x58
77 #define GPIOCTRL_ICH0 0x5C
78 #define GPIOBASE_ICH6 0x48
79 #define GPIOCTRL_ICH6 0x4C
80
81 #define RCBABASE 0xf0
82
83 #define wdt_io_res(i) wdt_res(0, i)
84 #define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i)
85 #define wdt_res(b, i) (&wdt_ich_res[(b) + (i)])
86
87 struct lpc_ich_priv {
88 int chipset;
89
90 int abase; /* ACPI base */
91 int actrl_pbase; /* ACPI control or PMC base */
92 int gbase; /* GPIO base */
93 int gctrl; /* GPIO control */
94
95 int abase_save; /* Cached ACPI base value */
96 int actrl_pbase_save; /* Cached ACPI control or PMC base value */
97 int gctrl_save; /* Cached GPIO control value */
98 };
99
100 static struct resource wdt_ich_res[] = {
101 /* ACPI - TCO */
102 {
103 .flags = IORESOURCE_IO,
104 },
105 /* ACPI - SMI */
106 {
107 .flags = IORESOURCE_IO,
108 },
109 /* GCS or PMC */
110 {
111 .flags = IORESOURCE_MEM,
112 },
113 };
114
115 static struct resource gpio_ich_res[] = {
116 /* GPIO */
117 {
118 .flags = IORESOURCE_IO,
119 },
120 /* ACPI - GPE0 */
121 {
122 .flags = IORESOURCE_IO,
123 },
124 };
125
126 static struct resource intel_spi_res[] = {
127 {
128 .flags = IORESOURCE_MEM,
129 }
130 };
131
132 static struct mfd_cell lpc_ich_wdt_cell = {
133 .name = "iTCO_wdt",
134 .num_resources = ARRAY_SIZE(wdt_ich_res),
135 .resources = wdt_ich_res,
136 .ignore_resource_conflicts = true,
137 };
138
139 static struct mfd_cell lpc_ich_gpio_cell = {
140 .name = "gpio_ich",
141 .num_resources = ARRAY_SIZE(gpio_ich_res),
142 .resources = gpio_ich_res,
143 .ignore_resource_conflicts = true,
144 };
145
146
147 static struct mfd_cell lpc_ich_spi_cell = {
148 .name = "intel-spi",
149 .num_resources = ARRAY_SIZE(intel_spi_res),
150 .resources = intel_spi_res,
151 .ignore_resource_conflicts = true,
152 };
153
154 /* chipset related info */
155 enum lpc_chipsets {
156 LPC_ICH = 0, /* ICH */
157 LPC_ICH0, /* ICH0 */
158 LPC_ICH2, /* ICH2 */
159 LPC_ICH2M, /* ICH2-M */
160 LPC_ICH3, /* ICH3-S */
161 LPC_ICH3M, /* ICH3-M */
162 LPC_ICH4, /* ICH4 */
163 LPC_ICH4M, /* ICH4-M */
164 LPC_CICH, /* C-ICH */
165 LPC_ICH5, /* ICH5 & ICH5R */
166 LPC_6300ESB, /* 6300ESB */
167 LPC_ICH6, /* ICH6 & ICH6R */
168 LPC_ICH6M, /* ICH6-M */
169 LPC_ICH6W, /* ICH6W & ICH6RW */
170 LPC_631XESB, /* 631xESB/632xESB */
171 LPC_ICH7, /* ICH7 & ICH7R */
172 LPC_ICH7DH, /* ICH7DH */
173 LPC_ICH7M, /* ICH7-M & ICH7-U */
174 LPC_ICH7MDH, /* ICH7-M DH */
175 LPC_NM10, /* NM10 */
176 LPC_ICH8, /* ICH8 & ICH8R */
177 LPC_ICH8DH, /* ICH8DH */
178 LPC_ICH8DO, /* ICH8DO */
179 LPC_ICH8M, /* ICH8M */
180 LPC_ICH8ME, /* ICH8M-E */
181 LPC_ICH9, /* ICH9 */
182 LPC_ICH9R, /* ICH9R */
183 LPC_ICH9DH, /* ICH9DH */
184 LPC_ICH9DO, /* ICH9DO */
185 LPC_ICH9M, /* ICH9M */
186 LPC_ICH9ME, /* ICH9M-E */
187 LPC_ICH10, /* ICH10 */
188 LPC_ICH10R, /* ICH10R */
189 LPC_ICH10D, /* ICH10D */
190 LPC_ICH10DO, /* ICH10DO */
191 LPC_PCH, /* PCH Desktop Full Featured */
192 LPC_PCHM, /* PCH Mobile Full Featured */
193 LPC_P55, /* P55 */
194 LPC_PM55, /* PM55 */
195 LPC_H55, /* H55 */
196 LPC_QM57, /* QM57 */
197 LPC_H57, /* H57 */
198 LPC_HM55, /* HM55 */
199 LPC_Q57, /* Q57 */
200 LPC_HM57, /* HM57 */
201 LPC_PCHMSFF, /* PCH Mobile SFF Full Featured */
202 LPC_QS57, /* QS57 */
203 LPC_3400, /* 3400 */
204 LPC_3420, /* 3420 */
205 LPC_3450, /* 3450 */
206 LPC_EP80579, /* EP80579 */
207 LPC_CPT, /* Cougar Point */
208 LPC_CPTD, /* Cougar Point Desktop */
209 LPC_CPTM, /* Cougar Point Mobile */
210 LPC_PBG, /* Patsburg */
211 LPC_DH89XXCC, /* DH89xxCC */
212 LPC_PPT, /* Panther Point */
213 LPC_LPT, /* Lynx Point */
214 LPC_LPT_LP, /* Lynx Point-LP */
215 LPC_WBG, /* Wellsburg */
216 LPC_AVN, /* Avoton SoC */
217 LPC_BAYTRAIL, /* Bay Trail SoC */
218 LPC_COLETO, /* Coleto Creek */
219 LPC_WPT_LP, /* Wildcat Point-LP */
220 LPC_BRASWELL, /* Braswell SoC */
221 LPC_LEWISBURG, /* Lewisburg */
222 LPC_9S, /* 9 Series */
223 LPC_APL, /* Apollo Lake SoC */
224 LPC_GLK, /* Gemini Lake SoC */
225 LPC_COUGARMOUNTAIN,/* Cougar Mountain SoC*/
226 };
227
228 static struct lpc_ich_info lpc_chipset_info[] = {
229 [LPC_ICH] = {
230 .name = "ICH",
231 .iTCO_version = 1,
232 },
233 [LPC_ICH0] = {
234 .name = "ICH0",
235 .iTCO_version = 1,
236 },
237 [LPC_ICH2] = {
238 .name = "ICH2",
239 .iTCO_version = 1,
240 },
241 [LPC_ICH2M] = {
242 .name = "ICH2-M",
243 .iTCO_version = 1,
244 },
245 [LPC_ICH3] = {
246 .name = "ICH3-S",
247 .iTCO_version = 1,
248 },
249 [LPC_ICH3M] = {
250 .name = "ICH3-M",
251 .iTCO_version = 1,
252 },
253 [LPC_ICH4] = {
254 .name = "ICH4",
255 .iTCO_version = 1,
256 },
257 [LPC_ICH4M] = {
258 .name = "ICH4-M",
259 .iTCO_version = 1,
260 },
261 [LPC_CICH] = {
262 .name = "C-ICH",
263 .iTCO_version = 1,
264 },
265 [LPC_ICH5] = {
266 .name = "ICH5 or ICH5R",
267 .iTCO_version = 1,
268 },
269 [LPC_6300ESB] = {
270 .name = "6300ESB",
271 .iTCO_version = 1,
272 },
273 [LPC_ICH6] = {
274 .name = "ICH6 or ICH6R",
275 .iTCO_version = 2,
276 .gpio_version = ICH_V6_GPIO,
277 },
278 [LPC_ICH6M] = {
279 .name = "ICH6-M",
280 .iTCO_version = 2,
281 .gpio_version = ICH_V6_GPIO,
282 },
283 [LPC_ICH6W] = {
284 .name = "ICH6W or ICH6RW",
285 .iTCO_version = 2,
286 .gpio_version = ICH_V6_GPIO,
287 },
288 [LPC_631XESB] = {
289 .name = "631xESB/632xESB",
290 .iTCO_version = 2,
291 .gpio_version = ICH_V6_GPIO,
292 },
293 [LPC_ICH7] = {
294 .name = "ICH7 or ICH7R",
295 .iTCO_version = 2,
296 .gpio_version = ICH_V7_GPIO,
297 },
298 [LPC_ICH7DH] = {
299 .name = "ICH7DH",
300 .iTCO_version = 2,
301 .gpio_version = ICH_V7_GPIO,
302 },
303 [LPC_ICH7M] = {
304 .name = "ICH7-M or ICH7-U",
305 .iTCO_version = 2,
306 .gpio_version = ICH_V7_GPIO,
307 },
308 [LPC_ICH7MDH] = {
309 .name = "ICH7-M DH",
310 .iTCO_version = 2,
311 .gpio_version = ICH_V7_GPIO,
312 },
313 [LPC_NM10] = {
314 .name = "NM10",
315 .iTCO_version = 2,
316 .gpio_version = ICH_V7_GPIO,
317 },
318 [LPC_ICH8] = {
319 .name = "ICH8 or ICH8R",
320 .iTCO_version = 2,
321 .gpio_version = ICH_V7_GPIO,
322 },
323 [LPC_ICH8DH] = {
324 .name = "ICH8DH",
325 .iTCO_version = 2,
326 .gpio_version = ICH_V7_GPIO,
327 },
328 [LPC_ICH8DO] = {
329 .name = "ICH8DO",
330 .iTCO_version = 2,
331 .gpio_version = ICH_V7_GPIO,
332 },
333 [LPC_ICH8M] = {
334 .name = "ICH8M",
335 .iTCO_version = 2,
336 .gpio_version = ICH_V7_GPIO,
337 },
338 [LPC_ICH8ME] = {
339 .name = "ICH8M-E",
340 .iTCO_version = 2,
341 .gpio_version = ICH_V7_GPIO,
342 },
343 [LPC_ICH9] = {
344 .name = "ICH9",
345 .iTCO_version = 2,
346 .gpio_version = ICH_V9_GPIO,
347 },
348 [LPC_ICH9R] = {
349 .name = "ICH9R",
350 .iTCO_version = 2,
351 .gpio_version = ICH_V9_GPIO,
352 },
353 [LPC_ICH9DH] = {
354 .name = "ICH9DH",
355 .iTCO_version = 2,
356 .gpio_version = ICH_V9_GPIO,
357 },
358 [LPC_ICH9DO] = {
359 .name = "ICH9DO",
360 .iTCO_version = 2,
361 .gpio_version = ICH_V9_GPIO,
362 },
363 [LPC_ICH9M] = {
364 .name = "ICH9M",
365 .iTCO_version = 2,
366 .gpio_version = ICH_V9_GPIO,
367 },
368 [LPC_ICH9ME] = {
369 .name = "ICH9M-E",
370 .iTCO_version = 2,
371 .gpio_version = ICH_V9_GPIO,
372 },
373 [LPC_ICH10] = {
374 .name = "ICH10",
375 .iTCO_version = 2,
376 .gpio_version = ICH_V10CONS_GPIO,
377 },
378 [LPC_ICH10R] = {
379 .name = "ICH10R",
380 .iTCO_version = 2,
381 .gpio_version = ICH_V10CONS_GPIO,
382 },
383 [LPC_ICH10D] = {
384 .name = "ICH10D",
385 .iTCO_version = 2,
386 .gpio_version = ICH_V10CORP_GPIO,
387 },
388 [LPC_ICH10DO] = {
389 .name = "ICH10DO",
390 .iTCO_version = 2,
391 .gpio_version = ICH_V10CORP_GPIO,
392 },
393 [LPC_PCH] = {
394 .name = "PCH Desktop Full Featured",
395 .iTCO_version = 2,
396 .gpio_version = ICH_V5_GPIO,
397 },
398 [LPC_PCHM] = {
399 .name = "PCH Mobile Full Featured",
400 .iTCO_version = 2,
401 .gpio_version = ICH_V5_GPIO,
402 },
403 [LPC_P55] = {
404 .name = "P55",
405 .iTCO_version = 2,
406 .gpio_version = ICH_V5_GPIO,
407 },
408 [LPC_PM55] = {
409 .name = "PM55",
410 .iTCO_version = 2,
411 .gpio_version = ICH_V5_GPIO,
412 },
413 [LPC_H55] = {
414 .name = "H55",
415 .iTCO_version = 2,
416 .gpio_version = ICH_V5_GPIO,
417 },
418 [LPC_QM57] = {
419 .name = "QM57",
420 .iTCO_version = 2,
421 .gpio_version = ICH_V5_GPIO,
422 },
423 [LPC_H57] = {
424 .name = "H57",
425 .iTCO_version = 2,
426 .gpio_version = ICH_V5_GPIO,
427 },
428 [LPC_HM55] = {
429 .name = "HM55",
430 .iTCO_version = 2,
431 .gpio_version = ICH_V5_GPIO,
432 },
433 [LPC_Q57] = {
434 .name = "Q57",
435 .iTCO_version = 2,
436 .gpio_version = ICH_V5_GPIO,
437 },
438 [LPC_HM57] = {
439 .name = "HM57",
440 .iTCO_version = 2,
441 .gpio_version = ICH_V5_GPIO,
442 },
443 [LPC_PCHMSFF] = {
444 .name = "PCH Mobile SFF Full Featured",
445 .iTCO_version = 2,
446 .gpio_version = ICH_V5_GPIO,
447 },
448 [LPC_QS57] = {
449 .name = "QS57",
450 .iTCO_version = 2,
451 .gpio_version = ICH_V5_GPIO,
452 },
453 [LPC_3400] = {
454 .name = "3400",
455 .iTCO_version = 2,
456 .gpio_version = ICH_V5_GPIO,
457 },
458 [LPC_3420] = {
459 .name = "3420",
460 .iTCO_version = 2,
461 .gpio_version = ICH_V5_GPIO,
462 },
463 [LPC_3450] = {
464 .name = "3450",
465 .iTCO_version = 2,
466 .gpio_version = ICH_V5_GPIO,
467 },
468 [LPC_EP80579] = {
469 .name = "EP80579",
470 .iTCO_version = 2,
471 },
472 [LPC_CPT] = {
473 .name = "Cougar Point",
474 .iTCO_version = 2,
475 .gpio_version = ICH_V5_GPIO,
476 },
477 [LPC_CPTD] = {
478 .name = "Cougar Point Desktop",
479 .iTCO_version = 2,
480 .gpio_version = ICH_V5_GPIO,
481 },
482 [LPC_CPTM] = {
483 .name = "Cougar Point Mobile",
484 .iTCO_version = 2,
485 .gpio_version = ICH_V5_GPIO,
486 },
487 [LPC_PBG] = {
488 .name = "Patsburg",
489 .iTCO_version = 2,
490 },
491 [LPC_DH89XXCC] = {
492 .name = "DH89xxCC",
493 .iTCO_version = 2,
494 .gpio_version = ICH_V5_GPIO,
495 },
496 [LPC_PPT] = {
497 .name = "Panther Point",
498 .iTCO_version = 2,
499 .gpio_version = ICH_V5_GPIO,
500 },
501 [LPC_LPT] = {
502 .name = "Lynx Point",
503 .iTCO_version = 2,
504 .gpio_version = ICH_V5_GPIO,
505 .spi_type = INTEL_SPI_LPT,
506 },
507 [LPC_LPT_LP] = {
508 .name = "Lynx Point_LP",
509 .iTCO_version = 2,
510 .spi_type = INTEL_SPI_LPT,
511 },
512 [LPC_WBG] = {
513 .name = "Wellsburg",
514 .iTCO_version = 2,
515 },
516 [LPC_AVN] = {
517 .name = "Avoton SoC",
518 .iTCO_version = 3,
519 .gpio_version = AVOTON_GPIO,
520 .spi_type = INTEL_SPI_BYT,
521 },
522 [LPC_BAYTRAIL] = {
523 .name = "Bay Trail SoC",
524 .iTCO_version = 3,
525 .spi_type = INTEL_SPI_BYT,
526 },
527 [LPC_COLETO] = {
528 .name = "Coleto Creek",
529 .iTCO_version = 2,
530 },
531 [LPC_WPT_LP] = {
532 .name = "Wildcat Point_LP",
533 .iTCO_version = 2,
534 .spi_type = INTEL_SPI_LPT,
535 },
536 [LPC_BRASWELL] = {
537 .name = "Braswell SoC",
538 .iTCO_version = 3,
539 .spi_type = INTEL_SPI_BYT,
540 },
541 [LPC_LEWISBURG] = {
542 .name = "Lewisburg",
543 .iTCO_version = 2,
544 },
545 [LPC_9S] = {
546 .name = "9 Series",
547 .iTCO_version = 2,
548 .gpio_version = ICH_V5_GPIO,
549 },
550 [LPC_APL] = {
551 .name = "Apollo Lake SoC",
552 .iTCO_version = 5,
553 .spi_type = INTEL_SPI_BXT,
554 },
555 [LPC_GLK] = {
556 .name = "Gemini Lake SoC",
557 .spi_type = INTEL_SPI_BXT,
558 },
559 [LPC_COUGARMOUNTAIN] = {
560 .name = "Cougar Mountain SoC",
561 .iTCO_version = 3,
562 },
563 };
564
565 /*
566 * This data only exists for exporting the supported PCI ids
567 * via MODULE_DEVICE_TABLE. We do not actually register a
568 * pci_driver, because the I/O Controller Hub has also other
569 * functions that probably will be registered by other drivers.
570 */
571 static const struct pci_device_id lpc_ich_ids[] = {
572 { PCI_VDEVICE(INTEL, 0x0f1c), LPC_BAYTRAIL},
573 { PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT},
574 { PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD},
575 { PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM},
576 { PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT},
577 { PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT},
578 { PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT},
579 { PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT},
580 { PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT},
581 { PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT},
582 { PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT},
583 { PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT},
584 { PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT},
585 { PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT},
586 { PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT},
587 { PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT},
588 { PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT},
589 { PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT},
590 { PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT},
591 { PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT},
592 { PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT},
593 { PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT},
594 { PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT},
595 { PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT},
596 { PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT},
597 { PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT},
598 { PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT},
599 { PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT},
600 { PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT},
601 { PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT},
602 { PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT},
603 { PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT},
604 { PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG},
605 { PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG},
606 { PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT},
607 { PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT},
608 { PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT},
609 { PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT},
610 { PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT},
611 { PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT},
612 { PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT},
613 { PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT},
614 { PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT},
615 { PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT},
616 { PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT},
617 { PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT},
618 { PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT},
619 { PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT},
620 { PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT},
621 { PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT},
622 { PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT},
623 { PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT},
624 { PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT},
625 { PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT},
626 { PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT},
627 { PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT},
628 { PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT},
629 { PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT},
630 { PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT},
631 { PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT},
632 { PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT},
633 { PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT},
634 { PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT},
635 { PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT},
636 { PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT},
637 { PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT},
638 { PCI_VDEVICE(INTEL, 0x1f38), LPC_AVN},
639 { PCI_VDEVICE(INTEL, 0x1f39), LPC_AVN},
640 { PCI_VDEVICE(INTEL, 0x1f3a), LPC_AVN},
641 { PCI_VDEVICE(INTEL, 0x1f3b), LPC_AVN},
642 { PCI_VDEVICE(INTEL, 0x229c), LPC_BRASWELL},
643 { PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC},
644 { PCI_VDEVICE(INTEL, 0x2390), LPC_COLETO},
645 { PCI_VDEVICE(INTEL, 0x2410), LPC_ICH},
646 { PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0},
647 { PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2},
648 { PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M},
649 { PCI_VDEVICE(INTEL, 0x2450), LPC_CICH},
650 { PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3},
651 { PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M},
652 { PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4},
653 { PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M},
654 { PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5},
655 { PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB},
656 { PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6},
657 { PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M},
658 { PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W},
659 { PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB},
660 { PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB},
661 { PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB},
662 { PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB},
663 { PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB},
664 { PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB},
665 { PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB},
666 { PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB},
667 { PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB},
668 { PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB},
669 { PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB},
670 { PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB},
671 { PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB},
672 { PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB},
673 { PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB},
674 { PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB},
675 { PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH},
676 { PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7},
677 { PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M},
678 { PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10},
679 { PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH},
680 { PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8},
681 { PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME},
682 { PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH},
683 { PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO},
684 { PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M},
685 { PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH},
686 { PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO},
687 { PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R},
688 { PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME},
689 { PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9},
690 { PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M},
691 { PCI_VDEVICE(INTEL, 0x3197), LPC_GLK},
692 { PCI_VDEVICE(INTEL, 0x2b9c), LPC_COUGARMOUNTAIN},
693 { PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO},
694 { PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R},
695 { PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10},
696 { PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D},
697 { PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH},
698 { PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM},
699 { PCI_VDEVICE(INTEL, 0x3b02), LPC_P55},
700 { PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55},
701 { PCI_VDEVICE(INTEL, 0x3b06), LPC_H55},
702 { PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57},
703 { PCI_VDEVICE(INTEL, 0x3b08), LPC_H57},
704 { PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55},
705 { PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57},
706 { PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57},
707 { PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF},
708 { PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57},
709 { PCI_VDEVICE(INTEL, 0x3b12), LPC_3400},
710 { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
711 { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
712 { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
713 { PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL},
714 { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
715 { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
716 { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
717 { PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT},
718 { PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT},
719 { PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT},
720 { PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT},
721 { PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT},
722 { PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT},
723 { PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT},
724 { PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT},
725 { PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT},
726 { PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT},
727 { PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT},
728 { PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT},
729 { PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT},
730 { PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT},
731 { PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT},
732 { PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT},
733 { PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT},
734 { PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT},
735 { PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT},
736 { PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT},
737 { PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT},
738 { PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT},
739 { PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT},
740 { PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT},
741 { PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT},
742 { PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT},
743 { PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT},
744 { PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT},
745 { PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT},
746 { PCI_VDEVICE(INTEL, 0x8cc1), LPC_9S},
747 { PCI_VDEVICE(INTEL, 0x8cc2), LPC_9S},
748 { PCI_VDEVICE(INTEL, 0x8cc3), LPC_9S},
749 { PCI_VDEVICE(INTEL, 0x8cc4), LPC_9S},
750 { PCI_VDEVICE(INTEL, 0x8cc6), LPC_9S},
751 { PCI_VDEVICE(INTEL, 0x8d40), LPC_WBG},
752 { PCI_VDEVICE(INTEL, 0x8d41), LPC_WBG},
753 { PCI_VDEVICE(INTEL, 0x8d42), LPC_WBG},
754 { PCI_VDEVICE(INTEL, 0x8d43), LPC_WBG},
755 { PCI_VDEVICE(INTEL, 0x8d44), LPC_WBG},
756 { PCI_VDEVICE(INTEL, 0x8d45), LPC_WBG},
757 { PCI_VDEVICE(INTEL, 0x8d46), LPC_WBG},
758 { PCI_VDEVICE(INTEL, 0x8d47), LPC_WBG},
759 { PCI_VDEVICE(INTEL, 0x8d48), LPC_WBG},
760 { PCI_VDEVICE(INTEL, 0x8d49), LPC_WBG},
761 { PCI_VDEVICE(INTEL, 0x8d4a), LPC_WBG},
762 { PCI_VDEVICE(INTEL, 0x8d4b), LPC_WBG},
763 { PCI_VDEVICE(INTEL, 0x8d4c), LPC_WBG},
764 { PCI_VDEVICE(INTEL, 0x8d4d), LPC_WBG},
765 { PCI_VDEVICE(INTEL, 0x8d4e), LPC_WBG},
766 { PCI_VDEVICE(INTEL, 0x8d4f), LPC_WBG},
767 { PCI_VDEVICE(INTEL, 0x8d50), LPC_WBG},
768 { PCI_VDEVICE(INTEL, 0x8d51), LPC_WBG},
769 { PCI_VDEVICE(INTEL, 0x8d52), LPC_WBG},
770 { PCI_VDEVICE(INTEL, 0x8d53), LPC_WBG},
771 { PCI_VDEVICE(INTEL, 0x8d54), LPC_WBG},
772 { PCI_VDEVICE(INTEL, 0x8d55), LPC_WBG},
773 { PCI_VDEVICE(INTEL, 0x8d56), LPC_WBG},
774 { PCI_VDEVICE(INTEL, 0x8d57), LPC_WBG},
775 { PCI_VDEVICE(INTEL, 0x8d58), LPC_WBG},
776 { PCI_VDEVICE(INTEL, 0x8d59), LPC_WBG},
777 { PCI_VDEVICE(INTEL, 0x8d5a), LPC_WBG},
778 { PCI_VDEVICE(INTEL, 0x8d5b), LPC_WBG},
779 { PCI_VDEVICE(INTEL, 0x8d5c), LPC_WBG},
780 { PCI_VDEVICE(INTEL, 0x8d5d), LPC_WBG},
781 { PCI_VDEVICE(INTEL, 0x8d5e), LPC_WBG},
782 { PCI_VDEVICE(INTEL, 0x8d5f), LPC_WBG},
783 { PCI_VDEVICE(INTEL, 0x9c40), LPC_LPT_LP},
784 { PCI_VDEVICE(INTEL, 0x9c41), LPC_LPT_LP},
785 { PCI_VDEVICE(INTEL, 0x9c42), LPC_LPT_LP},
786 { PCI_VDEVICE(INTEL, 0x9c43), LPC_LPT_LP},
787 { PCI_VDEVICE(INTEL, 0x9c44), LPC_LPT_LP},
788 { PCI_VDEVICE(INTEL, 0x9c45), LPC_LPT_LP},
789 { PCI_VDEVICE(INTEL, 0x9c46), LPC_LPT_LP},
790 { PCI_VDEVICE(INTEL, 0x9c47), LPC_LPT_LP},
791 { PCI_VDEVICE(INTEL, 0x9cc1), LPC_WPT_LP},
792 { PCI_VDEVICE(INTEL, 0x9cc2), LPC_WPT_LP},
793 { PCI_VDEVICE(INTEL, 0x9cc3), LPC_WPT_LP},
794 { PCI_VDEVICE(INTEL, 0x9cc5), LPC_WPT_LP},
795 { PCI_VDEVICE(INTEL, 0x9cc6), LPC_WPT_LP},
796 { PCI_VDEVICE(INTEL, 0x9cc7), LPC_WPT_LP},
797 { PCI_VDEVICE(INTEL, 0x9cc9), LPC_WPT_LP},
798 { PCI_VDEVICE(INTEL, 0xa1c1), LPC_LEWISBURG},
799 { PCI_VDEVICE(INTEL, 0xa1c2), LPC_LEWISBURG},
800 { PCI_VDEVICE(INTEL, 0xa1c3), LPC_LEWISBURG},
801 { PCI_VDEVICE(INTEL, 0xa1c4), LPC_LEWISBURG},
802 { PCI_VDEVICE(INTEL, 0xa1c5), LPC_LEWISBURG},
803 { PCI_VDEVICE(INTEL, 0xa1c6), LPC_LEWISBURG},
804 { PCI_VDEVICE(INTEL, 0xa1c7), LPC_LEWISBURG},
805 { PCI_VDEVICE(INTEL, 0xa242), LPC_LEWISBURG},
806 { PCI_VDEVICE(INTEL, 0xa243), LPC_LEWISBURG},
807 { 0, }, /* End of list */
808 };
809 MODULE_DEVICE_TABLE(pci, lpc_ich_ids);
810
lpc_ich_restore_config_space(struct pci_dev * dev)811 static void lpc_ich_restore_config_space(struct pci_dev *dev)
812 {
813 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
814
815 if (priv->abase_save >= 0) {
816 pci_write_config_byte(dev, priv->abase, priv->abase_save);
817 priv->abase_save = -1;
818 }
819
820 if (priv->actrl_pbase_save >= 0) {
821 pci_write_config_byte(dev, priv->actrl_pbase,
822 priv->actrl_pbase_save);
823 priv->actrl_pbase_save = -1;
824 }
825
826 if (priv->gctrl_save >= 0) {
827 pci_write_config_byte(dev, priv->gctrl, priv->gctrl_save);
828 priv->gctrl_save = -1;
829 }
830 }
831
lpc_ich_enable_acpi_space(struct pci_dev * dev)832 static void lpc_ich_enable_acpi_space(struct pci_dev *dev)
833 {
834 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
835 u8 reg_save;
836
837 switch (lpc_chipset_info[priv->chipset].iTCO_version) {
838 case 3:
839 /*
840 * Some chipsets (eg Avoton) enable the ACPI space in the
841 * ACPI BASE register.
842 */
843 pci_read_config_byte(dev, priv->abase, ®_save);
844 pci_write_config_byte(dev, priv->abase, reg_save | 0x2);
845 priv->abase_save = reg_save;
846 break;
847 default:
848 /*
849 * Most chipsets enable the ACPI space in the ACPI control
850 * register.
851 */
852 pci_read_config_byte(dev, priv->actrl_pbase, ®_save);
853 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x80);
854 priv->actrl_pbase_save = reg_save;
855 break;
856 }
857 }
858
lpc_ich_enable_gpio_space(struct pci_dev * dev)859 static void lpc_ich_enable_gpio_space(struct pci_dev *dev)
860 {
861 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
862 u8 reg_save;
863
864 pci_read_config_byte(dev, priv->gctrl, ®_save);
865 pci_write_config_byte(dev, priv->gctrl, reg_save | 0x10);
866 priv->gctrl_save = reg_save;
867 }
868
lpc_ich_enable_pmc_space(struct pci_dev * dev)869 static void lpc_ich_enable_pmc_space(struct pci_dev *dev)
870 {
871 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
872 u8 reg_save;
873
874 pci_read_config_byte(dev, priv->actrl_pbase, ®_save);
875 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x2);
876
877 priv->actrl_pbase_save = reg_save;
878 }
879
lpc_ich_finalize_wdt_cell(struct pci_dev * dev)880 static int lpc_ich_finalize_wdt_cell(struct pci_dev *dev)
881 {
882 struct itco_wdt_platform_data *pdata;
883 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
884 struct lpc_ich_info *info;
885 struct mfd_cell *cell = &lpc_ich_wdt_cell;
886
887 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
888 if (!pdata)
889 return -ENOMEM;
890
891 info = &lpc_chipset_info[priv->chipset];
892
893 pdata->version = info->iTCO_version;
894 strlcpy(pdata->name, info->name, sizeof(pdata->name));
895
896 cell->platform_data = pdata;
897 cell->pdata_size = sizeof(*pdata);
898 return 0;
899 }
900
lpc_ich_finalize_gpio_cell(struct pci_dev * dev)901 static void lpc_ich_finalize_gpio_cell(struct pci_dev *dev)
902 {
903 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
904 struct mfd_cell *cell = &lpc_ich_gpio_cell;
905
906 cell->platform_data = &lpc_chipset_info[priv->chipset];
907 cell->pdata_size = sizeof(struct lpc_ich_info);
908 }
909
910 /*
911 * We don't check for resource conflict globally. There are 2 or 3 independent
912 * GPIO groups and it's enough to have access to one of these to instantiate
913 * the device.
914 */
lpc_ich_check_conflict_gpio(struct resource * res)915 static int lpc_ich_check_conflict_gpio(struct resource *res)
916 {
917 int ret;
918 u8 use_gpio = 0;
919
920 if (resource_size(res) >= 0x50 &&
921 !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3"))
922 use_gpio |= 1 << 2;
923
924 if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2"))
925 use_gpio |= 1 << 1;
926
927 ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1");
928 if (!ret)
929 use_gpio |= 1 << 0;
930
931 return use_gpio ? use_gpio : ret;
932 }
933
lpc_ich_init_gpio(struct pci_dev * dev)934 static int lpc_ich_init_gpio(struct pci_dev *dev)
935 {
936 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
937 u32 base_addr_cfg;
938 u32 base_addr;
939 int ret;
940 bool acpi_conflict = false;
941 struct resource *res;
942
943 /* Setup power management base register */
944 pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
945 base_addr = base_addr_cfg & 0x0000ff80;
946 if (!base_addr) {
947 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
948 lpc_ich_gpio_cell.num_resources--;
949 goto gpe0_done;
950 }
951
952 res = &gpio_ich_res[ICH_RES_GPE0];
953 res->start = base_addr + ACPIBASE_GPE_OFF;
954 res->end = base_addr + ACPIBASE_GPE_END;
955 ret = acpi_check_resource_conflict(res);
956 if (ret) {
957 /*
958 * This isn't fatal for the GPIO, but we have to make sure that
959 * the platform_device subsystem doesn't see this resource
960 * or it will register an invalid region.
961 */
962 lpc_ich_gpio_cell.num_resources--;
963 acpi_conflict = true;
964 } else {
965 lpc_ich_enable_acpi_space(dev);
966 }
967
968 gpe0_done:
969 /* Setup GPIO base register */
970 pci_read_config_dword(dev, priv->gbase, &base_addr_cfg);
971 base_addr = base_addr_cfg & 0x0000ff80;
972 if (!base_addr) {
973 dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n");
974 ret = -ENODEV;
975 goto gpio_done;
976 }
977
978 /* Older devices provide fewer GPIO and have a smaller resource size. */
979 res = &gpio_ich_res[ICH_RES_GPIO];
980 res->start = base_addr;
981 switch (lpc_chipset_info[priv->chipset].gpio_version) {
982 case ICH_V5_GPIO:
983 case ICH_V10CORP_GPIO:
984 res->end = res->start + 128 - 1;
985 break;
986 default:
987 res->end = res->start + 64 - 1;
988 break;
989 }
990
991 ret = lpc_ich_check_conflict_gpio(res);
992 if (ret < 0) {
993 /* this isn't necessarily fatal for the GPIO */
994 acpi_conflict = true;
995 goto gpio_done;
996 }
997 lpc_chipset_info[priv->chipset].use_gpio = ret;
998 lpc_ich_enable_gpio_space(dev);
999
1000 lpc_ich_finalize_gpio_cell(dev);
1001 ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,
1002 &lpc_ich_gpio_cell, 1, NULL, 0, NULL);
1003
1004 gpio_done:
1005 if (acpi_conflict)
1006 pr_warn("Resource conflict(s) found affecting %s\n",
1007 lpc_ich_gpio_cell.name);
1008 return ret;
1009 }
1010
lpc_ich_init_wdt(struct pci_dev * dev)1011 static int lpc_ich_init_wdt(struct pci_dev *dev)
1012 {
1013 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1014 u32 base_addr_cfg;
1015 u32 base_addr;
1016 int ret;
1017 struct resource *res;
1018
1019 /* If we have ACPI based watchdog use that instead */
1020 if (acpi_has_watchdog())
1021 return -ENODEV;
1022
1023 /* Setup power management base register */
1024 pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
1025 base_addr = base_addr_cfg & 0x0000ff80;
1026 if (!base_addr) {
1027 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
1028 ret = -ENODEV;
1029 goto wdt_done;
1030 }
1031
1032 res = wdt_io_res(ICH_RES_IO_TCO);
1033 res->start = base_addr + ACPIBASE_TCO_OFF;
1034 res->end = base_addr + ACPIBASE_TCO_END;
1035
1036 res = wdt_io_res(ICH_RES_IO_SMI);
1037 res->start = base_addr + ACPIBASE_SMI_OFF;
1038 res->end = base_addr + ACPIBASE_SMI_END;
1039
1040 lpc_ich_enable_acpi_space(dev);
1041
1042 /*
1043 * iTCO v2:
1044 * Get the Memory-Mapped GCS register. To get access to it
1045 * we have to read RCBA from PCI Config space 0xf0 and use
1046 * it as base. GCS = RCBA + ICH6_GCS(0x3410).
1047 *
1048 * iTCO v3:
1049 * Get the Power Management Configuration register. To get access
1050 * to it we have to read the PMC BASE from config space and address
1051 * the register at offset 0x8.
1052 */
1053 if (lpc_chipset_info[priv->chipset].iTCO_version == 1) {
1054 /* Don't register iomem for TCO ver 1 */
1055 lpc_ich_wdt_cell.num_resources--;
1056 } else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) {
1057 pci_read_config_dword(dev, RCBABASE, &base_addr_cfg);
1058 base_addr = base_addr_cfg & 0xffffc000;
1059 if (!(base_addr_cfg & 1)) {
1060 dev_notice(&dev->dev, "RCBA is disabled by "
1061 "hardware/BIOS, device disabled\n");
1062 ret = -ENODEV;
1063 goto wdt_done;
1064 }
1065 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
1066 res->start = base_addr + ACPIBASE_GCS_OFF;
1067 res->end = base_addr + ACPIBASE_GCS_END;
1068 } else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) {
1069 lpc_ich_enable_pmc_space(dev);
1070 pci_read_config_dword(dev, ACPICTRL_PMCBASE, &base_addr_cfg);
1071 base_addr = base_addr_cfg & 0xfffffe00;
1072
1073 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
1074 res->start = base_addr + ACPIBASE_PMC_OFF;
1075 res->end = base_addr + ACPIBASE_PMC_END;
1076 }
1077
1078 ret = lpc_ich_finalize_wdt_cell(dev);
1079 if (ret)
1080 goto wdt_done;
1081
1082 ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,
1083 &lpc_ich_wdt_cell, 1, NULL, 0, NULL);
1084
1085 wdt_done:
1086 return ret;
1087 }
1088
lpc_ich_byt_set_writeable(void __iomem * base,void * data)1089 static bool lpc_ich_byt_set_writeable(void __iomem *base, void *data)
1090 {
1091 u32 val;
1092
1093 val = readl(base + BYT_BCR);
1094 if (!(val & BYT_BCR_WPD)) {
1095 val |= BYT_BCR_WPD;
1096 writel(val, base + BYT_BCR);
1097 val = readl(base + BYT_BCR);
1098 }
1099
1100 return val & BYT_BCR_WPD;
1101 }
1102
lpc_ich_lpt_set_writeable(void __iomem * base,void * data)1103 static bool lpc_ich_lpt_set_writeable(void __iomem *base, void *data)
1104 {
1105 struct pci_dev *pdev = data;
1106 u32 bcr;
1107
1108 pci_read_config_dword(pdev, BCR, &bcr);
1109 if (!(bcr & BCR_WPD)) {
1110 bcr |= BCR_WPD;
1111 pci_write_config_dword(pdev, BCR, bcr);
1112 pci_read_config_dword(pdev, BCR, &bcr);
1113 }
1114
1115 return bcr & BCR_WPD;
1116 }
1117
lpc_ich_bxt_set_writeable(void __iomem * base,void * data)1118 static bool lpc_ich_bxt_set_writeable(void __iomem *base, void *data)
1119 {
1120 unsigned int spi = PCI_DEVFN(13, 2);
1121 struct pci_bus *bus = data;
1122 u32 bcr;
1123
1124 pci_bus_read_config_dword(bus, spi, BCR, &bcr);
1125 if (!(bcr & BCR_WPD)) {
1126 bcr |= BCR_WPD;
1127 pci_bus_write_config_dword(bus, spi, BCR, bcr);
1128 pci_bus_read_config_dword(bus, spi, BCR, &bcr);
1129 }
1130
1131 return bcr & BCR_WPD;
1132 }
1133
lpc_ich_init_spi(struct pci_dev * dev)1134 static int lpc_ich_init_spi(struct pci_dev *dev)
1135 {
1136 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1137 struct resource *res = &intel_spi_res[0];
1138 struct intel_spi_boardinfo *info;
1139 u32 spi_base, rcba;
1140
1141 info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL);
1142 if (!info)
1143 return -ENOMEM;
1144
1145 info->type = lpc_chipset_info[priv->chipset].spi_type;
1146
1147 switch (info->type) {
1148 case INTEL_SPI_BYT:
1149 pci_read_config_dword(dev, SPIBASE_BYT, &spi_base);
1150 if (spi_base & SPIBASE_BYT_EN) {
1151 res->start = spi_base & ~(SPIBASE_BYT_SZ - 1);
1152 res->end = res->start + SPIBASE_BYT_SZ - 1;
1153
1154 info->set_writeable = lpc_ich_byt_set_writeable;
1155 }
1156 break;
1157
1158 case INTEL_SPI_LPT:
1159 pci_read_config_dword(dev, RCBABASE, &rcba);
1160 if (rcba & 1) {
1161 spi_base = round_down(rcba, SPIBASE_LPT_SZ);
1162 res->start = spi_base + SPIBASE_LPT;
1163 res->end = res->start + SPIBASE_LPT_SZ - 1;
1164
1165 info->set_writeable = lpc_ich_lpt_set_writeable;
1166 info->data = dev;
1167 }
1168 break;
1169
1170 case INTEL_SPI_BXT: {
1171 unsigned int p2sb = PCI_DEVFN(13, 0);
1172 unsigned int spi = PCI_DEVFN(13, 2);
1173 struct pci_bus *bus = dev->bus;
1174
1175 /*
1176 * The P2SB is hidden by BIOS and we need to unhide it in
1177 * order to read BAR of the SPI flash device. Once that is
1178 * done we hide it again.
1179 */
1180 pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x0);
1181 pci_bus_read_config_dword(bus, spi, PCI_BASE_ADDRESS_0,
1182 &spi_base);
1183 if (spi_base != ~0) {
1184 res->start = spi_base & 0xfffffff0;
1185 res->end = res->start + SPIBASE_APL_SZ - 1;
1186
1187 info->set_writeable = lpc_ich_bxt_set_writeable;
1188 info->data = bus;
1189 }
1190
1191 pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x1);
1192 break;
1193 }
1194
1195 default:
1196 return -EINVAL;
1197 }
1198
1199 if (!res->start)
1200 return -ENODEV;
1201
1202 lpc_ich_spi_cell.platform_data = info;
1203 lpc_ich_spi_cell.pdata_size = sizeof(*info);
1204
1205 return mfd_add_devices(&dev->dev, PLATFORM_DEVID_NONE,
1206 &lpc_ich_spi_cell, 1, NULL, 0, NULL);
1207 }
1208
lpc_ich_probe(struct pci_dev * dev,const struct pci_device_id * id)1209 static int lpc_ich_probe(struct pci_dev *dev,
1210 const struct pci_device_id *id)
1211 {
1212 struct lpc_ich_priv *priv;
1213 int ret;
1214 bool cell_added = false;
1215
1216 priv = devm_kzalloc(&dev->dev,
1217 sizeof(struct lpc_ich_priv), GFP_KERNEL);
1218 if (!priv)
1219 return -ENOMEM;
1220
1221 priv->chipset = id->driver_data;
1222
1223 priv->actrl_pbase_save = -1;
1224 priv->abase_save = -1;
1225
1226 priv->abase = ACPIBASE;
1227 priv->actrl_pbase = ACPICTRL_PMCBASE;
1228
1229 priv->gctrl_save = -1;
1230 if (priv->chipset <= LPC_ICH5) {
1231 priv->gbase = GPIOBASE_ICH0;
1232 priv->gctrl = GPIOCTRL_ICH0;
1233 } else {
1234 priv->gbase = GPIOBASE_ICH6;
1235 priv->gctrl = GPIOCTRL_ICH6;
1236 }
1237
1238 pci_set_drvdata(dev, priv);
1239
1240 if (lpc_chipset_info[priv->chipset].iTCO_version) {
1241 ret = lpc_ich_init_wdt(dev);
1242 if (!ret)
1243 cell_added = true;
1244 }
1245
1246 if (lpc_chipset_info[priv->chipset].gpio_version) {
1247 ret = lpc_ich_init_gpio(dev);
1248 if (!ret)
1249 cell_added = true;
1250 }
1251
1252 if (lpc_chipset_info[priv->chipset].spi_type) {
1253 ret = lpc_ich_init_spi(dev);
1254 if (!ret)
1255 cell_added = true;
1256 }
1257
1258 /*
1259 * We only care if at least one or none of the cells registered
1260 * successfully.
1261 */
1262 if (!cell_added) {
1263 dev_warn(&dev->dev, "No MFD cells added\n");
1264 lpc_ich_restore_config_space(dev);
1265 return -ENODEV;
1266 }
1267
1268 return 0;
1269 }
1270
lpc_ich_remove(struct pci_dev * dev)1271 static void lpc_ich_remove(struct pci_dev *dev)
1272 {
1273 mfd_remove_devices(&dev->dev);
1274 lpc_ich_restore_config_space(dev);
1275 }
1276
1277 static struct pci_driver lpc_ich_driver = {
1278 .name = "lpc_ich",
1279 .id_table = lpc_ich_ids,
1280 .probe = lpc_ich_probe,
1281 .remove = lpc_ich_remove,
1282 };
1283
1284 module_pci_driver(lpc_ich_driver);
1285
1286 MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>");
1287 MODULE_DESCRIPTION("LPC interface for Intel ICH");
1288 MODULE_LICENSE("GPL");
1289