| /drivers/usb/host/ |
| D | ohci-tmio.c | 65 void __iomem *ccr; member
85 tmio_iowrite16(pm, tmio->ccr + CCR_PM); in tmio_write_pm()
110 tmio_iowrite8(0, tmio->ccr + CCR_INTC); in tmio_stop_hc()
111 tmio_iowrite8(0, tmio->ccr + CCR_ILME); in tmio_stop_hc()
112 tmio_iowrite16(0, tmio->ccr + CCR_BASE); in tmio_stop_hc()
113 tmio_iowrite16(0, tmio->ccr + CCR_BASE + 2); in tmio_stop_hc()
114 tmio_iowrite16(pm, tmio->ccr + CCR_PM); in tmio_stop_hc()
124 tmio_iowrite16(base, tmio->ccr + CCR_BASE); in tmio_start_hc()
125 tmio_iowrite16(base >> 16, tmio->ccr + CCR_BASE + 2); in tmio_start_hc()
126 tmio_iowrite8(1, tmio->ccr + CCR_ILME); in tmio_start_hc()
[all …]
|
| /drivers/net/can/sja1000/ |
| D | peak_pcmcia.c | 140 u8 ccr; member
223 if (card->ccr == v) in pcan_write_reg()
225 card->ccr = v; in pcan_write_reg()
343 u8 ccr = card->ccr; in pcan_set_leds() local
349 ccr &= ~PCC_CCR_LED_MASK_CHAN(i); in pcan_set_leds()
351 ccr |= PCC_CCR_LED_CHAN(state, i); in pcan_set_leds()
355 pcan_write_reg(card, PCC_CCR, ccr); in pcan_set_leds()
380 u8 ccr; in pcan_led_timer() local
382 ccr = card->ccr; in pcan_led_timer()
385 ccr &= ~PCC_CCR_LED_MASK_CHAN(i); in pcan_led_timer()
[all …]
|
| /drivers/mtd/nand/raw/ |
| D | ndfc.c | 44 uint32_t ccr; in ndfc_select_chip() local
47 ccr = in_be32(ndfc->ndfcbase + NDFC_CCR); in ndfc_select_chip()
49 ccr &= ~NDFC_CCR_BS_MASK; in ndfc_select_chip()
50 ccr |= NDFC_CCR_BS(chip + ndfc->chip_select); in ndfc_select_chip()
52 ccr |= NDFC_CCR_RESET_CE; in ndfc_select_chip()
53 out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); in ndfc_select_chip()
78 uint32_t ccr; in ndfc_enable_hwecc() local
81 ccr = in_be32(ndfc->ndfcbase + NDFC_CCR); in ndfc_enable_hwecc()
82 ccr |= NDFC_CCR_RESET_ECC; in ndfc_enable_hwecc()
83 out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); in ndfc_enable_hwecc()
[all …]
|
| D | tmio_nand.c | 112 void __iomem *ccr; member
319 tmio_iowrite8(0x81, tmio->ccr + CCR_ICC); in tmio_hw_init()
322 tmio_iowrite16(tmio->fcr_base, tmio->ccr + CCR_BASE); in tmio_hw_init()
323 tmio_iowrite16(tmio->fcr_base >> 16, tmio->ccr + CCR_BASE + 2); in tmio_hw_init()
326 tmio_iowrite8(0x02, tmio->ccr + CCR_COMMAND); in tmio_hw_init()
330 tmio_iowrite8(0x02, tmio->ccr + CCR_NFPSC); in tmio_hw_init()
333 tmio_iowrite8(0x02, tmio->ccr + CCR_NFDC); in tmio_hw_init()
384 struct resource *ccr = platform_get_resource(dev, in tmio_probe() local
413 tmio->ccr = devm_ioremap(&dev->dev, ccr->start, resource_size(ccr)); in tmio_probe()
414 if (!tmio->ccr) in tmio_probe()
|
| /drivers/rtc/ |
| D | rtc-isl12026.c | 207 u8 ccr[8]; in isl12026_rtc_read_time() local
244 msgs[1].len = sizeof(ccr); in isl12026_rtc_read_time()
245 msgs[1].buf = ccr; in isl12026_rtc_read_time()
254 tm->tm_sec = bcd2bin(ccr[0] & 0x7F); in isl12026_rtc_read_time()
255 tm->tm_min = bcd2bin(ccr[1] & 0x7F); in isl12026_rtc_read_time()
256 if (ccr[2] & ISL12026_REG_HR_MIL) in isl12026_rtc_read_time()
257 tm->tm_hour = bcd2bin(ccr[2] & 0x3F); in isl12026_rtc_read_time()
259 tm->tm_hour = bcd2bin(ccr[2] & 0x1F) + in isl12026_rtc_read_time()
260 ((ccr[2] & 0x20) ? 12 : 0); in isl12026_rtc_read_time()
261 tm->tm_mday = bcd2bin(ccr[3] & 0x3F); in isl12026_rtc_read_time()
[all …]
|
| D | rtc-xgene.c | 79 u32 ccr; in xgene_rtc_alarm_irq_enable() local
81 ccr = readl(pdata->csr_base + RTC_CCR); in xgene_rtc_alarm_irq_enable()
83 ccr &= ~RTC_CCR_MASK; in xgene_rtc_alarm_irq_enable()
84 ccr |= RTC_CCR_IE; in xgene_rtc_alarm_irq_enable()
86 ccr &= ~RTC_CCR_IE; in xgene_rtc_alarm_irq_enable()
87 ccr |= RTC_CCR_MASK; in xgene_rtc_alarm_irq_enable()
89 writel(ccr, pdata->csr_base + RTC_CCR); in xgene_rtc_alarm_irq_enable()
|
| D | rtc-armada38x.c | 401 unsigned long ccr, flags; in armada38x_rtc_read_offset() local
405 ccr = rtc->data->read_rtc_reg(rtc, RTC_CCR); in armada38x_rtc_read_offset()
408 ppb_cor = (ccr & RTC_CCR_MODE ? 3815 : 954) * (s8)ccr; in armada38x_rtc_read_offset()
418 unsigned long ccr = 0; in armada38x_rtc_set_offset() local
437 ccr = RTC_CCR_MODE; in armada38x_rtc_set_offset()
445 ccr |= (off & 0x3fff) ^ 0x2000; in armada38x_rtc_set_offset()
446 rtc_delayed_write(ccr, rtc, RTC_CCR); in armada38x_rtc_set_offset()
|
| D | rtc-asm9260.c | 249 u32 ccr; in asm9260_rtc_probe() local
276 ccr = ioread32(priv->iobase + HW_CCR); in asm9260_rtc_probe()
278 if ((ccr & (BM_CLKEN | BM_CTCRST)) != BM_CLKEN) { in asm9260_rtc_probe()
280 ccr = 0; in asm9260_rtc_probe()
283 iowrite32(BM_CLKEN | ccr, priv->iobase + HW_CCR); in asm9260_rtc_probe()
|
| /drivers/dma/ |
| D | txx9dmac.h | 167 u32 ccr; member
239 return (dc->ccr & TXX9_DMA_CCR_INTENT) != 0; in txx9dmac_chan_INTENT()
244 dc->ccr |= TXX9_DMA_CCR_INTENT; in txx9dmac_chan_set_INTENT()
254 dc->ccr |= TXX9_DMA_CCR_SMPCHN; in txx9dmac_chan_set_SMPCHN()
259 u32 sair, u32 dair, u32 ccr) in txx9dmac_desc_set_nosimple() argument
289 u32 sai, u32 dai, u32 ccr) in txx9dmac_desc_set_nosimple() argument
294 desc->hwdesc.CCR = ccr; in txx9dmac_desc_set_nosimple()
298 desc->hwdesc32.CCR = ccr; in txx9dmac_desc_set_nosimple()
|
| D | stm32-mdma.c | 251 u32 ccr; member
428 u32 ccr, cisr, id, reg; in stm32_mdma_disable_chan() local
437 ccr = stm32_mdma_read(dmadev, reg); in stm32_mdma_disable_chan()
438 if (ccr & STM32_MDMA_CCR_EN) { in stm32_mdma_disable_chan()
505 u32 ccr, ctcr, ctbr, tlen; in stm32_mdma_set_xfer_param() local
512 ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)) & ~STM32_MDMA_CCR_EN; in stm32_mdma_set_xfer_param()
555 ccr &= ~(STM32_MDMA_CCR_SWRQ | STM32_MDMA_CCR_WEX | STM32_MDMA_CCR_HEX | in stm32_mdma_set_xfer_param()
557 ccr |= STM32_MDMA_CCR_PL(chan_config->priority_level); in stm32_mdma_set_xfer_param()
665 *mdma_ccr = ccr; in stm32_mdma_set_xfer_param()
733 u32 ccr, ctcr, ctbr; in stm32_mdma_setup_xfer() local
[all …]
|
| D | pl330.c | 237 #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1) argument
238 #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7)) argument
240 #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr)) argument
241 #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr)) argument
551 u32 ccr; member
1213 enum pl330_cond cond = BRST_LEN(pxs->ccr) > 1 ? BURST : SINGLE; in _bursts()
1259 dregs_ccr = pxs->ccr; in _dregs()
1376 u32 ccr = pxs->ccr; in _setup_loops() local
1377 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr); in _setup_loops()
1378 int num_dregs = (x->bytes - BURST_TO_BYTE(bursts, ccr)) / in _setup_loops()
[all …]
|
| D | txx9dmac.c | 365 channel64_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
386 channel32_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
391 channel32_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
759 dc->ccr | TXX9_DMA_CCR_XFACT); in txx9dmac_prep_dma_memcpy()
765 dc->ccr | TXX9_DMA_CCR_XFACT); in txx9dmac_prep_dma_memcpy()
867 dc->ccr | TXX9_DMA_CCR_XFACT); in txx9dmac_prep_slave_sg()
1001 dc->ccr = TXX9_DMA_CCR_IMMCHN | TXX9_DMA_CCR_INTENE | CCR_LE; in txx9dmac_alloc_chan_resources()
1003 if (!txx9_dma_have_SMPCHN() || (dc->ccr & TXX9_DMA_CCR_SMPCHN)) in txx9dmac_alloc_chan_resources()
1004 dc->ccr |= TXX9_DMA_CCR_INTENC; in txx9dmac_alloc_chan_resources()
1008 dc->ccr |= TXX9_DMA_CCR_XFSZ_X8; in txx9dmac_alloc_chan_resources()
[all …]
|
| D | stm32-dmamux.c | 43 u32 ccr[STM32_DMAMUX_MAX_DMA_REQUESTS]; /* Used to backup CCR register member
346 stm32_dmamux->ccr[i] = stm32_dmamux_read(stm32_dmamux->iomem, in stm32_dmamux_suspend()
372 stm32_dmamux->ccr[i]); in stm32_dmamux_resume()
|
| /drivers/spi/ |
| D | spi-mpc512x-psc.c | 97 u32 ccr; in mpc512x_psc_spi_activate_cs() local
120 ccr = in_be32(psc_addr(mps, ccr)); in mpc512x_psc_spi_activate_cs()
121 ccr &= 0xFF000000; in mpc512x_psc_spi_activate_cs()
127 ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8)); in mpc512x_psc_spi_activate_cs()
128 out_be32(psc_addr(mps, ccr), ccr); in mpc512x_psc_spi_activate_cs()
409 u32 ccr; in mpc512x_psc_spi_port_config() local
437 ccr = in_be32(psc_addr(mps, ccr)); in mpc512x_psc_spi_port_config()
438 ccr &= 0xFF000000; in mpc512x_psc_spi_port_config()
441 ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8)); in mpc512x_psc_spi_port_config()
442 out_be32(psc_addr(mps, ccr), ccr); in mpc512x_psc_spi_port_config()
|
| D | spi-mpc52xx-psc.c | 77 u16 ccr; in mpc52xx_psc_spi_activate_cs() local
101 ccr = in_be16((u16 __iomem *)&psc->ccr); in mpc52xx_psc_spi_activate_cs()
102 ccr &= 0xFF00; in mpc52xx_psc_spi_activate_cs()
104 ccr |= (MCLK / cs->speed_hz - 1) & 0xFF; in mpc52xx_psc_spi_activate_cs()
106 ccr |= (MCLK / 1000000 - 1) & 0xFF; in mpc52xx_psc_spi_activate_cs()
107 out_be16((u16 __iomem *)&psc->ccr, ccr); in mpc52xx_psc_spi_activate_cs()
334 out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */ in mpc52xx_psc_spi_port_config()
|
| D | spi-stm32-qspi.c | 368 u32 ccr, cr; in stm32_qspi_send() local
390 ccr = qspi->fmode; in stm32_qspi_send()
391 ccr |= FIELD_PREP(CCR_INST_MASK, op->cmd.opcode); in stm32_qspi_send()
392 ccr |= FIELD_PREP(CCR_IMODE_MASK, in stm32_qspi_send()
396 ccr |= FIELD_PREP(CCR_ADMODE_MASK, in stm32_qspi_send()
398 ccr |= FIELD_PREP(CCR_ADSIZE_MASK, op->addr.nbytes - 1); in stm32_qspi_send()
402 ccr |= FIELD_PREP(CCR_DCYC_MASK, in stm32_qspi_send()
406 ccr |= FIELD_PREP(CCR_DMODE_MASK, in stm32_qspi_send()
410 writel_relaxed(ccr, qspi->io_base + QSPI_CCR); in stm32_qspi_send()
|
| /drivers/mfd/ |
| D | tc6393xb.c | 99 u16 ccr; member
222 u16 ccr; in tc6393xb_ohci_enable() local
227 ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR); in tc6393xb_ohci_enable()
228 ccr |= SCR_CCR_USBCK; in tc6393xb_ohci_enable()
229 tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR); in tc6393xb_ohci_enable()
244 u16 ccr; in tc6393xb_ohci_disable() local
253 ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR); in tc6393xb_ohci_disable()
254 ccr &= ~SCR_CCR_USBCK; in tc6393xb_ohci_disable()
255 tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR); in tc6393xb_ohci_disable()
277 u16 ccr; in tc6393xb_fb_enable() local
[all …]
|
| /drivers/video/fbdev/ |
| D | tmiofb.c | 196 void __iomem *ccr; member
249 tmio_iowrite16(0, par->ccr + CCR_UGCC); in tmiofb_hw_stop()
274 tmio_iowrite16(0x003a, par->ccr + CCR_UGCC); in tmiofb_hw_init()
275 tmio_iowrite16(0x003a, par->ccr + CCR_GCC); in tmiofb_hw_init()
276 tmio_iowrite16(0x3f00, par->ccr + CCR_USC); in tmiofb_hw_init()
280 tmio_iowrite16(0x0000, par->ccr + CCR_USC); in tmiofb_hw_init()
281 tmio_iowrite16(base >> 16, par->ccr + CCR_BASEH); in tmiofb_hw_init()
282 tmio_iowrite16(base, par->ccr + CCR_BASEL); in tmiofb_hw_init()
283 tmio_iowrite16(0x0002, par->ccr + CCR_CMD); /* base address enable */ in tmiofb_hw_init()
284 tmio_iowrite16(0x40a8, par->ccr + CCR_VRAMRTC); /* VRAMRC, VRAMTC */ in tmiofb_hw_init()
[all …]
|
| /drivers/dma/ti/ |
| D | omap-dma.c | 67 uint32_t ccr; member
121 uint32_t ccr; /* CCR value */ member
457 omap_dma_chan_write(c, CCR, d->ccr | CCR_ENABLE); in omap_dma_start()
508 if (!(c->ccr & CCR_BUFFERING_DISABLE)) in omap_dma_stop()
519 if (!(c->ccr & CCR_BUFFERING_DISABLE)) in omap_dma_stop()
587 omap_dma_chan_write(c, CCR, d->ccr); in omap_dma_start_desc()
589 omap_dma_chan_write(c, CCR2, d->ccr >> 16); in omap_dma_start_desc()
739 c->ccr = CCR_OMAP31_DISABLE; in omap_dma_alloc_chan_resources()
741 c->ccr |= c->dma_ch + 1; in omap_dma_alloc_chan_resources()
743 c->ccr = c->dma_sig & 0x1f; in omap_dma_alloc_chan_resources()
[all …]
|
| /drivers/pcmcia/ |
| D | pxa2xx_sharpsl.c | 111 unsigned short cpr, ncpr, ccr, nccr, mcr, nmcr, imr, nimr; in sharpsl_pcmcia_configure_socket() local
131 nccr = (ccr = read_scoop_reg(scoop, SCOOP_CCR)) & ~0x0080; in sharpsl_pcmcia_configure_socket()
168 if (ccr != nccr) in sharpsl_pcmcia_configure_socket()
|
| /drivers/iio/adc/ |
| D | stm32-adc-core.c | 51 u32 ccr; member
303 .ccr = STM32F4_ADC_CCR,
313 .ccr = STM32H7_ADC_CCR,
552 writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr); in stm32_adc_core_hw_start()
574 priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr); in stm32_adc_core_hw_stop()
|
| /drivers/i2c/busses/ |
| D | i2c-stm32f4.c | 228 u32 ccr = 0; in stm32f4_i2c_set_speed_mode() local
269 ccr |= STM32F4_I2C_CCR_FS; in stm32f4_i2c_set_speed_mode()
272 ccr |= STM32F4_I2C_CCR_CCR(val); in stm32f4_i2c_set_speed_mode()
273 writel_relaxed(ccr, i2c_dev->base + STM32F4_I2C_CCR); in stm32f4_i2c_set_speed_mode()
|
| /drivers/pwm/ |
| D | pwm-stm32.c | 114 u32 ccen, ccr; in stm32_pwm_raw_capture() local
124 ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3; in stm32_pwm_raw_capture()
133 ret = stm32_timers_dma_burst_read(parent, priv->capture, dma_id, ccr, 2, in stm32_pwm_raw_capture()
|
| /drivers/hsi/controllers/ |
| D | omap_ssi_port.c | 216 u16 ccr; in ssi_start_dma() local
241 ccr = msg->channel + 0x10 + (port->num * 8); /* Sync */ in ssi_start_dma()
242 ccr |= SSI_DST_AMODE_POSTINC | SSI_SRC_AMODE_CONST | in ssi_start_dma()
258 ccr = (msg->channel + 1 + (port->num * 8)) & 0xf; /* Sync */ in ssi_start_dma()
259 ccr |= SSI_SRC_AMODE_POSTINC | SSI_DST_AMODE_CONST | in ssi_start_dma()
266 lch, csdp, ccr, s_addr, d_addr); in ssi_start_dma()
280 writew(ccr, gdd + SSI_GDD_CCR_REG(lch)); in ssi_start_dma()
|
| /drivers/net/phy/ |
| D | at803x.c | 266 int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG); in at803x_read_page() local
268 if (ccr < 0) in at803x_read_page()
269 return ccr; in at803x_read_page()
271 if (ccr & AT803X_BT_BX_REG_SEL) in at803x_read_page()
|