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Searched refs:csr_offset (Results 1 – 8 of 8) sorted by relevance

/drivers/crypto/qat/qat_common/
Dadf_accel_devices.h202 #define ADF_CSR_WR(csr_base, csr_offset, val) \ argument
203 __raw_writel(val, csr_base + csr_offset)
206 #define ADF_CSR_RD(csr_base, csr_offset) __raw_readl(csr_base + csr_offset) argument
/drivers/net/ethernet/marvell/octeontx2/af/
Dcgx.h43 #define CGXX_CMRX_RX_DMAC_CTL0 (0x1F8 + mac_ops->csr_offset)
49 #define CGXX_CMRX_RX_DMAC_CAM0 (0x200 + mac_ops->csr_offset)
Dlmac_common.h56 u64 csr_offset; member
Drpm.c13 .csr_offset = 0x4e00,
Dcgx.c1574 .csr_offset = 0,
/drivers/firewire/
Dcore.h91 u32 (*read_csr)(struct fw_card *card, int csr_offset);
92 void (*write_csr)(struct fw_card *card, int csr_offset, u32 value);
Dohci.c2656 static u32 ohci_read_csr(struct fw_card *card, int csr_offset) in ohci_read_csr() argument
2662 switch (csr_offset) { in ohci_read_csr()
2707 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value) in ohci_write_csr() argument
2712 switch (csr_offset) { in ohci_write_csr()
/drivers/net/ethernet/cavium/thunder/
Dthunder_bgx.c438 u64 csr_offset, cfg; in bgx_config_timestamping() local
448 csr_offset = BGX_GMP_GMI_RXX_FRM_CTL; in bgx_config_timestamping()
450 csr_offset = BGX_SMUX_RX_FRM_CTL; in bgx_config_timestamping()
452 cfg = bgx_reg_read(bgx, lmacid, csr_offset); in bgx_config_timestamping()
458 bgx_reg_write(bgx, lmacid, csr_offset, cfg); in bgx_config_timestamping()