Home
last modified time | relevance | path

Searched refs:cycles (Results 1 – 25 of 94) sorted by relevance

1234

/drivers/memory/
Djz4780-nemc.c163 uint32_t smcr, val, cycles; in jz4780_nemc_configure_bank() local
209 cycles = jz4780_nemc_ns_to_cycles(nemc, val); in jz4780_nemc_configure_bank()
210 if (cycles > nemc->soc_info->tas_tah_cycles_max) { in jz4780_nemc_configure_bank()
212 val, cycles); in jz4780_nemc_configure_bank()
216 smcr |= cycles << NEMC_SMCR_TAS_SHIFT; in jz4780_nemc_configure_bank()
221 cycles = jz4780_nemc_ns_to_cycles(nemc, val); in jz4780_nemc_configure_bank()
222 if (cycles > nemc->soc_info->tas_tah_cycles_max) { in jz4780_nemc_configure_bank()
224 val, cycles); in jz4780_nemc_configure_bank()
228 smcr |= cycles << NEMC_SMCR_TAH_SHIFT; in jz4780_nemc_configure_bank()
233 cycles = jz4780_nemc_ns_to_cycles(nemc, val); in jz4780_nemc_configure_bank()
[all …]
Dpl172.c61 int cycles; in pl172_timing_prop() local
65 cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start; in pl172_timing_prop()
66 if (cycles < 0) { in pl172_timing_prop()
67 cycles = 0; in pl172_timing_prop()
68 } else if (cycles > max) { in pl172_timing_prop()
73 writel(cycles, pl172->base + reg_offset); in pl172_timing_prop()
/drivers/gpu/drm/i915/gt/
Dselftest_gt_pm.c42 u32 cycles[5]; in measure_clocks() local
47 cycles[i] = -ENGINE_READ_FW(engine, RING_TIMESTAMP); in measure_clocks()
53 cycles[i] += ENGINE_READ_FW(engine, RING_TIMESTAMP); in measure_clocks()
58 sort(cycles, 5, sizeof(*cycles), cmp_u32, NULL); in measure_clocks()
59 *out_cycles = (cycles[1] + 2 * cycles[2] + cycles[3]) / 4; in measure_clocks()
103 u32 cycles; in live_gt_clocks() local
111 measure_clocks(engine, &cycles, &dt); in live_gt_clocks()
113 time = intel_gt_clock_interval_to_ns(engine->gt, cycles); in live_gt_clocks()
117 engine->name, cycles, time, dt, expected, in live_gt_clocks()
127 if (9 * expected < 8 * cycles || 8 * expected > 9 * cycles) { in live_gt_clocks()
Dselftest_engine_cs.c135 u32 cycles[COUNT]; in perf_mi_bb_start() local
154 for (i = 0; i < ARRAY_SIZE(cycles); i++) { in perf_mi_bb_start()
187 cycles[i] = rq->hwsp_seqno[3] - rq->hwsp_seqno[2]; in perf_mi_bb_start()
195 engine->name, trifilter(cycles)); in perf_mi_bb_start()
259 u32 cycles[COUNT]; in perf_mi_noop() local
294 for (i = 0; i < ARRAY_SIZE(cycles); i++) { in perf_mi_noop()
338 cycles[i] = in perf_mi_noop()
349 engine->name, trifilter(cycles)); in perf_mi_noop()
/drivers/net/ethernet/mellanox/mlx4/
Den_clock.c44 container_of(tc, struct mlx4_en_dev, cycles); in mlx4_en_read_clock()
141 mdev->cycles.mult = neg_adj ? mult - diff : mult + diff; in mlx4_en_phc_adjfreq()
210 timecounter_init(&mdev->clock, &mdev->cycles, ns); in mlx4_en_phc_settime()
277 memset(&mdev->cycles, 0, sizeof(mdev->cycles)); in mlx4_en_init_timestamp()
278 mdev->cycles.read = mlx4_en_read_clock; in mlx4_en_init_timestamp()
279 mdev->cycles.mask = CLOCKSOURCE_MASK(48); in mlx4_en_init_timestamp()
280 mdev->cycles.shift = freq_to_shift(dev->caps.hca_core_clock); in mlx4_en_init_timestamp()
281 mdev->cycles.mult = in mlx4_en_init_timestamp()
282 clocksource_khz2mult(1000 * dev->caps.hca_core_clock, mdev->cycles.shift); in mlx4_en_init_timestamp()
283 mdev->nominal_c_mult = mdev->cycles.mult; in mlx4_en_init_timestamp()
[all …]
/drivers/net/wireless/ath/
Dhw.c144 u32 cycles, busy, rx, tx; in ath_hw_cycle_counters_update() local
151 cycles = REG_READ(ah, AR_CCCNT); in ath_hw_cycle_counters_update()
166 common->cc_ani.cycles += cycles; in ath_hw_cycle_counters_update()
171 common->cc_survey.cycles += cycles; in ath_hw_cycle_counters_update()
183 listen_time = (cc->cycles - cc->rx_frame - cc->tx_frame) / in ath_hw_get_listen_time()
/drivers/pwm/
Dpwm-berlin.c96 u64 cycles; in berlin_pwm_config() local
98 cycles = clk_get_rate(bpc->clk); in berlin_pwm_config()
99 cycles *= period_ns; in berlin_pwm_config()
100 do_div(cycles, NSEC_PER_SEC); in berlin_pwm_config()
102 if (cycles > BERLIN_PWM_MAX_TCNT) { in berlin_pwm_config()
104 cycles >>= 12; // Prescaled by 4096 in berlin_pwm_config()
106 if (cycles > BERLIN_PWM_MAX_TCNT) in berlin_pwm_config()
110 period = cycles; in berlin_pwm_config()
111 cycles *= duty_ns; in berlin_pwm_config()
112 do_div(cycles, period_ns); in berlin_pwm_config()
[all …]
Dpwm-atmel.c200 unsigned long long cycles = state->period; in atmel_pwm_calculate_cprd_and_pres() local
204 cycles *= clkrate; in atmel_pwm_calculate_cprd_and_pres()
205 do_div(cycles, NSEC_PER_SEC); in atmel_pwm_calculate_cprd_and_pres()
212 shift = fls(cycles) - atmel_pwm->data->cfg.period_bits; in atmel_pwm_calculate_cprd_and_pres()
219 cycles >>= *pres; in atmel_pwm_calculate_cprd_and_pres()
224 *cprd = cycles; in atmel_pwm_calculate_cprd_and_pres()
233 unsigned long long cycles = state->duty_cycle; in atmel_pwm_calculate_cdty() local
235 cycles *= clkrate; in atmel_pwm_calculate_cdty()
236 do_div(cycles, NSEC_PER_SEC); in atmel_pwm_calculate_cdty()
237 cycles >>= pres; in atmel_pwm_calculate_cdty()
[all …]
/drivers/net/ethernet/mellanox/mlxsw/
Dspectrum_ptp.c64 struct cyclecounter cycles; member
98 container_of(cc, struct mlxsw_sp_ptp_clock, cycles); in mlxsw_sp1_ptp_read_frc()
116 u64 cycles = (u64) nsec; in mlxsw_sp1_ptp_ns2cycles() local
118 cycles <<= tc->cc->shift; in mlxsw_sp1_ptp_ns2cycles()
119 cycles = div_u64(cycles, tc->cc->mult); in mlxsw_sp1_ptp_ns2cycles()
121 return cycles; in mlxsw_sp1_ptp_ns2cycles()
128 u64 next_sec, next_sec_in_nsec, cycles; in mlxsw_sp1_ptp_phc_settime() local
137 cycles = mlxsw_sp1_ptp_ns2cycles(&clock->tc, next_sec_in_nsec); in mlxsw_sp1_ptp_phc_settime()
140 mlxsw_reg_mtpps_vpin_pack(mtpps_pl, cycles); in mlxsw_sp1_ptp_phc_settime()
173 clock->cycles.mult = neg_adj ? clock->nominal_c_mult - diff : in mlxsw_sp1_ptp_adjfine()
[all …]
/drivers/net/ethernet/mellanox/mlx5/core/lib/
Dclock.c119 struct mlx5_timer *timer = container_of(cc, struct mlx5_timer, cycles); in read_internal_timer()
142 clock_info->cycles = timer->tc.cycle_last; in mlx5_update_clock_info_page()
143 clock_info->mult = timer->cycles.mult; in mlx5_update_clock_info_page()
237 timecounter_init(&timer->tc, &timer->cycles, timespec64_to_ns(ts)); in mlx5_ptp_settime()
263 u64 cycles, ns; in mlx5_ptp_gettimex() local
272 cycles = mlx5_read_time(mdev, sts, false); in mlx5_ptp_gettimex()
273 ns = timecounter_cyc2time(&timer->tc, cycles); in mlx5_ptp_gettimex()
365 timer->cycles.mult = neg_adj ? timer->nominal_c_mult - diff : in mlx5_ptp_adjfreq()
449 cycles_delta = div64_u64(nsec_delta << timer->cycles.shift, in find_target_cycles()
450 timer->cycles.mult); in find_target_cycles()
[all …]
/drivers/char/hw_random/
Dcavium-rng-vf.c85 u64 status, cycles; in check_rng_health() local
99 cycles = status >> 1; in check_rng_health()
100 if (!cycles) in check_rng_health()
109 cycles = cycles / 2; in check_rng_health()
110 cur_err = (cycles * 1000000000) / rng->clock_rate; /* In nanosec */ in check_rng_health()
/drivers/clocksource/
Dexynos_mct.c270 static void exynos4_mct_comp0_start(bool periodic, unsigned long cycles) in exynos4_mct_comp0_start() argument
279 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR); in exynos4_mct_comp0_start()
282 comp_cycle = exynos4_read_count_64() + cycles; in exynos4_mct_comp0_start()
292 static int exynos4_comp_set_next_event(unsigned long cycles, in exynos4_comp_set_next_event() argument
295 exynos4_mct_comp0_start(false, cycles); in exynos4_comp_set_next_event()
370 static void exynos4_mct_tick_start(unsigned long cycles, in exynos4_mct_tick_start() argument
377 tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */ in exynos4_mct_tick_start()
398 static int exynos4_tick_set_next_event(unsigned long cycles, in exynos4_tick_set_next_event() argument
404 exynos4_mct_tick_start(cycles, mevt); in exynos4_tick_set_next_event()
Dtimer-sprd.c60 static void sprd_timer_update_counter(void __iomem *base, unsigned long cycles) in sprd_timer_update_counter() argument
62 writel_relaxed(cycles & TIMER_VALUE_LO_MASK, base + TIMER_LOAD_LO); in sprd_timer_update_counter()
79 static int sprd_timer_set_next_event(unsigned long cycles, in sprd_timer_set_next_event() argument
85 sprd_timer_update_counter(timer_of_base(to), cycles); in sprd_timer_set_next_event()
Dtimer-rda.c35 static int rda_ostimer_start(void __iomem *base, bool periodic, u64 cycles) in rda_ostimer_start() argument
39 load_l = (u32)cycles; in rda_ostimer_start()
40 ctrl = ((cycles >> 32) & 0xffffff); in rda_ostimer_start()
Dtimer-rockchip.c65 static void rk_timer_update_counter(unsigned long cycles, in rk_timer_update_counter() argument
68 writel_relaxed(cycles, timer->base + TIMER_LOAD_COUNT0); in rk_timer_update_counter()
77 static inline int rk_timer_set_next_event(unsigned long cycles, in rk_timer_set_next_event() argument
83 rk_timer_update_counter(cycles, timer); in rk_timer_set_next_event()
Dtimer-davinci.c138 davinci_clockevent_set_next_event_std(unsigned long cycles, in davinci_clockevent_set_next_event_std() argument
146 davinci_clockevent_write(clockevent, DAVINCI_TIMER_REG_PRD12, cycles); in davinci_clockevent_set_next_event_std()
154 davinci_clockevent_set_next_event_cmp(unsigned long cycles, in davinci_clockevent_set_next_event_cmp() argument
163 clockevent->cmp_off, curr_time + cycles); in davinci_clockevent_set_next_event_cmp()
/drivers/siox/
Dsiox-bus-gpio.c34 size_t cycles = max(setbuf_len, getbuf_len); in siox_gpio_pushpull() local
44 for (i = 0; i < cycles; ++i) { in siox_gpio_pushpull()
48 if (i >= cycles - setbuf_len) in siox_gpio_pushpull()
49 set = setbuf[i - (cycles - setbuf_len)]; in siox_gpio_pushpull()
/drivers/soc/ixp4xx/
Dixp4xx-npe.c410 int cycles = 0; in npe_send_message() local
429 while ((cycles < MAX_RETRIES) && in npe_send_message()
432 cycles++; in npe_send_message()
435 if (cycles == MAX_RETRIES) { in npe_send_message()
441 debug_msg(npe, "Sending a message took %i cycles\n", cycles); in npe_send_message()
449 int cycles = 0, cnt = 0; in npe_recv_message() local
453 while (cycles < MAX_RETRIES) { in npe_recv_message()
460 cycles++; in npe_recv_message()
473 if (cycles == MAX_RETRIES) { in npe_recv_message()
479 debug_msg(npe, "Receiving a message took %i cycles\n", cycles); in npe_recv_message()
/drivers/gpu/drm/i915/selftests/
Di915_request.c1809 static u64 cycles_to_ns(struct intel_engine_cs *engine, u32 cycles) in cycles_to_ns() argument
1811 u64 ns = intel_gt_clock_interval_to_ns(engine->gt, cycles); in cycles_to_ns()
1875 u32 elapsed[TF_COUNT], cycles; in measure_semaphore_response() local
1922 cycles = ENGINE_READ_FW(ce->engine, RING_TIMESTAMP); in measure_semaphore_response()
1931 elapsed[i - 1] = sema[i] - cycles; in measure_semaphore_response()
1934 cycles = trifilter(elapsed); in measure_semaphore_response()
1936 ce->engine->name, cycles >> TF_BIAS, in measure_semaphore_response()
1937 cycles_to_ns(ce->engine, cycles)); in measure_semaphore_response()
1950 u32 elapsed[TF_COUNT], cycles; in measure_idle_dispatch() local
2005 cycles = trifilter(elapsed); in measure_idle_dispatch()
[all …]
/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
Dfan.c129 u32 cycles, cur, prev; in nvkm_therm_fan_sense() local
145 cycles = 0; in nvkm_therm_fan_sense()
154 cycles++; in nvkm_therm_fan_sense()
157 } while (cycles < 5 && nvkm_timer_read(tmr) - start < 250000000); in nvkm_therm_fan_sense()
160 if (cycles == 5) { in nvkm_therm_fan_sense()
/drivers/gpu/drm/bridge/
Dnwl-dsi.c215 u32 cycles; in nwl_dsi_config_host() local
233 cycles = ui2bc(cfg->clk_pre); in nwl_dsi_config_host()
234 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_pre: 0x%x\n", cycles); in nwl_dsi_config_host()
235 nwl_dsi_write(dsi, NWL_DSI_CFG_T_PRE, cycles); in nwl_dsi_config_host()
236 cycles = ps2bc(dsi, cfg->lpx + cfg->clk_prepare + cfg->clk_zero); in nwl_dsi_config_host()
237 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap (pre): 0x%x\n", cycles); in nwl_dsi_config_host()
238 cycles += ui2bc(cfg->clk_pre); in nwl_dsi_config_host()
239 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_post: 0x%x\n", cycles); in nwl_dsi_config_host()
240 nwl_dsi_write(dsi, NWL_DSI_CFG_T_POST, cycles); in nwl_dsi_config_host()
241 cycles = ps2bc(dsi, cfg->hs_exit); in nwl_dsi_config_host()
[all …]
/drivers/gpu/drm/v3d/
Dv3d_debugfs.c217 uint32_t cycles; in v3d_measure_clock() local
241 cycles = V3D_CORE_READ(core, V3D_PCTR_0_PCTR0); in v3d_measure_clock()
244 cycles, in v3d_measure_clock()
245 cycles / (measure_ms * 1000), in v3d_measure_clock()
246 (cycles / (measure_ms * 100)) % 10); in v3d_measure_clock()
/drivers/media/usb/gspca/stv06xx/
Dstv06xx_hdcs.c176 int cycles, err; in hdcs_set_exposure() local
179 cycles = val * HDCS_CLK_FREQ_MHZ * 257; in hdcs_set_exposure()
187 rowexp = cycles / rp; in hdcs_set_exposure()
190 cycles -= rowexp * rp; in hdcs_set_exposure()
195 srowexp = hdcs->w - (cycles + hdcs->exp.er + 13) / ct; in hdcs_set_exposure()
201 srowexp = cp - hdcs->exp.er - 6 - cycles; in hdcs_set_exposure()
/drivers/firewire/
Dcore-transaction.c732 unsigned int cycles; in compute_split_timeout_timestamp() local
735 cycles = card->split_timeout_cycles; in compute_split_timeout_timestamp()
736 cycles += request_timestamp & 0x1fff; in compute_split_timeout_timestamp()
739 timestamp += (cycles / 8000) << 13; in compute_split_timeout_timestamp()
740 timestamp |= cycles % 8000; in compute_split_timeout_timestamp()
1075 unsigned int cycles; in update_split_timeout() local
1077 cycles = card->split_timeout_hi * 8000 + (card->split_timeout_lo >> 19); in update_split_timeout()
1080 cycles = clamp(cycles, 800u, 3u * 8000u); in update_split_timeout()
1082 card->split_timeout_cycles = cycles; in update_split_timeout()
1083 card->split_timeout_jiffies = DIV_ROUND_UP(cycles * HZ, 8000); in update_split_timeout()
/drivers/net/ethernet/ti/
Dam65-cpts.c515 u64 cycles; in am65_cpts_estf_enable() local
518 cycles = cfg->ns_period * cpts->refclk_freq; in am65_cpts_estf_enable()
519 cycles = DIV_ROUND_UP(cycles, NSEC_PER_SEC); in am65_cpts_estf_enable()
520 if (cycles > U32_MAX) in am65_cpts_estf_enable()
530 val = lower_32_bits(cycles); in am65_cpts_estf_enable()
550 u64 ns_period, ns_start, cycles; in am65_cpts_perout_enable_hw() local
559 cycles = (ns_period * cpts->refclk_freq) / NSEC_PER_SEC; in am65_cpts_perout_enable_hw()
569 val = lower_32_bits(cycles); in am65_cpts_perout_enable_hw()

1234