| /drivers/gpu/drm/omapdrm/dss/ |
| D | dispc.c | 50 #define REG_GET(dispc, idx, start, end) \ argument
51 FLD_GET(dispc_read_reg(dispc, idx), start, end)
53 #define REG_FLD_MOD(dispc, idx, val, start, end) \ argument
54 dispc_write_reg(dispc, idx, \
55 FLD_MOD(dispc_read_reg(dispc, idx), val, start, end))
100 int (*calc_scaling)(struct dispc_device *dispc,
342 static unsigned long dispc_fclk_rate(struct dispc_device *dispc);
343 static unsigned long dispc_core_clk_rate(struct dispc_device *dispc);
344 static unsigned long dispc_mgr_lclk_rate(struct dispc_device *dispc,
346 static unsigned long dispc_mgr_pclk_rate(struct dispc_device *dispc,
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| D | dss.h | 259 struct dispc_device *dispc; member
389 void dispc_dump_clocks(struct dispc_device *dispc, struct seq_file *s);
391 int dispc_runtime_get(struct dispc_device *dispc);
392 void dispc_runtime_put(struct dispc_device *dispc);
394 int dispc_get_num_ovls(struct dispc_device *dispc);
395 int dispc_get_num_mgrs(struct dispc_device *dispc);
397 const u32 *dispc_ovl_get_color_modes(struct dispc_device *dispc,
400 u32 dispc_read_irqstatus(struct dispc_device *dispc);
401 void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask);
402 void dispc_write_irqenable(struct dispc_device *dispc, u32 mask);
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| D | dpi.c | 178 static bool dpi_calc_hsdiv_cb(int m_dispc, unsigned long dispc, in dpi_calc_hsdiv_cb() argument
184 ctx->pll_cinfo.clkout[ctx->clkout_idx] = dispc; in dpi_calc_hsdiv_cb()
186 return dispc_div_calc(ctx->dpi->dss->dispc, dispc, in dpi_calc_hsdiv_cb()
214 return dispc_div_calc(ctx->dpi->dss->dispc, fck, in dpi_calc_dss_cb()
494 r = dispc_runtime_get(dpi->dss->dispc); in dpi_bridge_enable()
528 dispc_runtime_put(dpi->dss->dispc); in dpi_bridge_enable()
546 dispc_runtime_put(dpi->dss->dispc); in dpi_bridge_disable()
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| D | sdi.c | 68 return dispc_div_calc(ctx->sdi->dss->dispc, fck, in dpi_calc_dss_cb()
209 r = dispc_runtime_get(sdi->dss->dispc); in sdi_bridge_enable()
236 dispc_mgr_set_clock_div(sdi->dss->dispc, sdi->output.dispc_channel, in sdi_bridge_enable()
256 dispc_runtime_put(sdi->dss->dispc); in sdi_bridge_enable()
269 dispc_runtime_put(sdi->dss->dispc); in sdi_bridge_disable()
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| D | dss.c | 266 dispc_pck_free_enable(dss->dispc, 1); in dss_sdi_enable()
296 dispc_lcd_enable_signal(dss->dispc, 1); in dss_sdi_enable()
310 dispc_lcd_enable_signal(dss->dispc, 0); in dss_sdi_enable()
315 dispc_pck_free_enable(dss->dispc, 0); in dss_sdi_enable()
322 dispc_lcd_enable_signal(dss->dispc, 0); in dss_sdi_disable()
324 dispc_pck_free_enable(dss->dispc, 0); in dss_sdi_disable()
385 dispc_dump_clocks(dss->dispc, s); in dss_debug_dump_clocks()
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| D | dsi.c | 934 dispc_pck_free_enable(dsi->dss->dispc, 1); in dsi_pll_enable()
939 dispc_pck_free_enable(dsi->dss->dispc, 0); in dsi_pll_enable()
945 dispc_pck_free_enable(dsi->dss->dispc, 0); in dsi_pll_enable()
3145 dispc_disable_sidle(dsi->dss->dispc); in dsi_update_screen_dispc()
3178 dispc_enable_sidle(dsi->dss->dispc); in dsi_handle_framedone()
3316 r = dispc_calc_clock_rates(dsi->dss->dispc, fck, &dispc_cinfo); in dsi_configure_dispc_clocks()
3682 static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, in dsi_cm_calc_hsdiv_cb() argument
3688 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; in dsi_cm_calc_hsdiv_cb()
3690 return dispc_div_calc(ctx->dsi->dss->dispc, dispc, in dsi_cm_calc_hsdiv_cb()
3971 static bool dsi_vm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, in dsi_vm_calc_hsdiv_cb() argument
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| D | base.c | 21 return dss->dispc; in dispc_get_dispc()
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| /drivers/gpu/drm/tidss/ |
| D | tidss_dispc.c | 310 static void dispc_write(struct dispc_device *dispc, u16 reg, u32 val) in dispc_write() argument
312 iowrite32(val, dispc->base_common + reg); in dispc_write()
315 static u32 dispc_read(struct dispc_device *dispc, u16 reg) in dispc_read() argument
317 return ioread32(dispc->base_common + reg); in dispc_read()
321 void dispc_vid_write(struct dispc_device *dispc, u32 hw_plane, u16 reg, u32 val) in dispc_vid_write() argument
323 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_write()
328 static u32 dispc_vid_read(struct dispc_device *dispc, u32 hw_plane, u16 reg) in dispc_vid_read() argument
330 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_read()
335 static void dispc_ovr_write(struct dispc_device *dispc, u32 hw_videoport, in dispc_ovr_write() argument
338 void __iomem *base = dispc->base_ovr[hw_videoport]; in dispc_ovr_write()
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| D | tidss_dispc.h | 92 void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask);
93 dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc);
95 void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane,
97 void dispc_ovr_enable_layer(struct dispc_device *dispc,
100 void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport,
102 void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport,
104 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport);
105 void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport);
106 bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport);
107 void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport);
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| D | tidss_crtc.c | 40 busy = dispc_vp_go_busy(tidss->dispc, tcrtc->hw_videoport); in tidss_crtc_finish_page_flip()
94 struct dispc_device *dispc = tidss->dispc; in tidss_crtc_atomic_check() local
107 ok = dispc_vp_mode_valid(dispc, hw_videoport, mode); in tidss_crtc_atomic_check()
114 return dispc_vp_bus_check(dispc, hw_videoport, crtc_state); in tidss_crtc_atomic_check()
155 dispc_ovr_set_plane(tidss->dispc, tplane->hw_plane_id, in tidss_crtc_position_planes()
160 dispc_ovr_enable_layer(tidss->dispc, tcrtc->hw_videoport, layer, in tidss_crtc_position_planes()
192 if (WARN_ON(dispc_vp_go_busy(tidss->dispc, tcrtc->hw_videoport))) in tidss_crtc_atomic_flush()
200 dispc_vp_setup(tidss->dispc, tcrtc->hw_videoport, crtc->state, false); in tidss_crtc_atomic_flush()
208 dispc_vp_go(tidss->dispc, tcrtc->hw_videoport); in tidss_crtc_atomic_flush()
234 r = dispc_vp_set_clk_rate(tidss->dispc, tcrtc->hw_videoport, in tidss_crtc_atomic_enable()
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| D | tidss_plane.c | 99 ret = dispc_plane_check(tidss->dispc, hw_plane, new_plane_state, in tidss_plane_atomic_check()
121 dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false); in tidss_plane_atomic_update()
127 ret = dispc_plane_setup(tidss->dispc, tplane->hw_plane_id, in tidss_plane_atomic_update()
133 dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false); in tidss_plane_atomic_update()
137 dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, true); in tidss_plane_atomic_update()
149 dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false); in tidss_plane_atomic_disable()
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| D | tidss_irq.c | 23 dispc_set_irqenable(tidss->dispc, tidss->irq_mask); in tidss_irq_update()
63 irqstatus = dispc_read_and_clear_irqstatus(tidss->dispc); in tidss_irq_handler()
104 dispc_set_irqenable(tidss->dispc, 0); in tidss_irq_preinstall()
105 dispc_read_and_clear_irqstatus(tidss->dispc); in tidss_irq_preinstall()
160 dispc_set_irqenable(tidss->dispc, 0); in tidss_irq_uninstall()
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| D | tidss_drv.c | 56 return dispc_runtime_suspend(tidss->dispc); in tidss_pm_runtime_suspend()
66 r = dispc_runtime_resume(tidss->dispc); in tidss_pm_runtime_resume()
154 dispc_runtime_resume(tidss->dispc); in tidss_probe()
198 dispc_runtime_suspend(tidss->dispc); in tidss_probe()
221 dispc_runtime_suspend(tidss->dispc); in tidss_remove()
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| D | tidss_drv.h | 22 struct dispc_device *dispc; member
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| /drivers/gpu/drm/omapdrm/ |
| D | omap_irq.c | 32 dispc_write_irqenable(priv->dispc, irqmask); in omap_irq_update()
86 dispc_mgr_get_framedone_irq(priv->dispc, channel); in omap_irq_enable_framedone()
123 priv->irq_mask |= dispc_mgr_get_vsync_irq(priv->dispc, in omap_irq_enable_vblank()
149 priv->irq_mask &= ~dispc_mgr_get_vsync_irq(priv->dispc, in omap_irq_disable_vblank()
214 irqstatus = dispc_read_irqstatus(priv->dispc); in omap_irq_handler()
215 dispc_clear_irqstatus(priv->dispc, irqstatus); in omap_irq_handler()
216 dispc_read_irqstatus(priv->dispc); /* flush posted write */ in omap_irq_handler()
224 if (irqstatus & dispc_mgr_get_vsync_irq(priv->dispc, channel)) { in omap_irq_handler()
229 if (irqstatus & dispc_mgr_get_sync_lost_irq(priv->dispc, channel)) in omap_irq_handler()
232 if (irqstatus & dispc_mgr_get_framedone_irq(priv->dispc, channel)) in omap_irq_handler()
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| D | omap_crtc.c | 106 dispc_mgr_enable(priv->dispc, channel, true); in omap_crtc_dss_start_update()
131 dispc_mgr_enable(priv->dispc, channel, enable); in omap_crtc_set_enabled()
144 framedone_irq = dispc_mgr_get_framedone_irq(priv->dispc, in omap_crtc_set_enabled()
146 vsync_irq = dispc_mgr_get_vsync_irq(priv->dispc, channel); in omap_crtc_set_enabled()
166 dispc_mgr_enable(priv->dispc, channel, enable); in omap_crtc_set_enabled()
188 dispc_mgr_set_timings(priv->dispc, omap_crtc->channel, in omap_crtc_dss_enable()
222 dispc_mgr_set_lcd_config(priv->dispc, omap_crtc->channel, in omap_crtc_dss_set_lcd_config()
291 if (dispc_mgr_go_busy(priv->dispc, omap_crtc->channel)) { in omap_crtc_vblank_irq()
417 dispc_mgr_setup(priv->dispc, omap_crtc->channel, &info); in omap_crtc_write_crtc_properties()
458 dispc_runtime_get(priv->dispc); in omap_crtc_atomic_enable()
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| D | omap_plane.c | 80 ret = dispc_ovl_setup(priv->dispc, omap_plane->id, &info, in omap_plane_atomic_update()
86 dispc_ovl_enable(priv->dispc, omap_plane->id, false); in omap_plane_atomic_update()
90 dispc_ovl_enable(priv->dispc, omap_plane->id, true); in omap_plane_atomic_update()
104 dispc_ovl_enable(priv->dispc, omap_plane->id, false); in omap_plane_atomic_disable()
252 const u32 *formats = dispc_ovl_get_color_modes(priv->dispc, omap_plane->id); in omap_plane_supports_yuv()
284 unsigned int num_planes = dispc_get_num_ovls(priv->dispc); in omap_plane_init()
303 formats = dispc_ovl_get_color_modes(priv->dispc, id); in omap_plane_init()
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| D | omap_drv.c | 72 dispc_runtime_get(priv->dispc); in omap_atomic_commit_tail()
116 dispc_runtime_put(priv->dispc); in omap_atomic_commit_tail()
195 unsigned int num_planes = dispc_get_num_ovls(priv->dispc); in omap_modeset_init_properties()
224 int num_ovls = dispc_get_num_ovls(priv->dispc); in omap_modeset_init()
225 int num_mgrs = dispc_get_num_mgrs(priv->dispc); in omap_modeset_init()
569 priv->dispc = dispc_get_dispc(priv->dss); in omapdrm_init()
581 priv->max_bandwidth = dispc_get_memory_bandwidth_limit(priv->dispc); in omapdrm_init()
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| D | omap_drv.h | 49 struct dispc_device *dispc; member
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| D | Makefile | 21 omapdrm-y += dss/base.o dss/output.o dss/dss.o dss/dispc.o \
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| /drivers/video/fbdev/omap2/omapfb/dss/ |
| D | dispc.c | 127 } dispc; variable
253 __raw_writel(val, dispc.base + idx); in dispc_write_reg()
258 return __raw_readl(dispc.base + idx); in dispc_read_reg()
274 spin_lock_irqsave(&dispc.control_lock, flags); in mgr_fld_write()
279 spin_unlock_irqrestore(&dispc.control_lock, flags); in mgr_fld_write()
283 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
285 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
389 dispc.ctx_valid = true; in dispc_save_context()
400 if (!dispc.ctx_valid) in dispc_restore_context()
522 r = pm_runtime_get_sync(&dispc.pdev->dev); in dispc_runtime_get()
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| D | Makefile | 5 omapdss-y := core.o dss.o dss_features.o dispc.o dispc_coefs.o display.o \
9 dispc-compat.o display-sysfs.o
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| D | dpi.c | 172 static bool dpi_calc_hsdiv_cb(int m_dispc, unsigned long dispc, in dpi_calc_hsdiv_cb() argument
186 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; in dpi_calc_hsdiv_cb()
188 return dispc_div_calc(dispc, ctx->pck_min, ctx->pck_max, in dpi_calc_hsdiv_cb()
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| D | dss.h | 374 bool dispc_div_calc(unsigned long dispc,
459 typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
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| D | Kconfig | 24 dispc, dsi, hdmi and rfbi.
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