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Searched refs:dpll (Results 1 – 25 of 44) sorted by relevance

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/drivers/gpu/drm/i915/display/
Dintel_dpll.c300 int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params()
312 static u32 i9xx_dpll_compute_m(struct dpll *dpll) in i9xx_dpll_compute_m() argument
314 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
317 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params()
329 int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params()
341 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params()
360 const struct dpll *clock) in intel_pll_is_valid()
431 int target, int refclk, struct dpll *match_clock, in i9xx_find_best_dpll()
432 struct dpll *best_clock) in i9xx_find_best_dpll()
435 struct dpll clock; in i9xx_find_best_dpll()
[all …]
Dintel_dpll.h11 struct dpll;
18 int vlv_calc_dpll_params(int refclk, struct dpll *clock);
19 int pnv_calc_dpll_params(int refclk, struct dpll *clock);
20 int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
27 const struct dpll *dpll);
43 struct dpll *best_clock);
44 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
Dintel_dpll_mgr.c73 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) { in intel_atomic_duplicate_dpll_state()
74 struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i]; in intel_atomic_duplicate_dpll_state()
109 return &dev_priv->dpll.shared_dplls[id]; in intel_get_shared_dpll_by_id()
124 long pll_idx = pll - dev_priv->dpll.shared_dplls; in intel_get_shared_dpll_id()
128 pll_idx >= dev_priv->dpll.num_shared_dpll)) in intel_get_shared_dpll_id()
203 mutex_lock(&dev_priv->dpll.lock); in intel_prepare_shared_dpll()
212 mutex_unlock(&dev_priv->dpll.lock); in intel_prepare_shared_dpll()
232 mutex_lock(&dev_priv->dpll.lock); in intel_enable_shared_dpll()
258 mutex_unlock(&dev_priv->dpll.lock); in intel_enable_shared_dpll()
281 mutex_lock(&dev_priv->dpll.lock); in intel_disable_shared_dpll()
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Dintel_dvo.c454 u32 dpll[I915_MAX_PIPES]; in intel_dvo_init() local
491 dpll[pipe] = intel_de_read(dev_priv, DPLL(pipe)); in intel_dvo_init()
493 dpll[pipe] | DPLL_DVO_2X_MODE); in intel_dvo_init()
500 intel_de_write(dev_priv, DPLL(pipe), dpll[pipe]); in intel_dvo_init()
Dintel_display_types.h568 struct dpll { struct
1031 struct dpll dpll; member
2051 static inline u32 i9xx_dpll_compute_fp(struct dpll *dpll) in i9xx_dpll_compute_fp() argument
2053 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; in i9xx_dpll_compute_fp()
Dg4x_dp.h20 const struct dpll *vlv_get_dpll(struct drm_i915_private *i915);
Dg4x_dp.c25 struct dpll dpll; member
65 const struct dpll *vlv_get_dpll(struct drm_i915_private *i915) in vlv_get_dpll()
67 return IS_CHERRYVIEW(i915) ? &chv_dpll[0].dpll : &vlv_dpll[0].dpll; in vlv_get_dpll()
94 pipe_config->dpll = divisor[i].dpll; in g4x_dp_set_clock()
Dintel_dpll_mgr.h187 u32 dpll; member
Dintel_display.c4812 struct dpll clock; in vlv_crtc_clock_get()
4817 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in vlv_crtc_clock_get()
4840 struct dpll clock; in chv_crtc_clock_get()
4845 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in chv_crtc_clock_get()
4991 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, in i9xx_get_pipe_config()
5000 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | in i9xx_get_pipe_config()
5066 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) { in ilk_init_pch_refclk()
5973 tmp = pipe_config->dpll_hw_state.dpll; in ilk_get_pipe_config()
6547 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_pll_refclk() local
6549 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) in i9xx_pll_refclk()
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Dicl_dsi.c665 mutex_lock(&dev_priv->dpll.lock); in gen11_dsi_gate_clocks()
671 mutex_unlock(&dev_priv->dpll.lock); in gen11_dsi_gate_clocks()
681 mutex_lock(&dev_priv->dpll.lock); in gen11_dsi_ungate_clocks()
687 mutex_unlock(&dev_priv->dpll.lock); in gen11_dsi_ungate_clocks()
717 mutex_lock(&dev_priv->dpll.lock); in gen11_dsi_map_pll()
733 mutex_unlock(&dev_priv->dpll.lock); in gen11_dsi_map_pll()
/drivers/gpu/drm/gma500/
Dpsb_intel_display.c105 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in psb_intel_crtc_mode_set() local
152 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
154 dpll |= DPLLB_MODE_LVDS; in psb_intel_crtc_mode_set()
155 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
157 dpll |= DPLLB_MODE_DAC_SERIAL; in psb_intel_crtc_mode_set()
161 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
162 dpll |= in psb_intel_crtc_mode_set()
167 dpll |= (1 << (clock.p1 - 1)) << 16; in psb_intel_crtc_mode_set()
170 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in psb_intel_crtc_mode_set()
173 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in psb_intel_crtc_mode_set()
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Doaktrail_crtc.c242 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
244 REG_WRITE_WITH_AUX(map->dpll, temp, i); in oaktrail_crtc_dpms()
245 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
248 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
250 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
253 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
255 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
314 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
316 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
318 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
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Dcdv_intel_display.c583 u32 dpll = 0, dspcntr, pipeconf; in cdv_intel_crtc_mode_set() local
659 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
670 dpll |= DPLL_SYNCLOCK_ENABLE; in cdv_intel_crtc_mode_set()
716 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
717 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
752 dpll |= DPLL_VCO_ENABLE; in cdv_intel_crtc_mode_set()
761 REG_WRITE(map->dpll, in cdv_intel_crtc_mode_set()
762 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); in cdv_intel_crtc_mode_set()
763 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
767 if (!(REG_READ(map->dpll) & DPLL_LOCK)) { in cdv_intel_crtc_mode_set()
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Dgma_display.c215 temp = REG_READ(map->dpll); in gma_crtc_dpms()
217 REG_WRITE(map->dpll, temp); in gma_crtc_dpms()
218 REG_READ(map->dpll); in gma_crtc_dpms()
221 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
222 REG_READ(map->dpll); in gma_crtc_dpms()
225 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
226 REG_READ(map->dpll); in gma_crtc_dpms()
303 temp = REG_READ(map->dpll); in gma_crtc_dpms()
305 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); in gma_crtc_dpms()
306 REG_READ(map->dpll); in gma_crtc_dpms()
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Doaktrail_hdmi.c282 u32 dspcntr, pipeconf, dpll, temp; in oaktrail_crtc_hdmi_mode_set() local
292 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
293 if ((dpll & DPLL_PWRDN) == 0) { in oaktrail_crtc_hdmi_mode_set()
294 REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET)); in oaktrail_crtc_hdmi_mode_set()
308 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
309 dpll &= ~DPLL_PDIV_MASK; in oaktrail_crtc_hdmi_mode_set()
310 dpll &= ~(DPLL_PWRDN | DPLL_RESET); in oaktrail_crtc_hdmi_mode_set()
314 REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN)); in oaktrail_crtc_hdmi_mode_set()
Doaktrail_device.c199 p->dpll = PSB_RVDC32(MRST_DPLL_A); in oaktrail_save_display_registers()
316 PSB_WVDC32(p->dpll, MRST_DPLL_A); in oaktrail_restore_display_registers()
457 .dpll = MRST_DPLL_A,
481 .dpll = DPLL_B,
Dpsb_device.c257 .dpll = DPLL_A,
281 .dpll = DPLL_B,
/drivers/ata/
Dpata_hpt3x2n.c317 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_defer() local
324 if ((flags & USE_DPLL) != dpll && alt->qc_active) in hpt3x2n_qc_defer()
333 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_issue() local
335 if ((flags & USE_DPLL) != dpll) { in hpt3x2n_qc_issue()
337 flags |= dpll; in hpt3x2n_qc_issue()
340 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); in hpt3x2n_qc_issue()
Dpata_hpt37x.c996 int dpll, adjust; in hpt37x_init_one() local
999 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2; in hpt37x_init_one()
1001 f_low = (MHz[clock_slot] * 48) / MHz[dpll]; in hpt37x_init_one()
1029 if (dpll == 3) in hpt37x_init_one()
1035 MHz[clock_slot], MHz[dpll]); in hpt37x_init_one()
/drivers/gpu/drm/rcar-du/
Drcar_du_crtc.c85 struct dpll_info *dpll, in rcar_du_dpll_divider() argument
149 dpll->n = n; in rcar_du_dpll_divider()
150 dpll->m = m; in rcar_du_dpll_divider()
151 dpll->fdpll = fdpll; in rcar_du_dpll_divider()
152 dpll->output = output; in rcar_du_dpll_divider()
164 dpll->output, dpll->fdpll, dpll->n, dpll->m, best_diff); in rcar_du_dpll_divider()
224 struct dpll_info dpll = { 0 }; in rcar_du_crtc_set_display_timing() local
248 rcar_du_dpll_divider(rcrtc, &dpll, extclk, target); in rcar_du_crtc_set_display_timing()
251 | DPLLCR_FDPLL(dpll.fdpll) in rcar_du_crtc_set_display_timing()
252 | DPLLCR_N(dpll.n) | DPLLCR_M(dpll.m) in rcar_du_crtc_set_display_timing()
/drivers/ptp/
Dptp_clockmatrix.c341 u8 dpll = 0; in wait_for_sys_apll_dpll_lock() local
349 err = read_sys_dpll_status(idtcm, &dpll); in wait_for_sys_apll_dpll_lock()
354 dpll &= DPLL_SYS_STATE_MASK; in wait_for_sys_apll_dpll_lock()
357 dpll == DPLL_STATE_LOCKED) { in wait_for_sys_apll_dpll_lock()
359 } else if (dpll == DPLL_STATE_FREERUN || in wait_for_sys_apll_dpll_lock()
360 dpll == DPLL_STATE_HOLDOVER || in wait_for_sys_apll_dpll_lock()
361 dpll == DPLL_STATE_OPEN_LOOP) { in wait_for_sys_apll_dpll_lock()
363 "No wait state: DPLL_SYS_STATE %d", dpll); in wait_for_sys_apll_dpll_lock()
372 LOCK_TIMEOUT_MS, apll, dpll); in wait_for_sys_apll_dpll_lock()
1686 u16 dpll; in _enable_pll_tod_sync() local
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/drivers/video/fbdev/intelfb/
Dintelfbhw.c684 static void intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll, in intelfbhw_get_p1p2() argument
690 if (dpll & DPLL_P1_FORCE_DIV2) in intelfbhw_get_p1p2()
693 p1 = (dpll >> DPLL_P1_SHIFT) & 0xff; in intelfbhw_get_p1p2()
697 p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK; in intelfbhw_get_p1p2()
699 if (dpll & DPLL_P1_FORCE_DIV2) in intelfbhw_get_p1p2()
702 p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK; in intelfbhw_get_p1p2()
703 p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK; in intelfbhw_get_p1p2()
1045 u32 *dpll, *fp0, *fp1; in intelfbhw_mode_to_hw() local
1060 dpll = &hw->dpll_b; in intelfbhw_mode_to_hw()
1072 dpll = &hw->dpll_a; in intelfbhw_mode_to_hw()
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/drivers/clk/ti/
DMakefile5 clk-common = dpll.o composite.o divider.o gate.o \
/drivers/clk/rockchip/
Dclk-rk3036.c21 apll, dpll, gpll, enumerator
139 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
Dclk-rk3188.c19 apll, cpll, dpll, gpll, enumerator
218 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
229 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),

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