Searched refs:fdiv (Results 1 – 6 of 6) sorted by relevance
| /drivers/spi/ |
| D | spi-xlp.c | 139 u32 fdiv, cfg; in xlp_spi_setup() local
147 fdiv = DIV_ROUND_UP(xspi->spi_clk, spi->max_speed_hz); in xlp_spi_setup()
148 if (fdiv > XLP_SPI_FDIV_MAX) in xlp_spi_setup()
149 fdiv = XLP_SPI_FDIV_MAX; in xlp_spi_setup()
150 else if (fdiv < XLP_SPI_FDIV_MIN) in xlp_spi_setup()
151 fdiv = XLP_SPI_FDIV_MIN; in xlp_spi_setup()
153 xlp_spi_reg_write(xspi, cs, XLP_SPI_FDIV, fdiv); in xlp_spi_setup()
174 if (fdiv == 4) in xlp_spi_setup()
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| /drivers/tty/serial/ |
| D | max310x.c | 564 unsigned long fdiv, fmul, bestfreq = freq; in max310x_set_ref_clk() local
571 fdiv = DIV_ROUND_CLOSEST(freq, div); in max310x_set_ref_clk()
574 fmul = fdiv * 6; in max310x_set_ref_clk()
575 if ((fdiv >= 500000) && (fdiv <= 800000)) in max310x_set_ref_clk()
581 fmul = fdiv * 48; in max310x_set_ref_clk()
582 if ((fdiv >= 850000) && (fdiv <= 1200000)) in max310x_set_ref_clk()
588 fmul = fdiv * 96; in max310x_set_ref_clk()
589 if ((fdiv >= 425000) && (fdiv <= 1000000)) in max310x_set_ref_clk()
595 fmul = fdiv * 144; in max310x_set_ref_clk()
596 if ((fdiv >= 390000) && (fdiv <= 667000)) in max310x_set_ref_clk()
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| /drivers/media/tuners/ |
| D | it913x.c | 20 u8 fdiv; member
53 dev->fdiv = 3; in it913x_init()
60 dev->fdiv = 1; in it913x_init()
95 dev->fn_min /= (dev->fdiv * nv_val); in it913x_init()
274 t_cal_freq = (c->frequency / 1000) * n_div * dev->fdiv; in it913x_set_params()
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| /drivers/clk/st/ |
| D | clk-flexgen.c | 43 struct clk_divider fdiv; member
143 struct clk_hw *fdiv_hw = &flexgen->fdiv.hw; in flexgen_recalc_rate()
159 struct clk_hw *fdiv_hw = &flexgen->fdiv.hw; in flexgen_set_rate()
253 fgxbar->fdiv.lock = lock; in clk_register_flexgen()
254 fgxbar->fdiv.reg = fdiv_reg; in clk_register_flexgen()
255 fgxbar->fdiv.width = 6; in clk_register_flexgen()
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| /drivers/clk/bcm/ |
| D | clk-bcm2835.c | 549 u32 *ndiv, u32 *fdiv) in bcm2835_pll_choose_ndiv_and_fdiv() argument
557 *fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1); in bcm2835_pll_choose_ndiv_and_fdiv()
561 u32 ndiv, u32 fdiv, u32 pdiv) in bcm2835_pll_rate_from_divisors() argument
568 rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv); in bcm2835_pll_rate_from_divisors()
578 u32 ndiv, fdiv; in bcm2835_pll_round_rate() local
582 bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv); in bcm2835_pll_round_rate()
584 return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1); in bcm2835_pll_round_rate()
594 u32 ndiv, pdiv, fdiv; in bcm2835_pll_get_rate() local
600 fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK; in bcm2835_pll_get_rate()
608 fdiv *= 2; in bcm2835_pll_get_rate()
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| /drivers/clk/socfpga/ |
| D | clk-pll-s10.c | 44 unsigned long fdiv, reg, rdiv, qdiv; in n5x_clk_pll_recalc_rate() local
49 fdiv = (reg & SOCFPGA_N5X_PLLDIV_FDIV_MASK) >> SOCFPGA_N5X_PLLDIV_FDIV_SHIFT; in n5x_clk_pll_recalc_rate()
58 return ((parent_rate * 2 * (fdiv + 1)) / ((rdiv + 1) * power)); in n5x_clk_pll_recalc_rate()
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