1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver
4 *
5 * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru>
6 *
7 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org>
8 * Based on max3110.c, by Feng Tang <feng.tang@intel.com>
9 * Based on max3107.c, by Aavamobile
10 */
11
12 #include <linux/bitops.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/gpio/driver.h>
17 #include <linux/module.h>
18 #include <linux/mod_devicetable.h>
19 #include <linux/property.h>
20 #include <linux/regmap.h>
21 #include <linux/serial_core.h>
22 #include <linux/serial.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/spi/spi.h>
26 #include <linux/uaccess.h>
27
28 #define MAX310X_NAME "max310x"
29 #define MAX310X_MAJOR 204
30 #define MAX310X_MINOR 209
31 #define MAX310X_UART_NRMAX 16
32
33 /* MAX310X register definitions */
34 #define MAX310X_RHR_REG (0x00) /* RX FIFO */
35 #define MAX310X_THR_REG (0x00) /* TX FIFO */
36 #define MAX310X_IRQEN_REG (0x01) /* IRQ enable */
37 #define MAX310X_IRQSTS_REG (0x02) /* IRQ status */
38 #define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */
39 #define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */
40 #define MAX310X_REG_05 (0x05)
41 #define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */
42 #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */
43 #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */
44 #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */
45 #define MAX310X_MODE1_REG (0x09) /* MODE1 */
46 #define MAX310X_MODE2_REG (0x0a) /* MODE2 */
47 #define MAX310X_LCR_REG (0x0b) /* LCR */
48 #define MAX310X_RXTO_REG (0x0c) /* RX timeout */
49 #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */
50 #define MAX310X_IRDA_REG (0x0e) /* IRDA settings */
51 #define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */
52 #define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */
53 #define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */
54 #define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */
55 #define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */
56 #define MAX310X_XON1_REG (0x14) /* XON1 character */
57 #define MAX310X_XON2_REG (0x15) /* XON2 character */
58 #define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */
59 #define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */
60 #define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */
61 #define MAX310X_GPIODATA_REG (0x19) /* GPIO data */
62 #define MAX310X_PLLCFG_REG (0x1a) /* PLL config */
63 #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */
64 #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */
65 #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */
66 #define MAX310X_CLKSRC_REG (0x1e) /* Clock source */
67 #define MAX310X_REG_1F (0x1f)
68
69 #define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */
70
71 #define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */
72 #define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */
73
74 /* Extended registers */
75 #define MAX310X_REVID_EXTREG MAX310X_REG_05 /* Revision ID */
76
77 /* IRQ register bits */
78 #define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */
79 #define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */
80 #define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */
81 #define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */
82 #define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */
83 #define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */
84 #define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */
85 #define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */
86
87 /* LSR register bits */
88 #define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */
89 #define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */
90 #define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */
91 #define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */
92 #define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */
93 #define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */
94 #define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */
95
96 /* Special character register bits */
97 #define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */
98 #define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */
99 #define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */
100 #define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */
101 #define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */
102 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
103
104 /* Status register bits */
105 #define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */
106 #define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */
107 #define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */
108 #define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */
109 #define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */
110 #define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */
111
112 /* MODE1 register bits */
113 #define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */
114 #define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */
115 #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
116 #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
117 #define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */
118 #define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */
119 #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */
120 #define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */
121
122 /* MODE2 register bits */
123 #define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */
124 #define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */
125 #define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */
126 #define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */
127 #define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */
128 #define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */
129 #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */
130 #define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */
131
132 /* LCR register bits */
133 #define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
134 #define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
135 *
136 * Word length bits table:
137 * 00 -> 5 bit words
138 * 01 -> 6 bit words
139 * 10 -> 7 bit words
140 * 11 -> 8 bit words
141 */
142 #define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
143 *
144 * STOP length bit table:
145 * 0 -> 1 stop bit
146 * 1 -> 1-1.5 stop bits if
147 * word length is 5,
148 * 2 stop bits otherwise
149 */
150 #define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
151 #define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
152 #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
153 #define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
154 #define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */
155
156 /* IRDA register bits */
157 #define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */
158 #define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */
159
160 /* Flow control trigger level register masks */
161 #define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */
162 #define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */
163 #define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f)
164 #define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4)
165
166 /* FIFO interrupt trigger level register masks */
167 #define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */
168 #define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */
169 #define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f)
170 #define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4)
171
172 /* Flow control register bits */
173 #define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */
174 #define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */
175 #define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs
176 * are used in conjunction with
177 * XOFF2 for definition of
178 * special character */
179 #define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */
180 #define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */
181 #define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1
182 *
183 * SWFLOW bits 1 & 0 table:
184 * 00 -> no transmitter flow
185 * control
186 * 01 -> receiver compares
187 * XON2 and XOFF2
188 * and controls
189 * transmitter
190 * 10 -> receiver compares
191 * XON1 and XOFF1
192 * and controls
193 * transmitter
194 * 11 -> receiver compares
195 * XON1, XON2, XOFF1 and
196 * XOFF2 and controls
197 * transmitter
198 */
199 #define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */
200 #define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3
201 *
202 * SWFLOW bits 3 & 2 table:
203 * 00 -> no received flow
204 * control
205 * 01 -> transmitter generates
206 * XON2 and XOFF2
207 * 10 -> transmitter generates
208 * XON1 and XOFF1
209 * 11 -> transmitter generates
210 * XON1, XON2, XOFF1 and
211 * XOFF2
212 */
213
214 /* PLL configuration register masks */
215 #define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */
216 #define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */
217
218 /* Baud rate generator configuration register bits */
219 #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */
220 #define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */
221
222 /* Clock source register bits */
223 #define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */
224 #define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */
225 #define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */
226 #define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */
227 #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */
228
229 /* Global commands */
230 #define MAX310X_EXTREG_ENBL (0xce)
231 #define MAX310X_EXTREG_DSBL (0xcd)
232
233 /* Misc definitions */
234 #define MAX310X_FIFO_SIZE (128)
235 #define MAX310x_REV_MASK (0xf8)
236 #define MAX310X_WRITE_BIT 0x80
237
238 /* Crystal-related definitions */
239 #define MAX310X_XTAL_WAIT_RETRIES 20 /* Number of retries */
240 #define MAX310X_XTAL_WAIT_DELAY_MS 10 /* Delay between retries */
241
242 /* MAX3107 specific */
243 #define MAX3107_REV_ID (0xa0)
244
245 /* MAX3109 specific */
246 #define MAX3109_REV_ID (0xc0)
247
248 /* MAX14830 specific */
249 #define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6) /* Clock Disable */
250 #define MAX14830_REV_ID (0xb0)
251
252 struct max310x_devtype {
253 char name[9];
254 int nr;
255 u8 mode1;
256 int (*detect)(struct device *);
257 void (*power)(struct uart_port *, int);
258 };
259
260 struct max310x_one {
261 struct uart_port port;
262 struct work_struct tx_work;
263 struct work_struct md_work;
264 struct work_struct rs_work;
265
266 u8 wr_header;
267 u8 rd_header;
268 u8 rx_buf[MAX310X_FIFO_SIZE];
269 };
270 #define to_max310x_port(_port) \
271 container_of(_port, struct max310x_one, port)
272
273 struct max310x_port {
274 const struct max310x_devtype *devtype;
275 struct regmap *regmap;
276 struct clk *clk;
277 #ifdef CONFIG_GPIOLIB
278 struct gpio_chip gpio;
279 #endif
280 struct max310x_one p[];
281 };
282
283 static struct uart_driver max310x_uart = {
284 .owner = THIS_MODULE,
285 .driver_name = MAX310X_NAME,
286 .dev_name = "ttyMAX",
287 .major = MAX310X_MAJOR,
288 .minor = MAX310X_MINOR,
289 .nr = MAX310X_UART_NRMAX,
290 };
291
292 static DECLARE_BITMAP(max310x_lines, MAX310X_UART_NRMAX);
293
max310x_port_read(struct uart_port * port,u8 reg)294 static u8 max310x_port_read(struct uart_port *port, u8 reg)
295 {
296 struct max310x_port *s = dev_get_drvdata(port->dev);
297 unsigned int val = 0;
298
299 regmap_read(s->regmap, port->iobase + reg, &val);
300
301 return val;
302 }
303
max310x_port_write(struct uart_port * port,u8 reg,u8 val)304 static void max310x_port_write(struct uart_port *port, u8 reg, u8 val)
305 {
306 struct max310x_port *s = dev_get_drvdata(port->dev);
307
308 regmap_write(s->regmap, port->iobase + reg, val);
309 }
310
max310x_port_update(struct uart_port * port,u8 reg,u8 mask,u8 val)311 static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val)
312 {
313 struct max310x_port *s = dev_get_drvdata(port->dev);
314
315 regmap_update_bits(s->regmap, port->iobase + reg, mask, val);
316 }
317
max3107_detect(struct device * dev)318 static int max3107_detect(struct device *dev)
319 {
320 struct max310x_port *s = dev_get_drvdata(dev);
321 unsigned int val = 0;
322 int ret;
323
324 ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val);
325 if (ret)
326 return ret;
327
328 if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) {
329 dev_err(dev,
330 "%s ID 0x%02x does not match\n", s->devtype->name, val);
331 return -ENODEV;
332 }
333
334 return 0;
335 }
336
max3108_detect(struct device * dev)337 static int max3108_detect(struct device *dev)
338 {
339 struct max310x_port *s = dev_get_drvdata(dev);
340 unsigned int val = 0;
341 int ret;
342
343 /* MAX3108 have not REV ID register, we just check default value
344 * from clocksource register to make sure everything works.
345 */
346 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val);
347 if (ret)
348 return ret;
349
350 if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) {
351 dev_err(dev, "%s not present\n", s->devtype->name);
352 return -ENODEV;
353 }
354
355 return 0;
356 }
357
max3109_detect(struct device * dev)358 static int max3109_detect(struct device *dev)
359 {
360 struct max310x_port *s = dev_get_drvdata(dev);
361 unsigned int val = 0;
362 int ret;
363
364 ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG,
365 MAX310X_EXTREG_ENBL);
366 if (ret)
367 return ret;
368
369 regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val);
370 regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL);
371 if (((val & MAX310x_REV_MASK) != MAX3109_REV_ID)) {
372 dev_err(dev,
373 "%s ID 0x%02x does not match\n", s->devtype->name, val);
374 return -ENODEV;
375 }
376
377 return 0;
378 }
379
max310x_power(struct uart_port * port,int on)380 static void max310x_power(struct uart_port *port, int on)
381 {
382 max310x_port_update(port, MAX310X_MODE1_REG,
383 MAX310X_MODE1_FORCESLEEP_BIT,
384 on ? 0 : MAX310X_MODE1_FORCESLEEP_BIT);
385 if (on)
386 msleep(50);
387 }
388
max14830_detect(struct device * dev)389 static int max14830_detect(struct device *dev)
390 {
391 struct max310x_port *s = dev_get_drvdata(dev);
392 unsigned int val = 0;
393 int ret;
394
395 ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG,
396 MAX310X_EXTREG_ENBL);
397 if (ret)
398 return ret;
399
400 regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val);
401 regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL);
402 if (((val & MAX310x_REV_MASK) != MAX14830_REV_ID)) {
403 dev_err(dev,
404 "%s ID 0x%02x does not match\n", s->devtype->name, val);
405 return -ENODEV;
406 }
407
408 return 0;
409 }
410
max14830_power(struct uart_port * port,int on)411 static void max14830_power(struct uart_port *port, int on)
412 {
413 max310x_port_update(port, MAX310X_BRGCFG_REG,
414 MAX14830_BRGCFG_CLKDIS_BIT,
415 on ? 0 : MAX14830_BRGCFG_CLKDIS_BIT);
416 if (on)
417 msleep(50);
418 }
419
420 static const struct max310x_devtype max3107_devtype = {
421 .name = "MAX3107",
422 .nr = 1,
423 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT | MAX310X_MODE1_IRQSEL_BIT,
424 .detect = max3107_detect,
425 .power = max310x_power,
426 };
427
428 static const struct max310x_devtype max3108_devtype = {
429 .name = "MAX3108",
430 .nr = 1,
431 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT,
432 .detect = max3108_detect,
433 .power = max310x_power,
434 };
435
436 static const struct max310x_devtype max3109_devtype = {
437 .name = "MAX3109",
438 .nr = 2,
439 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT,
440 .detect = max3109_detect,
441 .power = max310x_power,
442 };
443
444 static const struct max310x_devtype max14830_devtype = {
445 .name = "MAX14830",
446 .nr = 4,
447 .mode1 = MAX310X_MODE1_IRQSEL_BIT,
448 .detect = max14830_detect,
449 .power = max14830_power,
450 };
451
max310x_reg_writeable(struct device * dev,unsigned int reg)452 static bool max310x_reg_writeable(struct device *dev, unsigned int reg)
453 {
454 switch (reg & 0x1f) {
455 case MAX310X_IRQSTS_REG:
456 case MAX310X_LSR_IRQSTS_REG:
457 case MAX310X_SPCHR_IRQSTS_REG:
458 case MAX310X_STS_IRQSTS_REG:
459 case MAX310X_TXFIFOLVL_REG:
460 case MAX310X_RXFIFOLVL_REG:
461 return false;
462 default:
463 break;
464 }
465
466 return true;
467 }
468
max310x_reg_volatile(struct device * dev,unsigned int reg)469 static bool max310x_reg_volatile(struct device *dev, unsigned int reg)
470 {
471 switch (reg & 0x1f) {
472 case MAX310X_RHR_REG:
473 case MAX310X_IRQSTS_REG:
474 case MAX310X_LSR_IRQSTS_REG:
475 case MAX310X_SPCHR_IRQSTS_REG:
476 case MAX310X_STS_IRQSTS_REG:
477 case MAX310X_TXFIFOLVL_REG:
478 case MAX310X_RXFIFOLVL_REG:
479 case MAX310X_GPIODATA_REG:
480 case MAX310X_BRGDIVLSB_REG:
481 case MAX310X_REG_05:
482 case MAX310X_REG_1F:
483 return true;
484 default:
485 break;
486 }
487
488 return false;
489 }
490
max310x_reg_precious(struct device * dev,unsigned int reg)491 static bool max310x_reg_precious(struct device *dev, unsigned int reg)
492 {
493 switch (reg & 0x1f) {
494 case MAX310X_RHR_REG:
495 case MAX310X_IRQSTS_REG:
496 case MAX310X_SPCHR_IRQSTS_REG:
497 case MAX310X_STS_IRQSTS_REG:
498 return true;
499 default:
500 break;
501 }
502
503 return false;
504 }
505
max310x_set_baud(struct uart_port * port,int baud)506 static int max310x_set_baud(struct uart_port *port, int baud)
507 {
508 unsigned int mode = 0, div = 0, frac = 0, c = 0, F = 0;
509
510 /*
511 * Calculate the integer divisor first. Select a proper mode
512 * in case if the requested baud is too high for the pre-defined
513 * clocks frequency.
514 */
515 div = port->uartclk / baud;
516 if (div < 8) {
517 /* Mode x4 */
518 c = 4;
519 mode = MAX310X_BRGCFG_4XMODE_BIT;
520 } else if (div < 16) {
521 /* Mode x2 */
522 c = 8;
523 mode = MAX310X_BRGCFG_2XMODE_BIT;
524 } else {
525 c = 16;
526 }
527
528 /* Calculate the divisor in accordance with the fraction coefficient */
529 div /= c;
530 F = c*baud;
531
532 /* Calculate the baud rate fraction */
533 if (div > 0)
534 frac = (16*(port->uartclk % F)) / F;
535 else
536 div = 1;
537
538 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, div >> 8);
539 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div);
540 max310x_port_write(port, MAX310X_BRGCFG_REG, frac | mode);
541
542 /* Return the actual baud rate we just programmed */
543 return (16*port->uartclk) / (c*(16*div + frac));
544 }
545
max310x_update_best_err(unsigned long f,long * besterr)546 static int max310x_update_best_err(unsigned long f, long *besterr)
547 {
548 /* Use baudrate 115200 for calculate error */
549 long err = f % (460800 * 16);
550
551 if ((*besterr < 0) || (*besterr > err)) {
552 *besterr = err;
553 return 0;
554 }
555
556 return 1;
557 }
558
max310x_set_ref_clk(struct device * dev,struct max310x_port * s,unsigned long freq,bool xtal)559 static s32 max310x_set_ref_clk(struct device *dev, struct max310x_port *s,
560 unsigned long freq, bool xtal)
561 {
562 unsigned int div, clksrc, pllcfg = 0;
563 long besterr = -1;
564 unsigned long fdiv, fmul, bestfreq = freq;
565
566 /* First, update error without PLL */
567 max310x_update_best_err(freq, &besterr);
568
569 /* Try all possible PLL dividers */
570 for (div = 1; (div <= 63) && besterr; div++) {
571 fdiv = DIV_ROUND_CLOSEST(freq, div);
572
573 /* Try multiplier 6 */
574 fmul = fdiv * 6;
575 if ((fdiv >= 500000) && (fdiv <= 800000))
576 if (!max310x_update_best_err(fmul, &besterr)) {
577 pllcfg = (0 << 6) | div;
578 bestfreq = fmul;
579 }
580 /* Try multiplier 48 */
581 fmul = fdiv * 48;
582 if ((fdiv >= 850000) && (fdiv <= 1200000))
583 if (!max310x_update_best_err(fmul, &besterr)) {
584 pllcfg = (1 << 6) | div;
585 bestfreq = fmul;
586 }
587 /* Try multiplier 96 */
588 fmul = fdiv * 96;
589 if ((fdiv >= 425000) && (fdiv <= 1000000))
590 if (!max310x_update_best_err(fmul, &besterr)) {
591 pllcfg = (2 << 6) | div;
592 bestfreq = fmul;
593 }
594 /* Try multiplier 144 */
595 fmul = fdiv * 144;
596 if ((fdiv >= 390000) && (fdiv <= 667000))
597 if (!max310x_update_best_err(fmul, &besterr)) {
598 pllcfg = (3 << 6) | div;
599 bestfreq = fmul;
600 }
601 }
602
603 /* Configure clock source */
604 clksrc = MAX310X_CLKSRC_EXTCLK_BIT | (xtal ? MAX310X_CLKSRC_CRYST_BIT : 0);
605
606 /* Configure PLL */
607 if (pllcfg) {
608 clksrc |= MAX310X_CLKSRC_PLL_BIT;
609 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg);
610 } else
611 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT;
612
613 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc);
614
615 /* Wait for crystal */
616 if (xtal) {
617 bool stable = false;
618 unsigned int try = 0, val = 0;
619
620 do {
621 msleep(MAX310X_XTAL_WAIT_DELAY_MS);
622 regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val);
623
624 if (val & MAX310X_STS_CLKREADY_BIT)
625 stable = true;
626 } while (!stable && (++try < MAX310X_XTAL_WAIT_RETRIES));
627
628 if (!stable)
629 return dev_err_probe(dev, -EAGAIN,
630 "clock is not stable\n");
631 }
632
633 return bestfreq;
634 }
635
max310x_batch_write(struct uart_port * port,u8 * txbuf,unsigned int len)636 static void max310x_batch_write(struct uart_port *port, u8 *txbuf, unsigned int len)
637 {
638 struct max310x_one *one = to_max310x_port(port);
639 struct spi_transfer xfer[] = {
640 {
641 .tx_buf = &one->wr_header,
642 .len = sizeof(one->wr_header),
643 }, {
644 .tx_buf = txbuf,
645 .len = len,
646 }
647 };
648 spi_sync_transfer(to_spi_device(port->dev), xfer, ARRAY_SIZE(xfer));
649 }
650
max310x_batch_read(struct uart_port * port,u8 * rxbuf,unsigned int len)651 static void max310x_batch_read(struct uart_port *port, u8 *rxbuf, unsigned int len)
652 {
653 struct max310x_one *one = to_max310x_port(port);
654 struct spi_transfer xfer[] = {
655 {
656 .tx_buf = &one->rd_header,
657 .len = sizeof(one->rd_header),
658 }, {
659 .rx_buf = rxbuf,
660 .len = len,
661 }
662 };
663 spi_sync_transfer(to_spi_device(port->dev), xfer, ARRAY_SIZE(xfer));
664 }
665
max310x_handle_rx(struct uart_port * port,unsigned int rxlen)666 static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen)
667 {
668 struct max310x_one *one = to_max310x_port(port);
669 unsigned int sts, ch, flag, i;
670
671 if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) {
672 /* We are just reading, happily ignoring any error conditions.
673 * Break condition, parity checking, framing errors -- they
674 * are all ignored. That means that we can do a batch-read.
675 *
676 * There is a small opportunity for race if the RX FIFO
677 * overruns while we're reading the buffer; the datasheets says
678 * that the LSR register applies to the "current" character.
679 * That's also the reason why we cannot do batched reads when
680 * asked to check the individual statuses.
681 * */
682
683 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
684 max310x_batch_read(port, one->rx_buf, rxlen);
685
686 port->icount.rx += rxlen;
687 flag = TTY_NORMAL;
688 sts &= port->read_status_mask;
689
690 if (sts & MAX310X_LSR_RXOVR_BIT) {
691 dev_warn_ratelimited(port->dev, "Hardware RX FIFO overrun\n");
692 port->icount.overrun++;
693 }
694
695 for (i = 0; i < (rxlen - 1); ++i)
696 uart_insert_char(port, sts, 0, one->rx_buf[i], flag);
697
698 /*
699 * Handle the overrun case for the last character only, since
700 * the RxFIFO overflow happens after it is pushed to the FIFO
701 * tail.
702 */
703 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT,
704 one->rx_buf[rxlen-1], flag);
705
706 } else {
707 if (unlikely(rxlen >= port->fifosize)) {
708 dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n");
709 port->icount.buf_overrun++;
710 /* Ensure sanity of RX level */
711 rxlen = port->fifosize;
712 }
713
714 while (rxlen--) {
715 ch = max310x_port_read(port, MAX310X_RHR_REG);
716 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
717
718 sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT |
719 MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT;
720
721 port->icount.rx++;
722 flag = TTY_NORMAL;
723
724 if (unlikely(sts)) {
725 if (sts & MAX310X_LSR_RXBRK_BIT) {
726 port->icount.brk++;
727 if (uart_handle_break(port))
728 continue;
729 } else if (sts & MAX310X_LSR_RXPAR_BIT)
730 port->icount.parity++;
731 else if (sts & MAX310X_LSR_FRERR_BIT)
732 port->icount.frame++;
733 else if (sts & MAX310X_LSR_RXOVR_BIT)
734 port->icount.overrun++;
735
736 sts &= port->read_status_mask;
737 if (sts & MAX310X_LSR_RXBRK_BIT)
738 flag = TTY_BREAK;
739 else if (sts & MAX310X_LSR_RXPAR_BIT)
740 flag = TTY_PARITY;
741 else if (sts & MAX310X_LSR_FRERR_BIT)
742 flag = TTY_FRAME;
743 else if (sts & MAX310X_LSR_RXOVR_BIT)
744 flag = TTY_OVERRUN;
745 }
746
747 if (uart_handle_sysrq_char(port, ch))
748 continue;
749
750 if (sts & port->ignore_status_mask)
751 continue;
752
753 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag);
754 }
755 }
756
757 tty_flip_buffer_push(&port->state->port);
758 }
759
max310x_handle_tx(struct uart_port * port)760 static void max310x_handle_tx(struct uart_port *port)
761 {
762 struct circ_buf *xmit = &port->state->xmit;
763 unsigned int txlen, to_send, until_end;
764
765 if (unlikely(port->x_char)) {
766 max310x_port_write(port, MAX310X_THR_REG, port->x_char);
767 port->icount.tx++;
768 port->x_char = 0;
769 return;
770 }
771
772 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
773 return;
774
775 /* Get length of data pending in circular buffer */
776 to_send = uart_circ_chars_pending(xmit);
777 until_end = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
778 if (likely(to_send)) {
779 /* Limit to size of TX FIFO */
780 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
781 txlen = port->fifosize - txlen;
782 to_send = (to_send > txlen) ? txlen : to_send;
783
784 if (until_end < to_send) {
785 /* It's a circ buffer -- wrap around.
786 * We could do that in one SPI transaction, but meh. */
787 max310x_batch_write(port, xmit->buf + xmit->tail, until_end);
788 max310x_batch_write(port, xmit->buf, to_send - until_end);
789 } else {
790 max310x_batch_write(port, xmit->buf + xmit->tail, to_send);
791 }
792
793 /* Add data to send */
794 port->icount.tx += to_send;
795 xmit->tail = (xmit->tail + to_send) & (UART_XMIT_SIZE - 1);
796 }
797
798 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
799 uart_write_wakeup(port);
800 }
801
max310x_start_tx(struct uart_port * port)802 static void max310x_start_tx(struct uart_port *port)
803 {
804 struct max310x_one *one = to_max310x_port(port);
805
806 schedule_work(&one->tx_work);
807 }
808
max310x_port_irq(struct max310x_port * s,int portno)809 static irqreturn_t max310x_port_irq(struct max310x_port *s, int portno)
810 {
811 struct uart_port *port = &s->p[portno].port;
812 irqreturn_t res = IRQ_NONE;
813
814 do {
815 unsigned int ists, lsr, rxlen;
816
817 /* Read IRQ status & RX FIFO level */
818 ists = max310x_port_read(port, MAX310X_IRQSTS_REG);
819 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG);
820 if (!ists && !rxlen)
821 break;
822
823 res = IRQ_HANDLED;
824
825 if (ists & MAX310X_IRQ_CTS_BIT) {
826 lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
827 uart_handle_cts_change(port,
828 !!(lsr & MAX310X_LSR_CTS_BIT));
829 }
830 if (rxlen)
831 max310x_handle_rx(port, rxlen);
832 if (ists & MAX310X_IRQ_TXEMPTY_BIT)
833 max310x_start_tx(port);
834 } while (1);
835 return res;
836 }
837
max310x_ist(int irq,void * dev_id)838 static irqreturn_t max310x_ist(int irq, void *dev_id)
839 {
840 struct max310x_port *s = (struct max310x_port *)dev_id;
841 bool handled = false;
842
843 if (s->devtype->nr > 1) {
844 do {
845 unsigned int val = ~0;
846
847 WARN_ON_ONCE(regmap_read(s->regmap,
848 MAX310X_GLOBALIRQ_REG, &val));
849 val = ((1 << s->devtype->nr) - 1) & ~val;
850 if (!val)
851 break;
852 if (max310x_port_irq(s, fls(val) - 1) == IRQ_HANDLED)
853 handled = true;
854 } while (1);
855 } else {
856 if (max310x_port_irq(s, 0) == IRQ_HANDLED)
857 handled = true;
858 }
859
860 return IRQ_RETVAL(handled);
861 }
862
max310x_tx_proc(struct work_struct * ws)863 static void max310x_tx_proc(struct work_struct *ws)
864 {
865 struct max310x_one *one = container_of(ws, struct max310x_one, tx_work);
866
867 max310x_handle_tx(&one->port);
868 }
869
max310x_tx_empty(struct uart_port * port)870 static unsigned int max310x_tx_empty(struct uart_port *port)
871 {
872 u8 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
873
874 return lvl ? 0 : TIOCSER_TEMT;
875 }
876
max310x_get_mctrl(struct uart_port * port)877 static unsigned int max310x_get_mctrl(struct uart_port *port)
878 {
879 /* DCD and DSR are not wired and CTS/RTS is handled automatically
880 * so just indicate DSR and CAR asserted
881 */
882 return TIOCM_DSR | TIOCM_CAR;
883 }
884
max310x_md_proc(struct work_struct * ws)885 static void max310x_md_proc(struct work_struct *ws)
886 {
887 struct max310x_one *one = container_of(ws, struct max310x_one, md_work);
888
889 max310x_port_update(&one->port, MAX310X_MODE2_REG,
890 MAX310X_MODE2_LOOPBACK_BIT,
891 (one->port.mctrl & TIOCM_LOOP) ?
892 MAX310X_MODE2_LOOPBACK_BIT : 0);
893 }
894
max310x_set_mctrl(struct uart_port * port,unsigned int mctrl)895 static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl)
896 {
897 struct max310x_one *one = to_max310x_port(port);
898
899 schedule_work(&one->md_work);
900 }
901
max310x_break_ctl(struct uart_port * port,int break_state)902 static void max310x_break_ctl(struct uart_port *port, int break_state)
903 {
904 max310x_port_update(port, MAX310X_LCR_REG,
905 MAX310X_LCR_TXBREAK_BIT,
906 break_state ? MAX310X_LCR_TXBREAK_BIT : 0);
907 }
908
max310x_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)909 static void max310x_set_termios(struct uart_port *port,
910 struct ktermios *termios,
911 struct ktermios *old)
912 {
913 unsigned int lcr = 0, flow = 0;
914 int baud;
915
916 /* Mask termios capabilities we don't support */
917 termios->c_cflag &= ~CMSPAR;
918
919 /* Word size */
920 switch (termios->c_cflag & CSIZE) {
921 case CS5:
922 break;
923 case CS6:
924 lcr = MAX310X_LCR_LENGTH0_BIT;
925 break;
926 case CS7:
927 lcr = MAX310X_LCR_LENGTH1_BIT;
928 break;
929 case CS8:
930 default:
931 lcr = MAX310X_LCR_LENGTH1_BIT | MAX310X_LCR_LENGTH0_BIT;
932 break;
933 }
934
935 /* Parity */
936 if (termios->c_cflag & PARENB) {
937 lcr |= MAX310X_LCR_PARITY_BIT;
938 if (!(termios->c_cflag & PARODD))
939 lcr |= MAX310X_LCR_EVENPARITY_BIT;
940 }
941
942 /* Stop bits */
943 if (termios->c_cflag & CSTOPB)
944 lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */
945
946 /* Update LCR register */
947 max310x_port_write(port, MAX310X_LCR_REG, lcr);
948
949 /* Set read status mask */
950 port->read_status_mask = MAX310X_LSR_RXOVR_BIT;
951 if (termios->c_iflag & INPCK)
952 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT |
953 MAX310X_LSR_FRERR_BIT;
954 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
955 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT;
956
957 /* Set status ignore mask */
958 port->ignore_status_mask = 0;
959 if (termios->c_iflag & IGNBRK)
960 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT;
961 if (!(termios->c_cflag & CREAD))
962 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT |
963 MAX310X_LSR_RXOVR_BIT |
964 MAX310X_LSR_FRERR_BIT |
965 MAX310X_LSR_RXBRK_BIT;
966
967 /* Configure flow control */
968 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]);
969 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]);
970
971 /* Disable transmitter before enabling AutoCTS or auto transmitter
972 * flow control
973 */
974 if (termios->c_cflag & CRTSCTS || termios->c_iflag & IXOFF) {
975 max310x_port_update(port, MAX310X_MODE1_REG,
976 MAX310X_MODE1_TXDIS_BIT,
977 MAX310X_MODE1_TXDIS_BIT);
978 }
979
980 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
981
982 if (termios->c_cflag & CRTSCTS) {
983 /* Enable AUTORTS and AUTOCTS */
984 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
985 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT |
986 MAX310X_FLOWCTRL_AUTORTS_BIT;
987 }
988 if (termios->c_iflag & IXON)
989 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT |
990 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
991 if (termios->c_iflag & IXOFF) {
992 port->status |= UPSTAT_AUTOXOFF;
993 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT |
994 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
995 }
996 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow);
997
998 /* Enable transmitter after disabling AutoCTS and auto transmitter
999 * flow control
1000 */
1001 if (!(termios->c_cflag & CRTSCTS) && !(termios->c_iflag & IXOFF)) {
1002 max310x_port_update(port, MAX310X_MODE1_REG,
1003 MAX310X_MODE1_TXDIS_BIT,
1004 0);
1005 }
1006
1007 /* Get baud rate generator configuration */
1008 baud = uart_get_baud_rate(port, termios, old,
1009 port->uartclk / 16 / 0xffff,
1010 port->uartclk / 4);
1011
1012 /* Setup baudrate generator */
1013 baud = max310x_set_baud(port, baud);
1014
1015 /* Update timeout according to new baud rate */
1016 uart_update_timeout(port, termios->c_cflag, baud);
1017 }
1018
max310x_rs_proc(struct work_struct * ws)1019 static void max310x_rs_proc(struct work_struct *ws)
1020 {
1021 struct max310x_one *one = container_of(ws, struct max310x_one, rs_work);
1022 unsigned int delay, mode1 = 0, mode2 = 0;
1023
1024 delay = (one->port.rs485.delay_rts_before_send << 4) |
1025 one->port.rs485.delay_rts_after_send;
1026 max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, delay);
1027
1028 if (one->port.rs485.flags & SER_RS485_ENABLED) {
1029 mode1 = MAX310X_MODE1_TRNSCVCTRL_BIT;
1030
1031 if (!(one->port.rs485.flags & SER_RS485_RX_DURING_TX))
1032 mode2 = MAX310X_MODE2_ECHOSUPR_BIT;
1033 }
1034
1035 max310x_port_update(&one->port, MAX310X_MODE1_REG,
1036 MAX310X_MODE1_TRNSCVCTRL_BIT, mode1);
1037 max310x_port_update(&one->port, MAX310X_MODE2_REG,
1038 MAX310X_MODE2_ECHOSUPR_BIT, mode2);
1039 }
1040
max310x_rs485_config(struct uart_port * port,struct serial_rs485 * rs485)1041 static int max310x_rs485_config(struct uart_port *port,
1042 struct serial_rs485 *rs485)
1043 {
1044 struct max310x_one *one = to_max310x_port(port);
1045
1046 if ((rs485->delay_rts_before_send > 0x0f) ||
1047 (rs485->delay_rts_after_send > 0x0f))
1048 return -ERANGE;
1049
1050 rs485->flags &= SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX |
1051 SER_RS485_ENABLED;
1052 memset(rs485->padding, 0, sizeof(rs485->padding));
1053 port->rs485 = *rs485;
1054
1055 schedule_work(&one->rs_work);
1056
1057 return 0;
1058 }
1059
max310x_startup(struct uart_port * port)1060 static int max310x_startup(struct uart_port *port)
1061 {
1062 struct max310x_port *s = dev_get_drvdata(port->dev);
1063 unsigned int val;
1064
1065 s->devtype->power(port, 1);
1066
1067 /* Configure MODE1 register */
1068 max310x_port_update(port, MAX310X_MODE1_REG,
1069 MAX310X_MODE1_TRNSCVCTRL_BIT, 0);
1070
1071 /* Configure MODE2 register & Reset FIFOs*/
1072 val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT;
1073 max310x_port_write(port, MAX310X_MODE2_REG, val);
1074 max310x_port_update(port, MAX310X_MODE2_REG,
1075 MAX310X_MODE2_FIFORST_BIT, 0);
1076
1077 /* Configure mode1/mode2 to have rs485/rs232 enabled at startup */
1078 val = (clamp(port->rs485.delay_rts_before_send, 0U, 15U) << 4) |
1079 clamp(port->rs485.delay_rts_after_send, 0U, 15U);
1080 max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val);
1081
1082 if (port->rs485.flags & SER_RS485_ENABLED) {
1083 max310x_port_update(port, MAX310X_MODE1_REG,
1084 MAX310X_MODE1_TRNSCVCTRL_BIT,
1085 MAX310X_MODE1_TRNSCVCTRL_BIT);
1086
1087 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
1088 max310x_port_update(port, MAX310X_MODE2_REG,
1089 MAX310X_MODE2_ECHOSUPR_BIT,
1090 MAX310X_MODE2_ECHOSUPR_BIT);
1091 }
1092
1093 /* Configure flow control levels */
1094 /* Flow control halt level 96, resume level 48 */
1095 max310x_port_write(port, MAX310X_FLOWLVL_REG,
1096 MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96));
1097
1098 /* Clear IRQ status register */
1099 max310x_port_read(port, MAX310X_IRQSTS_REG);
1100
1101 /* Enable RX, TX, CTS change interrupts */
1102 val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT;
1103 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT);
1104
1105 return 0;
1106 }
1107
max310x_shutdown(struct uart_port * port)1108 static void max310x_shutdown(struct uart_port *port)
1109 {
1110 struct max310x_port *s = dev_get_drvdata(port->dev);
1111
1112 /* Disable all interrupts */
1113 max310x_port_write(port, MAX310X_IRQEN_REG, 0);
1114
1115 s->devtype->power(port, 0);
1116 }
1117
max310x_type(struct uart_port * port)1118 static const char *max310x_type(struct uart_port *port)
1119 {
1120 struct max310x_port *s = dev_get_drvdata(port->dev);
1121
1122 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL;
1123 }
1124
max310x_request_port(struct uart_port * port)1125 static int max310x_request_port(struct uart_port *port)
1126 {
1127 /* Do nothing */
1128 return 0;
1129 }
1130
max310x_config_port(struct uart_port * port,int flags)1131 static void max310x_config_port(struct uart_port *port, int flags)
1132 {
1133 if (flags & UART_CONFIG_TYPE)
1134 port->type = PORT_MAX310X;
1135 }
1136
max310x_verify_port(struct uart_port * port,struct serial_struct * s)1137 static int max310x_verify_port(struct uart_port *port, struct serial_struct *s)
1138 {
1139 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X))
1140 return -EINVAL;
1141 if (s->irq != port->irq)
1142 return -EINVAL;
1143
1144 return 0;
1145 }
1146
max310x_null_void(struct uart_port * port)1147 static void max310x_null_void(struct uart_port *port)
1148 {
1149 /* Do nothing */
1150 }
1151
1152 static const struct uart_ops max310x_ops = {
1153 .tx_empty = max310x_tx_empty,
1154 .set_mctrl = max310x_set_mctrl,
1155 .get_mctrl = max310x_get_mctrl,
1156 .stop_tx = max310x_null_void,
1157 .start_tx = max310x_start_tx,
1158 .stop_rx = max310x_null_void,
1159 .break_ctl = max310x_break_ctl,
1160 .startup = max310x_startup,
1161 .shutdown = max310x_shutdown,
1162 .set_termios = max310x_set_termios,
1163 .type = max310x_type,
1164 .request_port = max310x_request_port,
1165 .release_port = max310x_null_void,
1166 .config_port = max310x_config_port,
1167 .verify_port = max310x_verify_port,
1168 };
1169
max310x_suspend(struct device * dev)1170 static int __maybe_unused max310x_suspend(struct device *dev)
1171 {
1172 struct max310x_port *s = dev_get_drvdata(dev);
1173 int i;
1174
1175 for (i = 0; i < s->devtype->nr; i++) {
1176 uart_suspend_port(&max310x_uart, &s->p[i].port);
1177 s->devtype->power(&s->p[i].port, 0);
1178 }
1179
1180 return 0;
1181 }
1182
max310x_resume(struct device * dev)1183 static int __maybe_unused max310x_resume(struct device *dev)
1184 {
1185 struct max310x_port *s = dev_get_drvdata(dev);
1186 int i;
1187
1188 for (i = 0; i < s->devtype->nr; i++) {
1189 s->devtype->power(&s->p[i].port, 1);
1190 uart_resume_port(&max310x_uart, &s->p[i].port);
1191 }
1192
1193 return 0;
1194 }
1195
1196 static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume);
1197
1198 #ifdef CONFIG_GPIOLIB
max310x_gpio_get(struct gpio_chip * chip,unsigned offset)1199 static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset)
1200 {
1201 unsigned int val;
1202 struct max310x_port *s = gpiochip_get_data(chip);
1203 struct uart_port *port = &s->p[offset / 4].port;
1204
1205 val = max310x_port_read(port, MAX310X_GPIODATA_REG);
1206
1207 return !!((val >> 4) & (1 << (offset % 4)));
1208 }
1209
max310x_gpio_set(struct gpio_chip * chip,unsigned offset,int value)1210 static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1211 {
1212 struct max310x_port *s = gpiochip_get_data(chip);
1213 struct uart_port *port = &s->p[offset / 4].port;
1214
1215 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1216 value ? 1 << (offset % 4) : 0);
1217 }
1218
max310x_gpio_direction_input(struct gpio_chip * chip,unsigned offset)1219 static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1220 {
1221 struct max310x_port *s = gpiochip_get_data(chip);
1222 struct uart_port *port = &s->p[offset / 4].port;
1223
1224 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0);
1225
1226 return 0;
1227 }
1228
max310x_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int value)1229 static int max310x_gpio_direction_output(struct gpio_chip *chip,
1230 unsigned offset, int value)
1231 {
1232 struct max310x_port *s = gpiochip_get_data(chip);
1233 struct uart_port *port = &s->p[offset / 4].port;
1234
1235 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1236 value ? 1 << (offset % 4) : 0);
1237 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4),
1238 1 << (offset % 4));
1239
1240 return 0;
1241 }
1242
max310x_gpio_set_config(struct gpio_chip * chip,unsigned int offset,unsigned long config)1243 static int max310x_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
1244 unsigned long config)
1245 {
1246 struct max310x_port *s = gpiochip_get_data(chip);
1247 struct uart_port *port = &s->p[offset / 4].port;
1248
1249 switch (pinconf_to_config_param(config)) {
1250 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1251 max310x_port_update(port, MAX310X_GPIOCFG_REG,
1252 1 << ((offset % 4) + 4),
1253 1 << ((offset % 4) + 4));
1254 return 0;
1255 case PIN_CONFIG_DRIVE_PUSH_PULL:
1256 max310x_port_update(port, MAX310X_GPIOCFG_REG,
1257 1 << ((offset % 4) + 4), 0);
1258 return 0;
1259 default:
1260 return -ENOTSUPP;
1261 }
1262 }
1263 #endif
1264
max310x_probe(struct device * dev,const struct max310x_devtype * devtype,struct regmap * regmap,int irq)1265 static int max310x_probe(struct device *dev, const struct max310x_devtype *devtype,
1266 struct regmap *regmap, int irq)
1267 {
1268 int i, ret, fmin, fmax, freq;
1269 struct max310x_port *s;
1270 s32 uartclk = 0;
1271 bool xtal;
1272
1273 if (IS_ERR(regmap))
1274 return PTR_ERR(regmap);
1275
1276 /* Alloc port structure */
1277 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr), GFP_KERNEL);
1278 if (!s) {
1279 dev_err(dev, "Error allocating port structure\n");
1280 return -ENOMEM;
1281 }
1282
1283 /* Always ask for fixed clock rate from a property. */
1284 device_property_read_u32(dev, "clock-frequency", &uartclk);
1285
1286 xtal = device_property_match_string(dev, "clock-names", "osc") < 0;
1287 if (xtal)
1288 s->clk = devm_clk_get_optional(dev, "xtal");
1289 else
1290 s->clk = devm_clk_get_optional(dev, "osc");
1291 if (IS_ERR(s->clk))
1292 return PTR_ERR(s->clk);
1293
1294 ret = clk_prepare_enable(s->clk);
1295 if (ret)
1296 return ret;
1297
1298 freq = clk_get_rate(s->clk);
1299 if (freq == 0)
1300 freq = uartclk;
1301 if (freq == 0) {
1302 dev_err(dev, "Cannot get clock rate\n");
1303 ret = -EINVAL;
1304 goto out_clk;
1305 }
1306
1307 if (xtal) {
1308 fmin = 1000000;
1309 fmax = 4000000;
1310 } else {
1311 fmin = 500000;
1312 fmax = 35000000;
1313 }
1314
1315 /* Check frequency limits */
1316 if (freq < fmin || freq > fmax) {
1317 ret = -ERANGE;
1318 goto out_clk;
1319 }
1320
1321 s->regmap = regmap;
1322 s->devtype = devtype;
1323 dev_set_drvdata(dev, s);
1324
1325 /* Check device to ensure we are talking to what we expect */
1326 ret = devtype->detect(dev);
1327 if (ret)
1328 goto out_clk;
1329
1330 for (i = 0; i < devtype->nr; i++) {
1331 unsigned int offs = i << 5;
1332
1333 /* Reset port */
1334 regmap_write(s->regmap, MAX310X_MODE2_REG + offs,
1335 MAX310X_MODE2_RST_BIT);
1336 /* Clear port reset */
1337 regmap_write(s->regmap, MAX310X_MODE2_REG + offs, 0);
1338
1339 /* Wait for port startup */
1340 do {
1341 regmap_read(s->regmap,
1342 MAX310X_BRGDIVLSB_REG + offs, &ret);
1343 } while (ret != 0x01);
1344
1345 regmap_write(s->regmap, MAX310X_MODE1_REG + offs,
1346 devtype->mode1);
1347 }
1348
1349 uartclk = max310x_set_ref_clk(dev, s, freq, xtal);
1350 if (uartclk < 0) {
1351 ret = uartclk;
1352 goto out_uart;
1353 }
1354
1355 dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk);
1356
1357 for (i = 0; i < devtype->nr; i++) {
1358 unsigned int line;
1359
1360 line = find_first_zero_bit(max310x_lines, MAX310X_UART_NRMAX);
1361 if (line == MAX310X_UART_NRMAX) {
1362 ret = -ERANGE;
1363 goto out_uart;
1364 }
1365
1366 /* Initialize port data */
1367 s->p[i].port.line = line;
1368 s->p[i].port.dev = dev;
1369 s->p[i].port.irq = irq;
1370 s->p[i].port.type = PORT_MAX310X;
1371 s->p[i].port.fifosize = MAX310X_FIFO_SIZE;
1372 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1373 s->p[i].port.iotype = UPIO_PORT;
1374 s->p[i].port.iobase = i * 0x20;
1375 s->p[i].port.membase = (void __iomem *)~0;
1376 s->p[i].port.uartclk = uartclk;
1377 s->p[i].port.rs485_config = max310x_rs485_config;
1378 s->p[i].port.ops = &max310x_ops;
1379 /* Disable all interrupts */
1380 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0);
1381 /* Clear IRQ status register */
1382 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG);
1383 /* Initialize queue for start TX */
1384 INIT_WORK(&s->p[i].tx_work, max310x_tx_proc);
1385 /* Initialize queue for changing LOOPBACK mode */
1386 INIT_WORK(&s->p[i].md_work, max310x_md_proc);
1387 /* Initialize queue for changing RS485 mode */
1388 INIT_WORK(&s->p[i].rs_work, max310x_rs_proc);
1389 /* Initialize SPI-transfer buffers */
1390 s->p[i].wr_header = (s->p[i].port.iobase + MAX310X_THR_REG) |
1391 MAX310X_WRITE_BIT;
1392 s->p[i].rd_header = (s->p[i].port.iobase + MAX310X_RHR_REG);
1393
1394 /* Register port */
1395 ret = uart_add_one_port(&max310x_uart, &s->p[i].port);
1396 if (ret) {
1397 s->p[i].port.dev = NULL;
1398 goto out_uart;
1399 }
1400 set_bit(line, max310x_lines);
1401
1402 /* Go to suspend mode */
1403 devtype->power(&s->p[i].port, 0);
1404 }
1405
1406 #ifdef CONFIG_GPIOLIB
1407 /* Setup GPIO cotroller */
1408 s->gpio.owner = THIS_MODULE;
1409 s->gpio.parent = dev;
1410 s->gpio.label = devtype->name;
1411 s->gpio.direction_input = max310x_gpio_direction_input;
1412 s->gpio.get = max310x_gpio_get;
1413 s->gpio.direction_output= max310x_gpio_direction_output;
1414 s->gpio.set = max310x_gpio_set;
1415 s->gpio.set_config = max310x_gpio_set_config;
1416 s->gpio.base = -1;
1417 s->gpio.ngpio = devtype->nr * 4;
1418 s->gpio.can_sleep = 1;
1419 ret = devm_gpiochip_add_data(dev, &s->gpio, s);
1420 if (ret)
1421 goto out_uart;
1422 #endif
1423
1424 /* Setup interrupt */
1425 ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist,
1426 IRQF_ONESHOT | IRQF_SHARED, dev_name(dev), s);
1427 if (!ret)
1428 return 0;
1429
1430 dev_err(dev, "Unable to reguest IRQ %i\n", irq);
1431
1432 out_uart:
1433 for (i = 0; i < devtype->nr; i++) {
1434 if (s->p[i].port.dev) {
1435 uart_remove_one_port(&max310x_uart, &s->p[i].port);
1436 clear_bit(s->p[i].port.line, max310x_lines);
1437 }
1438 }
1439
1440 out_clk:
1441 clk_disable_unprepare(s->clk);
1442
1443 return ret;
1444 }
1445
max310x_remove(struct device * dev)1446 static int max310x_remove(struct device *dev)
1447 {
1448 struct max310x_port *s = dev_get_drvdata(dev);
1449 int i;
1450
1451 for (i = 0; i < s->devtype->nr; i++) {
1452 cancel_work_sync(&s->p[i].tx_work);
1453 cancel_work_sync(&s->p[i].md_work);
1454 cancel_work_sync(&s->p[i].rs_work);
1455 uart_remove_one_port(&max310x_uart, &s->p[i].port);
1456 clear_bit(s->p[i].port.line, max310x_lines);
1457 s->devtype->power(&s->p[i].port, 0);
1458 }
1459
1460 clk_disable_unprepare(s->clk);
1461
1462 return 0;
1463 }
1464
1465 static const struct of_device_id __maybe_unused max310x_dt_ids[] = {
1466 { .compatible = "maxim,max3107", .data = &max3107_devtype, },
1467 { .compatible = "maxim,max3108", .data = &max3108_devtype, },
1468 { .compatible = "maxim,max3109", .data = &max3109_devtype, },
1469 { .compatible = "maxim,max14830", .data = &max14830_devtype },
1470 { }
1471 };
1472 MODULE_DEVICE_TABLE(of, max310x_dt_ids);
1473
1474 static struct regmap_config regcfg = {
1475 .reg_bits = 8,
1476 .val_bits = 8,
1477 .write_flag_mask = MAX310X_WRITE_BIT,
1478 .cache_type = REGCACHE_RBTREE,
1479 .writeable_reg = max310x_reg_writeable,
1480 .volatile_reg = max310x_reg_volatile,
1481 .precious_reg = max310x_reg_precious,
1482 };
1483
1484 #ifdef CONFIG_SPI_MASTER
max310x_spi_probe(struct spi_device * spi)1485 static int max310x_spi_probe(struct spi_device *spi)
1486 {
1487 const struct max310x_devtype *devtype;
1488 struct regmap *regmap;
1489 int ret;
1490
1491 /* Setup SPI bus */
1492 spi->bits_per_word = 8;
1493 spi->mode = spi->mode ? : SPI_MODE_0;
1494 spi->max_speed_hz = spi->max_speed_hz ? : 26000000;
1495 ret = spi_setup(spi);
1496 if (ret)
1497 return ret;
1498
1499 devtype = device_get_match_data(&spi->dev);
1500 if (!devtype)
1501 devtype = (struct max310x_devtype *)spi_get_device_id(spi)->driver_data;
1502
1503 regcfg.max_register = devtype->nr * 0x20 - 1;
1504 regmap = devm_regmap_init_spi(spi, ®cfg);
1505
1506 return max310x_probe(&spi->dev, devtype, regmap, spi->irq);
1507 }
1508
max310x_spi_remove(struct spi_device * spi)1509 static int max310x_spi_remove(struct spi_device *spi)
1510 {
1511 return max310x_remove(&spi->dev);
1512 }
1513
1514 static const struct spi_device_id max310x_id_table[] = {
1515 { "max3107", (kernel_ulong_t)&max3107_devtype, },
1516 { "max3108", (kernel_ulong_t)&max3108_devtype, },
1517 { "max3109", (kernel_ulong_t)&max3109_devtype, },
1518 { "max14830", (kernel_ulong_t)&max14830_devtype, },
1519 { }
1520 };
1521 MODULE_DEVICE_TABLE(spi, max310x_id_table);
1522
1523 static struct spi_driver max310x_spi_driver = {
1524 .driver = {
1525 .name = MAX310X_NAME,
1526 .of_match_table = max310x_dt_ids,
1527 .pm = &max310x_pm_ops,
1528 },
1529 .probe = max310x_spi_probe,
1530 .remove = max310x_spi_remove,
1531 .id_table = max310x_id_table,
1532 };
1533 #endif
1534
max310x_uart_init(void)1535 static int __init max310x_uart_init(void)
1536 {
1537 int ret;
1538
1539 bitmap_zero(max310x_lines, MAX310X_UART_NRMAX);
1540
1541 ret = uart_register_driver(&max310x_uart);
1542 if (ret)
1543 return ret;
1544
1545 #ifdef CONFIG_SPI_MASTER
1546 ret = spi_register_driver(&max310x_spi_driver);
1547 if (ret)
1548 uart_unregister_driver(&max310x_uart);
1549 #endif
1550
1551 return ret;
1552 }
1553 module_init(max310x_uart_init);
1554
max310x_uart_exit(void)1555 static void __exit max310x_uart_exit(void)
1556 {
1557 #ifdef CONFIG_SPI_MASTER
1558 spi_unregister_driver(&max310x_spi_driver);
1559 #endif
1560
1561 uart_unregister_driver(&max310x_uart);
1562 }
1563 module_exit(max310x_uart_exit);
1564
1565 MODULE_LICENSE("GPL");
1566 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1567 MODULE_DESCRIPTION("MAX310X serial driver");
1568