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Searched refs:gds (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Damdgpu_cs.c488 struct amdgpu_bo *gds; in amdgpu_cs_parser_bos() local
602 gds = p->bo_list->gds_obj; in amdgpu_cs_parser_bos()
606 if (gds) { in amdgpu_cs_parser_bos()
607 p->job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT; in amdgpu_cs_parser_bos()
608 p->job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT; in amdgpu_cs_parser_bos()
Dgfx_v9_0.c4567 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, adev->gds.gds_size); in gfx_v9_0_do_edc_gds_workarounds()
4579 adev->gds.gds_size); in gfx_v9_0_do_edc_gds_workarounds()
4801 (adev->gds.gds_size)) { in gfx_v9_0_ecc_late_init()
5427 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); in gfx_v9_0_ring_emit_ib_compute()
7090 adev->gds.gds_size = 0x10000; in gfx_v9_0_set_gds_init()
7094 adev->gds.gds_size = 0x1000; in gfx_v9_0_set_gds_init()
7100 adev->gds.gds_size = 0; in gfx_v9_0_set_gds_init()
7103 adev->gds.gds_size = 0x10000; in gfx_v9_0_set_gds_init()
7110 adev->gds.gds_compute_max_wave_id = 0x7ff; in gfx_v9_0_set_gds_init()
7113 adev->gds.gds_compute_max_wave_id = 0x27f; in gfx_v9_0_set_gds_init()
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Damdgpu_kms.c690 gds_info.compute_partition_size = adev->gds.gds_size; in amdgpu_info_ioctl()
691 gds_info.gds_total_size = adev->gds.gds_size; in amdgpu_info_ioctl()
692 gds_info.gws_per_compute_partition = adev->gds.gws_size; in amdgpu_info_ioctl()
693 gds_info.oa_per_compute_partition = adev->gds.oa_size; in amdgpu_info_ioctl()
Damdgpu_ttm.c1781 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size); in amdgpu_ttm_init()
1787 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size); in amdgpu_ttm_init()
1793 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size); in amdgpu_ttm_init()
Damdgpu_amdkfd.c660 return adev->gds.gws_size; in amdgpu_amdkfd_get_num_gws()
Dgfx_v7_0.c2310 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); in gfx_v7_0_ring_emit_ib_compute()
5154 adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE); in gfx_v7_0_set_gds_init()
5155 adev->gds.gws_size = 64; in gfx_v7_0_set_gds_init()
5156 adev->gds.oa_size = 16; in gfx_v7_0_set_gds_init()
5157 adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID); in gfx_v7_0_set_gds_init()
Dmes_v10_1.c237 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; in mes_v10_1_set_hw_resources()
Damdgpu.h995 struct amdgpu_gds gds; member
Dgfx_v8_0.c6175 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); in gfx_v8_0_ring_emit_ib_compute()
7101 adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE); in gfx_v8_0_set_gds_init()
7102 adev->gds.gws_size = 64; in gfx_v8_0_set_gds_init()
7103 adev->gds.oa_size = 16; in gfx_v8_0_set_gds_init()
7104 adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID); in gfx_v8_0_set_gds_init()
Dgfx_v10_0.c8665 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); in gfx_v10_0_ring_emit_ib_compute()
8914 gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size, in gfx_v10_0_ring_emit_de_meta()
9589 adev->gds.gds_size = 0x10000; in gfx_v10_0_set_gds_init()
9590 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; in gfx_v10_0_set_gds_init()
9591 adev->gds.gws_size = 64; in gfx_v10_0_set_gds_init()
9592 adev->gds.oa_size = 16; in gfx_v10_0_set_gds_init()